diff --git a/openfpga_flow/scripts/arch_file_updater.py b/openfpga_flow/scripts/arch_file_updater.py index 3538ec7f3f..1ef9c37868 100644 --- a/openfpga_flow/scripts/arch_file_updater.py +++ b/openfpga_flow/scripts/arch_file_updater.py @@ -26,6 +26,7 @@ ##################################################################### logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.INFO) + ##################################################################### # Upgrade an architecture XML file from version 1.1 syntax to version 1.2 # Change rules: diff --git a/openfpga_flow/scripts/io_sequence_visualizer.py b/openfpga_flow/scripts/io_sequence_visualizer.py index d80acf1f2c..cf435f217c 100644 --- a/openfpga_flow/scripts/io_sequence_visualizer.py +++ b/openfpga_flow/scripts/io_sequence_visualizer.py @@ -13,6 +13,7 @@ Author: Ganesh Gore """ + import math import svgwrite from svgwrite.container import Group diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 3ad7bec8f2..1cb3bc8a65 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -674,9 +674,11 @@ def create_yosys_params(): ys_params["READ_HDL_FILE"] += " ".join( [ "verific", - "-L " + ys_params["VERIFIC_SEARCH_LIB"] - if "VERIFIC_SEARCH_LIB" in ys_params - else "", + ( + "-L " + ys_params["VERIFIC_SEARCH_LIB"] + if "VERIFIC_SEARCH_LIB" in ys_params + else "" + ), standard, " ".join([shlex.quote(src) for src in sources]), "\n", diff --git a/requirements.txt b/requirements.txt index 889fe91591..502bfc8e0a 100644 --- a/requirements.txt +++ b/requirements.txt @@ -5,5 +5,5 @@ pyverilog # Python linter and formatter click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click) -black==20.8b1 +black==24.3.0 pylint==2.7.4