From dbd466cdec018a0c1a8b4f68db273ec0c952d537 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 25 Sep 2023 18:16:24 -0700 Subject: [PATCH] [core] now support tile port merge --- openfpga/src/fabric/build_top_module_child_tile_instance.cpp | 5 +++++ openfpga/src/fabric/build_top_module_connection.cpp | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index b4bc5e8c29..8cf04a36d9 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -1398,6 +1398,11 @@ static int build_top_module_global_net_for_given_tile_module( vpr_device_annotation.physical_tile_pin_port_info(physical_tile, grid_pin_index); VTR_ASSERT(true == grid_pin_info.is_valid()); + if (tile_annotation.is_tile_port_to_merge( + std::string(physical_tile->name), grid_pin_info.get_name()) && + subtile_index != 0) { + continue; + } /* Build nets */ for (const e_side& pin_side : pin_sides) { diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index d49a6f1cf8..48b5f1cd68 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -944,6 +944,11 @@ static int build_top_module_global_net_for_given_grid_module( vpr_device_annotation.physical_tile_pin_port_info(physical_tile, grid_pin_index); VTR_ASSERT(true == grid_pin_info.is_valid()); + if (tile_annotation.is_tile_port_to_merge( + std::string(physical_tile->name), grid_pin_info.get_name()) && + subtile_index != 0) { + continue; + } /* Build nets */ for (const e_side& pin_side : pin_sides) {