From fd99dafad7e98c4aa2331e3b5eac4e44d34d0b61 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 25 Sep 2023 16:51:01 -0700 Subject: [PATCH] [core] code format --- .../src/read_xml_tile_annotation.cpp | 8 ++++--- libs/libarchopenfpga/src/tile_annotation.cpp | 22 +++++++++++++------ libs/libarchopenfpga/src/tile_annotation.h | 9 +++++--- .../src/write_xml_tile_annotation.cpp | 9 ++++---- 4 files changed, 31 insertions(+), 17 deletions(-) diff --git a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp index d01b81b64f..135e38361a 100644 --- a/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp +++ b/libs/libarchopenfpga/src/read_xml_tile_annotation.cpp @@ -137,7 +137,7 @@ static void read_xml_tile_merge_port_annotation( const std::string& port_attr = get_attribute(xml_tile, "port", loc_data).as_string(); - + tile_annotation.add_merge_subtile_ports(tile_attr, port_attr); } @@ -165,11 +165,13 @@ openfpga::TileAnnotation read_xml_tile_annotations( if (xml_tile_global_port.name() == std::string("global_port")) { read_xml_tile_global_port_annotation(xml_tile_global_port, loc_data, tile_annotations); - } else if (xml_tile_global_port.name() == std::string("merge_subtile_ports")) { + } else if (xml_tile_global_port.name() == + std::string("merge_subtile_ports")) { read_xml_tile_merge_port_annotation(xml_tile_global_port, loc_data, tile_annotations); } else { - bad_tag(xml_tile_global_port, loc_data, xml_annotations, {"global_port or merge_subtile_ports"}); + bad_tag(xml_tile_global_port, loc_data, xml_annotations, + {"global_port or merge_subtile_ports"}); } } diff --git a/libs/libarchopenfpga/src/tile_annotation.cpp b/libs/libarchopenfpga/src/tile_annotation.cpp index 0ea6c5d8d5..1cc1bd8810 100644 --- a/libs/libarchopenfpga/src/tile_annotation.cpp +++ b/libs/libarchopenfpga/src/tile_annotation.cpp @@ -2,9 +2,10 @@ * Member functions for class TileAnnotation ***********************************************************************/ #include "tile_annotation.h" -#include "command_exit_codes.h" + #include +#include "command_exit_codes.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -25,17 +26,20 @@ TileAnnotation::global_port_range TileAnnotation::global_ports() const { std::vector TileAnnotation::tiles_to_merge_ports() const { std::vector tile_names; - for (auto it = tile_ports_to_merge_.begin(); it != tile_ports_to_merge_.end(); it++) { + for (auto it = tile_ports_to_merge_.begin(); it != tile_ports_to_merge_.end(); + it++) { tile_names.push_back(it->first); } return tile_names; } -std::vector TileAnnotation::tile_ports_to_merge(const std::string& tile_name) const { +std::vector TileAnnotation::tile_ports_to_merge( + const std::string& tile_name) const { std::vector port_names; const auto& result = tile_ports_to_merge_.find(tile_name); if (result == tile_ports_to_merge_.end()) { - VTR_LOG_WARN("Tile '%s' does not contain any ports to merge!\n", tile_name.c_str()); + VTR_LOG_WARN("Tile '%s' does not contain any ports to merge!\n", + tile_name.c_str()); return port_names; } return result->second; @@ -199,17 +203,21 @@ bool TileAnnotation::valid_global_port_attributes( return ((0 == attribute_counter) || (1 == attribute_counter)); } -int TileAnnotation::add_merge_subtile_ports(const std::string& tile_name, const std::string& port_name) { +int TileAnnotation::add_merge_subtile_ports(const std::string& tile_name, + const std::string& port_name) { auto result = tile_ports_to_merge_.find(tile_name); if (result == tile_ports_to_merge_.end()) { /* Empty list: add a new element */ tile_ports_to_merge_[tile_name].push_back(port_name); } else { /* Check if the port name is already in the list, if yes, error out */ - if (result->second.end() == std::find(result->second.begin(), result->second.end(), port_name)) { + if (result->second.end() == + std::find(result->second.begin(), result->second.end(), port_name)) { tile_ports_to_merge_[tile_name].push_back(port_name); } else { - VTR_LOG_ERROR("Port '%s' has already been defined twice for tile '%s' to be merged!", port_name.c_str(), tile_name.c_str()); + VTR_LOG_ERROR( + "Port '%s' has already been defined twice for tile '%s' to be merged!", + port_name.c_str(), tile_name.c_str()); return CMD_EXEC_FATAL_ERROR; } } diff --git a/libs/libarchopenfpga/src/tile_annotation.h b/libs/libarchopenfpga/src/tile_annotation.h index de5a40a082..c92372f8cb 100644 --- a/libs/libarchopenfpga/src/tile_annotation.h +++ b/libs/libarchopenfpga/src/tile_annotation.h @@ -40,7 +40,8 @@ class TileAnnotation { public: /* Public accessors: aggregators */ global_port_range global_ports() const; std::vector tiles_to_merge_ports() const; - std::vector tile_ports_to_merge(const std::string& tile_name) const; + std::vector tile_ports_to_merge( + const std::string& tile_name) const; public: /* Public accessors */ std::string global_port_name(const TileGlobalPortId& global_port_id) const; @@ -79,7 +80,8 @@ class TileAnnotation { void set_global_port_default_value(const TileGlobalPortId& global_port_id, const size_t& default_value); - int add_merge_subtile_ports(const std::string& tile_name, const std::string& port_name); + int add_merge_subtile_ports(const std::string& tile_name, + const std::string& port_name); public: /* Public validator */ bool valid_global_port_id(const TileGlobalPortId& global_port_id) const; @@ -108,7 +110,8 @@ class TileAnnotation { std::map global_port_name2ids_; /* Merge port information for tiles */ - std::map> tile_ports_to_merge_; // tile_name -> port_name + std::map> + tile_ports_to_merge_; // tile_name -> port_name }; } // namespace openfpga diff --git a/libs/libarchopenfpga/src/write_xml_tile_annotation.cpp b/libs/libarchopenfpga/src/write_xml_tile_annotation.cpp index 5bccbc2c69..9db2e01b7b 100644 --- a/libs/libarchopenfpga/src/write_xml_tile_annotation.cpp +++ b/libs/libarchopenfpga/src/write_xml_tile_annotation.cpp @@ -91,8 +91,7 @@ static void write_xml_tile_annotation_global_port( * A writer to output a device variation in a technology library to XML format *******************************************************************/ static void write_xml_tile_annotation_subtile_port_to_merge( - std::fstream& fp, const char* fname, - const std::string& tile_name, + std::fstream& fp, const char* fname, const std::string& tile_name, const std::string& port_name) { /* Validate the file stream */ openfpga::check_file_stream(fname, fp); @@ -129,8 +128,10 @@ void write_xml_tile_annotations(std::fstream& fp, const char* fname, global_port_id); } for (std::string tile_name : tile_annotation.tiles_to_merge_ports()) { - for (std::string port_name : tile_annotation.tile_ports_to_merge(tile_name)) { - write_xml_tile_annotation_subtile_port_to_merge(fp, fname, tile_name, port_name); + for (std::string port_name : + tile_annotation.tile_ports_to_merge(tile_name)) { + write_xml_tile_annotation_subtile_port_to_merge(fp, fname, tile_name, + port_name); } }