Support merging subtile ports in fabric modeling

[tangxifan]

Is your feature request related to a problem? Please describe.
Currently, when a tile consists of a number of subtiles, each subtile has an independent set of ports. For example, an I/O tile consists of 4 subtiles, each of which contains 8 clocks.

Here is a short example on the architecture:

    <tile name="io_top" area="0">
      <sub_tile name="io_top_pi" capacity="4">
        <equivalent_sites>
          <site pb_type="io_pi"/>
        </equivalent_sites>
        <clock name="clk" num_pins="8"/>
        <output name="a2f_o" num_pins="1"/>
        <input name="reset" num_pins="1" is_non_clock_global="true"/>
        <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
          <fc_override port_name="clk" fc_type="frac" fc_val="0"/>
          <fc_override port_name="reset" fc_type="frac" fc_val="0"/>
        </fc>
        <pinlocations pattern="custom">
          <loc side="top">io_top_pi[5:0].a2f_o</loc>
          <loc side="right">io_top_pi[11:6].a2f_o</loc>
          <loc side="left"/>
          <loc side="bottom">io_top_pi.clk io_top_pi.reset</loc>
        </pinlocations>
      </sub_tile>

On the I/O tile, we see the following

module grid_io(config_enable,
                    prog_reset,
                    prog_clk,
                    gfpga_pad_pinput_A2F,
                    gfpga_pad_poutput_F2A,
                    bottom_width_0_height_0_subtile_0__pin_reset_0_,
                    bottom_width_0_height_0_subtile_0__pin_clk_0_,
                    bottom_width_0_height_0_subtile_0__pin_clk_1_,
                    bottom_width_0_height_0_subtile_0__pin_clk_2_,
                    bottom_width_0_height_0_subtile_0__pin_clk_3_,
                    bottom_width_0_height_0_subtile_0__pin_clk_4_,
                    bottom_width_0_height_0_subtile_0__pin_clk_5_,
                    bottom_width_0_height_0_subtile_0__pin_clk_6_,
                    bottom_width_0_height_0_subtile_0__pin_clk_7_,
                    bottom_width_0_height_0_subtile_1__pin_reset_0_,
                    bottom_width_0_height_0_subtile_1__pin_clk_0_,
                    bottom_width_0_height_0_subtile_1__pin_clk_1_,
                    bottom_width_0_height_0_subtile_1__pin_clk_2_,
                    bottom_width_0_height_0_subtile_1__pin_clk_3_,
                    bottom_width_0_height_0_subtile_1__pin_clk_4_,
                    bottom_width_0_height_0_subtile_1__pin_clk_5_,
                    bottom_width_0_height_0_subtile_1__pin_clk_6_,
                    bottom_width_0_height_0_subtile_1__pin_clk_7_,
                    bottom_width_0_height_0_subtile_2__pin_reset_0_,
                    bottom_width_0_height_0_subtile_2__pin_clk_0_,
                    bottom_width_0_height_0_subtile_2__pin_clk_1_,
                    bottom_width_0_height_0_subtile_2__pin_clk_2_,
                    bottom_width_0_height_0_subtile_2__pin_clk_3_,
                    bottom_width_0_height_0_subtile_2__pin_clk_4_,
                    bottom_width_0_height_0_subtile_2__pin_clk_5_,
                    bottom_width_0_height_0_subtile_2__pin_clk_6_,
                    bottom_width_0_height_0_subtile_2__pin_clk_7_,
                    bottom_width_0_height_0_subtile_3__pin_reset_0_,
                    bottom_width_0_height_0_subtile_3__pin_clk_0_,
                    bottom_width_0_height_0_subtile_3__pin_clk_1_,
                    bottom_width_0_height_0_subtile_3__pin_clk_2_,
                    bottom_width_0_height_0_subtile_3__pin_clk_3_,
                    bottom_width_0_height_0_subtile_3__pin_clk_4_,
                    bottom_width_0_height_0_subtile_3__pin_clk_5_,
                    bottom_width_0_height_0_subtile_3__pin_clk_6_,
                    bottom_width_0_height_0_subtile_3__pin_clk_7_);

This leads to serious physical design problems when we performing P&R on a tile. All these pins have to be placed on the boundary of a tile. However, when the number of pins is large, the tile perimeter may not be sufficient. In such case, we have to increase the physical dimension of a tile in order to accommodate all the pins. This comes with a serious degradation on the area and low utilization rate (I/O tiles do not carry a lot of logics typically).

Describe the solution you'd like
Actually, some of the ports can be merged without impacting functionality. Take the example above, all these clocks and reset can be merged across all the subtiles in an I/O tile.
The net merging can be applied in side an I/O tile. The resulting netlist may look like:

module grid_io(config_enable,
                    prog_reset,
                    prog_clk,
                    gfpga_pad_pinput_A2F,
                    gfpga_pad_poutput_F2A,
                    bottom_width_0_height_0_pin_reset_0_,
                    bottom_width_0_height_0_pin_clk_0_,
                    bottom_width_0_height_0_pin_clk_1_,
                    bottom_width_0_height_0_pin_clk_2_,
                    bottom_width_0_height_0_pin_clk_3_,
                    bottom_width_0_height_0_pin_clk_4_,
                    bottom_width_0_height_0_pin_clk_5_,
                    bottom_width_0_height_0_pin_clk_6_,
                    bottom_width_0_height_0_pin_clk_7_);

To offer flexiblity to users, the following syntax can be added to tile annotation:

<tile_annotation>
  <merge_subtile_ports tile="io" port="clk"/>
  <merge_subtile_ports tile="io" port="reset"/>
</tile_annotation>

Note that the merging can be ONLY applied to the ports whose Fc is 0!!!