From deed17d73616931a433004aefa05e85c5fe0aae4 Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Sun, 3 Mar 2024 22:16:58 -0800 Subject: [PATCH 1/6] Preserve escaped names --- .../fpga_verilog/verilog_testbench_utils.cpp | 38 +++++++++++++------ .../src/fpga_verilog/verilog_writer_utils.cpp | 4 +- .../src/fpga_verilog/verilog_writer_utils.h | 2 + 3 files changed, 30 insertions(+), 14 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 4dbb879c94..66a4773465 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -116,6 +116,14 @@ void print_verilog_testbench_fpga_instance( fp << std::endl; } +std::string escapeNames(const std::string& original) { + std::string result = original; + if (result.find("$") != std::string::npos) { + result = "\\" + result + " "; + } + return result; +} + /******************************************************************** * Instanciate the input benchmark module *******************************************************************/ @@ -224,17 +232,18 @@ void print_verilog_testbench_benchmark_instance( fp << "~"; } - fp << bus_group.pin_name(pin); + std::string escapedName = bus_group.pin_name(pin); /* For clock ports, skip postfix */ if (clock_port_names.end() == std::find(clock_port_names.begin(), clock_port_names.end(), port_names[iport])) { - fp << input_port_postfix; + escapedName += input_port_postfix; } else if (include_clock_port_postfix) { - fp << input_port_postfix; + escapedName += input_port_postfix; } - + escapedName = escapeNames(escapedName); + fp << escapedName; pin_counter++; } fp << "}"; @@ -249,16 +258,17 @@ void print_verilog_testbench_benchmark_instance( pin_constraints.net_default_value(port_names[iport])) { fp << "~"; } - - fp << port_names[iport]; + std::string escapedName = port_names[iport]; /* For clock ports, skip postfix */ if (clock_port_names.end() == std::find(clock_port_names.begin(), clock_port_names.end(), port_names[iport])) { - fp << input_port_postfix; + escapedName += input_port_postfix; } else if (include_clock_port_postfix) { - fp << input_port_postfix; + escapedName += input_port_postfix; } + escapedName = escapeNames(escapedName); + fp << escapedName; } if (true == use_explicit_port_map) { @@ -286,12 +296,16 @@ void print_verilog_testbench_benchmark_instance( if (0 < pin_counter) { fp << ", "; } - fp << bus_group.pin_name(pin) << output_port_postfix; + std::string escapedName = bus_group.pin_name(pin) + output_port_postfix; + escapedName = escapeNames(escapedName); + fp << escapedName; pin_counter++; } fp << "}"; } else { - fp << port_names[iport] << output_port_postfix; + std::string escapedName = port_names[iport] + output_port_postfix; + escapedName = escapeNames(escapedName); + fp << escapedName; } if (true == use_explicit_port_map) { fp << ")"; @@ -867,7 +881,7 @@ void print_verilog_testbench_random_stimuli( /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << block_name + input_port_postfix << " <= 1'b0;" + fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= 1'b0;" << std::endl; } } @@ -951,7 +965,7 @@ void print_verilog_testbench_random_stimuli( /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << block_name + input_port_postfix << " <= $random;" + fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= $random;" << std::endl; } } diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index dd95205de4..20a29d2720 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -533,10 +533,10 @@ std::string generate_verilog_port( } else if ((1 == port_info.get_width())) { size_str = "[" + std::to_string(port_info.get_lsb()) + "]"; } - verilog_line = port_info.get_name() + size_str; + verilog_line = escapeNames(port_info.get_name()) + size_str; } else { verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type]; - verilog_line += " " + size_str + " " + port_info.get_name(); + verilog_line += " " + size_str + " " + escapeNames(port_info.get_name()); } return verilog_line; diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index 665f191a2d..81e21b353b 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -199,6 +199,8 @@ void print_verilog_netlist_include_header_file( const char* subckt_dir, const char* header_file_name, const bool& include_time_stamp); +std::string escapeNames(const std::string& name); + } /* end namespace openfpga */ #endif From a3d627b21fd7b9c3999c619838bef9b9d64e4a29 Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Mon, 4 Mar 2024 09:27:12 -0800 Subject: [PATCH 2/6] Preserve escaped names --- .../fpga_verilog/verilog_testbench_utils.cpp | 334 +++++++++--------- 1 file changed, 168 insertions(+), 166 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 66a4773465..2e781afacc 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -35,16 +35,16 @@ namespace openfpga { ); *******************************************************************/ void print_verilog_testbench_fpga_instance( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const ModuleId& core_module, - const std::string& top_instance_name, const std::string& net_postfix, - const IoNameMap& io_name_map, const bool& explicit_port_mapping) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const ModuleId& core_module, + const std::string& top_instance_name, const std::string& net_postfix, + const IoNameMap& io_name_map, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); /* Include defined top-level module */ print_verilog_comment( - fp, std::string("----- FPGA top-level module to be capsulated -----")); + fp, std::string("----- FPGA top-level module to be capsulated -----")); /* Precheck on the top module and decide if we need to consider I/O naming * - If we do have a fpga_core module added, and dut is fpga_top, we need a @@ -68,7 +68,7 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); BasicPort net_port = module_port; net_port.set_name(module_port.get_name() + net_postfix); port2port_name_map[module_port.get_name()] = net_port; @@ -81,11 +81,11 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); /* Bypass dummy port: the port does not exist at core module */ if (io_name_map.fpga_top_port_is_dummy(module_port)) { - ModulePortId core_module_port = - module_manager.find_module_port(core_module, module_port.get_name()); + ModulePortId core_module_port = module_manager.find_module_port( + core_module, module_port.get_name()); if (!module_manager.valid_module_port_id(core_module, core_module_port)) { /* Print the wire for the dummy port */ @@ -128,16 +128,17 @@ std::string escapeNames(const std::string& original) { * Instanciate the input benchmark module *******************************************************************/ void print_verilog_testbench_benchmark_instance( - std::fstream& fp, const std::string& module_name, - const std::string& instance_name, - const std::string& module_input_port_postfix, - const std::string& module_output_port_postfix, - const std::string& input_port_postfix, const std::string& output_port_postfix, - const std::vector& clock_port_names, - const bool& include_clock_port_postfix, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const PinConstraints& pin_constraints, const BusGroup& bus_group, - const bool& use_explicit_port_map) { + std::fstream& fp, const std::string& module_name, + const std::string& instance_name, + const std::string& module_input_port_postfix, + const std::string& module_output_port_postfix, + const std::string& input_port_postfix, + const std::string& output_port_postfix, + const std::vector& clock_port_names, + const bool& include_clock_port_postfix, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const BusGroup& bus_group, + const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -267,7 +268,7 @@ void print_verilog_testbench_benchmark_instance( } else if (include_clock_port_postfix) { escapedName += input_port_postfix; } - escapedName = escapeNames(escapedName); + escapedName = escapeNames(escapedName); fp << escapedName; } @@ -296,8 +297,9 @@ void print_verilog_testbench_benchmark_instance( if (0 < pin_counter) { fp << ", "; } - std::string escapedName = bus_group.pin_name(pin) + output_port_postfix; - escapedName = escapeNames(escapedName); + std::string escapedName = + bus_group.pin_name(pin) + output_port_postfix; + escapedName = escapeNames(escapedName); fp << escapedName; pin_counter++; } @@ -326,15 +328,15 @@ void print_verilog_testbench_benchmark_instance( * by default *******************************************************************/ void print_verilog_testbench_connect_fpga_ios( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const AtomContext& atom_ctx, - const PlacementContext& place_ctx, const IoLocationMap& io_location_map, - const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, - const std::string& net_name_postfix, - const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix, - const std::vector& clock_port_names, - const size_t& unused_io_value) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const AtomContext& atom_ctx, + const PlacementContext& place_ctx, const IoLocationMap& io_location_map, + const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, + const std::string& net_name_postfix, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, + const std::vector& clock_port_names, + const size_t& unused_io_value) { /* Validate the file stream */ valid_file_stream(fp); @@ -358,25 +360,25 @@ void print_verilog_testbench_connect_fpga_ios( std::map> io_used; for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); io_used[module_io_port_id] = - std::vector(module_io_port.get_width(), false); + std::vector(module_io_port.get_width(), false); } /* Type mapping between VPR block and Module port */ std::map - atom_block_type_to_module_port_type; + atom_block_type_to_module_port_type; atom_block_type_to_module_port_type[AtomBlockType::INPAD] = - ModuleManager::MODULE_GPIN_PORT; + ModuleManager::MODULE_GPIN_PORT; atom_block_type_to_module_port_type[AtomBlockType::OUTPAD] = - ModuleManager::MODULE_GPOUT_PORT; + ModuleManager::MODULE_GPOUT_PORT; /* See if this I/O should be wired to a benchmark input/output */ /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs * This brings convenience to checking functionality */ print_verilog_comment( - fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); + fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* Bypass non-I/O atom blocks ! */ @@ -390,17 +392,17 @@ void print_verilog_testbench_connect_fpga_ios( * or should find a GPOUT for OUTPAD */ std::pair mapped_module_io_info = - std::make_pair(ModulePortId::INVALID(), -1); + std::make_pair(ModulePortId::INVALID(), -1); for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, - module_io_port.get_name()); + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ if (size_t(-1) == temp_io_index) { @@ -411,28 +413,28 @@ void print_verilog_testbench_connect_fpga_ios( if (ModuleManager::MODULE_GPIO_PORT == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } /* If this is an INPAD, we can use an GPIN port (if available) */ if (atom_block_type_to_module_port_type[atom_ctx.nlist.block_type( - atom_blk)] == + atom_blk)] == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } } /* We must find a valid one */ VTR_ASSERT(true == module_manager.valid_module_port_id( - top_module, mapped_module_io_info.first)); + top_module, mapped_module_io_info.first)); VTR_ASSERT(size_t(-1) != mapped_module_io_info.second); /* Ensure that IO index is in range */ BasicPort module_mapped_io_port = - module_manager.module_port(top_module, mapped_module_io_info.first); + module_manager.module_port(top_module, mapped_module_io_info.first); size_t io_index = mapped_module_io_info.second; /* Set the port pin index */ @@ -482,24 +484,24 @@ void print_verilog_testbench_connect_fpga_ios( benchmark_io_port.set_name(block_name); } else { benchmark_io_port.set_name( - std::string(block_name + io_input_port_name_postfix)); + std::string(block_name + io_input_port_name_postfix)); } print_verilog_comment( - fp, std::string("----- Blif Benchmark input " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark input " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); } else { VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)); benchmark_io_port.set_name( - std::string(block_name + io_output_port_name_postfix)); + std::string(block_name + io_output_port_name_postfix)); print_verilog_comment( - fp, std::string("----- Blif Benchmark output " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark output " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); } @@ -513,7 +515,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire the unused iopads to a constant */ print_verilog_comment( - fp, std::string("----- Wire unused FPGA I/Os to constants -----")); + fp, std::string("----- Wire unused FPGA I/Os to constants -----")); for (const ModulePortId& module_io_port_id : module_io_ports) { for (size_t io_index = 0; io_index < io_used[module_io_port_id].size(); ++io_index) { @@ -530,7 +532,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire to a contant */ BasicPort module_unused_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Set the port pin index */ module_unused_io_port.set_name(module_unused_io_port.get_name() + net_name_postfix); @@ -554,16 +556,16 @@ void print_verilog_testbench_connect_fpga_ios( * Note that: these codes are tuned for Icarus simulator!!! *******************************************************************/ void print_verilog_timeout_and_vcd( - std::fstream& fp, const std::string& module_name, - const std::string& vcd_fname, - const std::string& simulation_start_counter_name, - const std::string& error_counter_name, const float& simulation_time, - const bool& no_self_checking) { + std::fstream& fp, const std::string& module_name, + const std::string& vcd_fname, + const std::string& simulation_start_counter_name, + const std::string& error_counter_name, const float& simulation_time, + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_comment( - fp, std::string("----- Begin output waveform to VCD file-------")); + fp, std::string("----- Begin output waveform to VCD file-------")); fp << "\tinitial begin" << std::endl; fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl; @@ -571,7 +573,7 @@ void print_verilog_timeout_and_vcd( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("----- END output waveform to VCD file -------")); + fp, std::string("----- END output waveform to VCD file -------")); /* Add an empty line as splitter */ fp << std::endl; @@ -588,8 +590,8 @@ void print_verilog_timeout_and_vcd( fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; fp << "\t$display(\"Simulation start\");" << std::endl; print_verilog_comment( - fp, - std::string("----- Can be changed by the user for his/her need -------")); + fp, + std::string("----- Can be changed by the user for his/her need -------")); fp << "\t#" << std::setprecision(10) << simulation_time << std::endl; if (!no_self_checking) { @@ -618,8 +620,8 @@ void print_verilog_timeout_and_vcd( * Assume this is a single clock benchmark *******************************************************************/ std::vector generate_verilog_testbench_clock_port( - const std::vector& clock_port_names, - const std::string& default_clock_name) { + const std::vector& clock_port_names, + const std::string& default_clock_name) { std::vector clock_ports; if (0 == clock_port_names.size()) { clock_ports.push_back(BasicPort(default_clock_name, 1)); @@ -638,23 +640,23 @@ std::vector generate_verilog_testbench_clock_port( * Restriction: this function only supports single clock benchmarks! *******************************************************************/ void print_verilog_testbench_check( - std::fstream& fp, const std::string& simulation_start_counter_name, - const std::string& benchmark_port_postfix, - const std::string& fpga_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& config_done_name, const std::string& error_counter_name, - const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& default_clock_name) { + std::fstream& fp, const std::string& simulation_start_counter_name, + const std::string& benchmark_port_postfix, + const std::string& fpga_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& config_done_name, const std::string& error_counter_name, + const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& default_clock_name) { /* Validate the file stream */ valid_file_stream(fp); /* Add output autocheck */ print_verilog_comment( - fp, std::string("----- Begin checking output vectors -------")); + fp, std::string("----- Begin checking output vectors -------")); - std::vector clock_ports = - generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); + std::vector clock_ports = generate_verilog_testbench_clock_port( + clock_port_names, default_clock_name); print_verilog_comment(fp, std::string("----- Skip the first falling edge of " @@ -764,21 +766,21 @@ void print_verilog_testbench_check( * but be only used as a synchronizer in verification *******************************************************************/ void print_verilog_testbench_clock_stimuli( - std::fstream& fp, const PinConstraints& pin_constraints, - const SimulationSetting& simulation_parameters, - const std::vector& clock_ports) { + std::fstream& fp, const PinConstraints& pin_constraints, + const SimulationSetting& simulation_parameters, + const std::vector& clock_ports) { /* Validate the file stream */ valid_file_stream(fp); for (const BasicPort& clock_port : clock_ports) { print_verilog_comment(fp, std::string("----- Clock '") + - clock_port.get_name() + - std::string("' Initialization -------")); + clock_port.get_name() + + std::string("' Initialization -------")); /* Find the corresponding clock frequency from the simulation parameters */ float clk_freq_to_use = - (0.5 / simulation_parameters.default_operating_clock_frequency()) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.default_operating_clock_frequency()) / + VERILOG_SIM_TIMESCALE; /* Check pin constraints to see if this clock is constrained to a specific * pin If constrained, * - connect this clock to default values if it is set to be OPEN @@ -800,8 +802,8 @@ void print_verilog_testbench_clock_stimuli( if (pin_constraints.pin(pin_constraint) == simulation_parameters.clock_port(sim_clock_id)) { clk_freq_to_use = - (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / + VERILOG_SIM_TIMESCALE; } } } @@ -830,15 +832,15 @@ void print_verilog_testbench_clock_stimuli( * For clock signals, please use print_verilog_testbench_clock_stimuli *******************************************************************/ void print_verilog_testbench_random_stimuli( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, - const std::vector& clock_port_names, - const std::string& input_port_postfix, - const std::string& check_flag_port_postfix, - const std::vector& clock_ports, const bool& no_self_checking) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, + const std::vector& clock_port_names, + const std::string& input_port_postfix, + const std::string& check_flag_port_postfix, + const std::vector& clock_ports, const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -874,15 +876,15 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= 1'b0;" - << std::endl; + fp << "\t\t" << escapeNames(block_name + input_port_postfix) + << " <= 1'b0;" << std::endl; } } @@ -958,15 +960,15 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= $random;" - << std::endl; + fp << "\t\t" << escapeNames(block_name + input_port_postfix) + << " <= $random;" << std::endl; } } @@ -984,14 +986,14 @@ void print_verilog_testbench_random_stimuli( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_input_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const bool& include_clock_ports, const std::string& shared_input_port_postfix, - const bool& use_reg_port) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const bool& include_clock_ports, + const std::string& shared_input_port_postfix, const bool& use_reg_port) { /* Validate the file stream */ valid_file_stream(fp); @@ -1023,8 +1025,8 @@ void print_verilog_testbench_shared_input_ports( BasicPort input_port(block_name + shared_input_port_postfix, 1); /* For global ports, use wires; otherwise, use registers*/ if (false == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { if (use_reg_port) { fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; @@ -1048,9 +1050,9 @@ void print_verilog_testbench_shared_input_ports( * 2. the output ports (wires) for FPGA fabric *******************************************************************/ void print_verilog_testbench_shared_fpga_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& fpga_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& fpga_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1088,9 +1090,9 @@ void print_verilog_testbench_shared_fpga_output_ports( * 2. the output ports (wires) for benchmark instance *******************************************************************/ void print_verilog_testbench_shared_benchmark_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& benchmark_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& benchmark_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1112,7 +1114,7 @@ void print_verilog_testbench_shared_benchmark_output_ports( /* Each logical block assumes a single-width port */ BasicPort output_port( - std::string(block_name + benchmark_output_port_postfix), 1); + std::string(block_name + benchmark_output_port_postfix), 1); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; } @@ -1131,15 +1133,15 @@ void print_verilog_testbench_shared_benchmark_output_ports( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_check_flags( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& check_flag_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& check_flag_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); /* Instantiate register for output comparison */ print_verilog_comment( - fp, std::string("----- Output vectors checking flags -------")); + fp, std::string("----- Output vectors checking flags -------")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* We care only those logic blocks which are output I/Os */ if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { @@ -1174,30 +1176,30 @@ void print_verilog_testbench_shared_check_flags( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& shared_input_port_postfix, - const std::string& benchmark_output_port_postfix, - const std::string& fpga_output_port_postfix, - const std::string& check_flag_port_postfix, const bool& no_self_checking) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& shared_input_port_postfix, + const std::string& benchmark_output_port_postfix, + const std::string& fpga_output_port_postfix, + const std::string& check_flag_port_postfix, const bool& no_self_checking) { print_verilog_testbench_shared_input_ports( - fp, module_manager, module_name_map, global_ports, pin_constraints, - atom_ctx, netlist_annotation, clock_port_names, false, - shared_input_port_postfix, true); + fp, module_manager, module_name_map, global_ports, pin_constraints, + atom_ctx, netlist_annotation, clock_port_names, false, + shared_input_port_postfix, true); print_verilog_testbench_shared_fpga_output_ports( - fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); + fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); if (no_self_checking) { return; } print_verilog_testbench_shared_benchmark_output_ports( - fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); + fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); print_verilog_testbench_shared_check_flags(fp, atom_ctx, netlist_annotation, check_flag_port_postfix); @@ -1212,11 +1214,11 @@ void print_verilog_testbench_shared_ports( * in the graph of modules *******************************************************************/ static void rec_print_verilog_testbench_primitive_module_signal_initialization( - std::fstream& fp, const std::string& hie_path, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, - const std::vector& circuit_input_ports, - const ModuleManager& module_manager, const ModuleId& parent_module, - const ModuleId& primitive_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& hie_path, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const std::vector& circuit_input_ports, + const ModuleManager& module_manager, const ModuleId& parent_module, + const ModuleId& primitive_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1234,20 +1236,20 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) { std::string instance_name = module_manager.instance_name( - parent_module, child_module, child_instance); + parent_module, child_module, child_instance); /* Use default instanec name if not assigned */ if (true == instance_name.empty()) { instance_name = generate_instance_name( - module_manager.module_name(child_module), child_instance); + module_manager.module_name(child_module), child_instance); } std::string child_hie_path = hie_path + "." + instance_name; if (child_module != primitive_module) { rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, - module_manager, child_module, primitive_module, - deposit_random_values); + fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, + module_manager, child_module, primitive_module, + deposit_random_values); } else { /* If the child module is the primitive module, * we output the signal initialization codes for the input ports @@ -1255,7 +1257,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( VTR_ASSERT_SAFE(child_module == primitive_module); print_verilog_comment( - fp, std::string("------ BEGIN driver initialization -----")); + fp, std::string("------ BEGIN driver initialization -----")); fp << "\tinitial begin" << std::endl; for (const auto& input_port : circuit_input_ports) { @@ -1281,7 +1283,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("------ END driver initialization -----")); + fp, std::string("------ END driver initialization -----")); } } } @@ -1295,9 +1297,9 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( * - Logic gates (ONLY for MUX2) *******************************************************************/ void print_verilog_testbench_signal_initialization( - std::fstream& fp, const std::string& top_instance_name, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& top_instance_name, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, + const ModuleId& top_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1306,7 +1308,7 @@ void print_verilog_testbench_signal_initialization( /* Collect the input ports that require signal initialization */ std::map> - signal_init_circuit_ports; + signal_init_circuit_ports; for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_PASSGATE)) { @@ -1315,7 +1317,7 @@ void print_verilog_testbench_signal_initialization( * which is the first port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(0 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); } @@ -1328,7 +1330,7 @@ void print_verilog_testbench_signal_initialization( * which is the first two port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(1 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); signal_init_circuit_ports[model].push_back(input_ports[1]); @@ -1347,14 +1349,14 @@ void print_verilog_testbench_signal_initialization( /* Find the module id corresponding to the circuit model from module graph */ ModuleId primitive_module = module_manager.find_module( - circuit_lib.model_name(signal_init_circuit_model)); + circuit_lib.model_name(signal_init_circuit_model)); VTR_ASSERT(true == module_manager.valid_module_id(primitive_module)); /* Find all the instances created by the circuit model across the fabric*/ rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, top_instance_name, circuit_lib, signal_init_circuit_model, - signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, - top_module, primitive_module, deposit_random_values); + fp, top_instance_name, circuit_lib, signal_init_circuit_model, + signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, + top_module, primitive_module, deposit_random_values); } } From 9d64d8e678b886ff18ffaa976aa8d827850a4a31 Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Sun, 3 Mar 2024 22:16:58 -0800 Subject: [PATCH 3/6] Preserve escaped names --- .../fpga_verilog/verilog_testbench_utils.cpp | 38 +++++++++++++------ .../src/fpga_verilog/verilog_writer_utils.cpp | 4 +- .../src/fpga_verilog/verilog_writer_utils.h | 2 + 3 files changed, 30 insertions(+), 14 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 4dbb879c94..66a4773465 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -116,6 +116,14 @@ void print_verilog_testbench_fpga_instance( fp << std::endl; } +std::string escapeNames(const std::string& original) { + std::string result = original; + if (result.find("$") != std::string::npos) { + result = "\\" + result + " "; + } + return result; +} + /******************************************************************** * Instanciate the input benchmark module *******************************************************************/ @@ -224,17 +232,18 @@ void print_verilog_testbench_benchmark_instance( fp << "~"; } - fp << bus_group.pin_name(pin); + std::string escapedName = bus_group.pin_name(pin); /* For clock ports, skip postfix */ if (clock_port_names.end() == std::find(clock_port_names.begin(), clock_port_names.end(), port_names[iport])) { - fp << input_port_postfix; + escapedName += input_port_postfix; } else if (include_clock_port_postfix) { - fp << input_port_postfix; + escapedName += input_port_postfix; } - + escapedName = escapeNames(escapedName); + fp << escapedName; pin_counter++; } fp << "}"; @@ -249,16 +258,17 @@ void print_verilog_testbench_benchmark_instance( pin_constraints.net_default_value(port_names[iport])) { fp << "~"; } - - fp << port_names[iport]; + std::string escapedName = port_names[iport]; /* For clock ports, skip postfix */ if (clock_port_names.end() == std::find(clock_port_names.begin(), clock_port_names.end(), port_names[iport])) { - fp << input_port_postfix; + escapedName += input_port_postfix; } else if (include_clock_port_postfix) { - fp << input_port_postfix; + escapedName += input_port_postfix; } + escapedName = escapeNames(escapedName); + fp << escapedName; } if (true == use_explicit_port_map) { @@ -286,12 +296,16 @@ void print_verilog_testbench_benchmark_instance( if (0 < pin_counter) { fp << ", "; } - fp << bus_group.pin_name(pin) << output_port_postfix; + std::string escapedName = bus_group.pin_name(pin) + output_port_postfix; + escapedName = escapeNames(escapedName); + fp << escapedName; pin_counter++; } fp << "}"; } else { - fp << port_names[iport] << output_port_postfix; + std::string escapedName = port_names[iport] + output_port_postfix; + escapedName = escapeNames(escapedName); + fp << escapedName; } if (true == use_explicit_port_map) { fp << ")"; @@ -867,7 +881,7 @@ void print_verilog_testbench_random_stimuli( /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << block_name + input_port_postfix << " <= 1'b0;" + fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= 1'b0;" << std::endl; } } @@ -951,7 +965,7 @@ void print_verilog_testbench_random_stimuli( /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << block_name + input_port_postfix << " <= $random;" + fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= $random;" << std::endl; } } diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index dd95205de4..20a29d2720 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -533,10 +533,10 @@ std::string generate_verilog_port( } else if ((1 == port_info.get_width())) { size_str = "[" + std::to_string(port_info.get_lsb()) + "]"; } - verilog_line = port_info.get_name() + size_str; + verilog_line = escapeNames(port_info.get_name()) + size_str; } else { verilog_line = VERILOG_PORT_TYPE_STRING[verilog_port_type]; - verilog_line += " " + size_str + " " + port_info.get_name(); + verilog_line += " " + size_str + " " + escapeNames(port_info.get_name()); } return verilog_line; diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h index 665f191a2d..81e21b353b 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.h +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h @@ -199,6 +199,8 @@ void print_verilog_netlist_include_header_file( const char* subckt_dir, const char* header_file_name, const bool& include_time_stamp); +std::string escapeNames(const std::string& name); + } /* end namespace openfpga */ #endif From 23e3e29019af1cd22c3fa2691519e610fd14acd8 Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Mon, 4 Mar 2024 09:27:12 -0800 Subject: [PATCH 4/6] Preserve escaped names --- .../fpga_verilog/verilog_testbench_utils.cpp | 334 +++++++++--------- 1 file changed, 168 insertions(+), 166 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 66a4773465..2e781afacc 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -35,16 +35,16 @@ namespace openfpga { ); *******************************************************************/ void print_verilog_testbench_fpga_instance( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const ModuleId& core_module, - const std::string& top_instance_name, const std::string& net_postfix, - const IoNameMap& io_name_map, const bool& explicit_port_mapping) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const ModuleId& core_module, + const std::string& top_instance_name, const std::string& net_postfix, + const IoNameMap& io_name_map, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); /* Include defined top-level module */ print_verilog_comment( - fp, std::string("----- FPGA top-level module to be capsulated -----")); + fp, std::string("----- FPGA top-level module to be capsulated -----")); /* Precheck on the top module and decide if we need to consider I/O naming * - If we do have a fpga_core module added, and dut is fpga_top, we need a @@ -68,7 +68,7 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); BasicPort net_port = module_port; net_port.set_name(module_port.get_name() + net_postfix); port2port_name_map[module_port.get_name()] = net_port; @@ -81,11 +81,11 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); /* Bypass dummy port: the port does not exist at core module */ if (io_name_map.fpga_top_port_is_dummy(module_port)) { - ModulePortId core_module_port = - module_manager.find_module_port(core_module, module_port.get_name()); + ModulePortId core_module_port = module_manager.find_module_port( + core_module, module_port.get_name()); if (!module_manager.valid_module_port_id(core_module, core_module_port)) { /* Print the wire for the dummy port */ @@ -128,16 +128,17 @@ std::string escapeNames(const std::string& original) { * Instanciate the input benchmark module *******************************************************************/ void print_verilog_testbench_benchmark_instance( - std::fstream& fp, const std::string& module_name, - const std::string& instance_name, - const std::string& module_input_port_postfix, - const std::string& module_output_port_postfix, - const std::string& input_port_postfix, const std::string& output_port_postfix, - const std::vector& clock_port_names, - const bool& include_clock_port_postfix, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const PinConstraints& pin_constraints, const BusGroup& bus_group, - const bool& use_explicit_port_map) { + std::fstream& fp, const std::string& module_name, + const std::string& instance_name, + const std::string& module_input_port_postfix, + const std::string& module_output_port_postfix, + const std::string& input_port_postfix, + const std::string& output_port_postfix, + const std::vector& clock_port_names, + const bool& include_clock_port_postfix, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const BusGroup& bus_group, + const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -267,7 +268,7 @@ void print_verilog_testbench_benchmark_instance( } else if (include_clock_port_postfix) { escapedName += input_port_postfix; } - escapedName = escapeNames(escapedName); + escapedName = escapeNames(escapedName); fp << escapedName; } @@ -296,8 +297,9 @@ void print_verilog_testbench_benchmark_instance( if (0 < pin_counter) { fp << ", "; } - std::string escapedName = bus_group.pin_name(pin) + output_port_postfix; - escapedName = escapeNames(escapedName); + std::string escapedName = + bus_group.pin_name(pin) + output_port_postfix; + escapedName = escapeNames(escapedName); fp << escapedName; pin_counter++; } @@ -326,15 +328,15 @@ void print_verilog_testbench_benchmark_instance( * by default *******************************************************************/ void print_verilog_testbench_connect_fpga_ios( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const AtomContext& atom_ctx, - const PlacementContext& place_ctx, const IoLocationMap& io_location_map, - const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, - const std::string& net_name_postfix, - const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix, - const std::vector& clock_port_names, - const size_t& unused_io_value) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const AtomContext& atom_ctx, + const PlacementContext& place_ctx, const IoLocationMap& io_location_map, + const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, + const std::string& net_name_postfix, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, + const std::vector& clock_port_names, + const size_t& unused_io_value) { /* Validate the file stream */ valid_file_stream(fp); @@ -358,25 +360,25 @@ void print_verilog_testbench_connect_fpga_ios( std::map> io_used; for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); io_used[module_io_port_id] = - std::vector(module_io_port.get_width(), false); + std::vector(module_io_port.get_width(), false); } /* Type mapping between VPR block and Module port */ std::map - atom_block_type_to_module_port_type; + atom_block_type_to_module_port_type; atom_block_type_to_module_port_type[AtomBlockType::INPAD] = - ModuleManager::MODULE_GPIN_PORT; + ModuleManager::MODULE_GPIN_PORT; atom_block_type_to_module_port_type[AtomBlockType::OUTPAD] = - ModuleManager::MODULE_GPOUT_PORT; + ModuleManager::MODULE_GPOUT_PORT; /* See if this I/O should be wired to a benchmark input/output */ /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs * This brings convenience to checking functionality */ print_verilog_comment( - fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); + fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* Bypass non-I/O atom blocks ! */ @@ -390,17 +392,17 @@ void print_verilog_testbench_connect_fpga_ios( * or should find a GPOUT for OUTPAD */ std::pair mapped_module_io_info = - std::make_pair(ModulePortId::INVALID(), -1); + std::make_pair(ModulePortId::INVALID(), -1); for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, - module_io_port.get_name()); + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ if (size_t(-1) == temp_io_index) { @@ -411,28 +413,28 @@ void print_verilog_testbench_connect_fpga_ios( if (ModuleManager::MODULE_GPIO_PORT == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } /* If this is an INPAD, we can use an GPIN port (if available) */ if (atom_block_type_to_module_port_type[atom_ctx.nlist.block_type( - atom_blk)] == + atom_blk)] == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } } /* We must find a valid one */ VTR_ASSERT(true == module_manager.valid_module_port_id( - top_module, mapped_module_io_info.first)); + top_module, mapped_module_io_info.first)); VTR_ASSERT(size_t(-1) != mapped_module_io_info.second); /* Ensure that IO index is in range */ BasicPort module_mapped_io_port = - module_manager.module_port(top_module, mapped_module_io_info.first); + module_manager.module_port(top_module, mapped_module_io_info.first); size_t io_index = mapped_module_io_info.second; /* Set the port pin index */ @@ -482,24 +484,24 @@ void print_verilog_testbench_connect_fpga_ios( benchmark_io_port.set_name(block_name); } else { benchmark_io_port.set_name( - std::string(block_name + io_input_port_name_postfix)); + std::string(block_name + io_input_port_name_postfix)); } print_verilog_comment( - fp, std::string("----- Blif Benchmark input " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark input " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); } else { VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)); benchmark_io_port.set_name( - std::string(block_name + io_output_port_name_postfix)); + std::string(block_name + io_output_port_name_postfix)); print_verilog_comment( - fp, std::string("----- Blif Benchmark output " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark output " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); } @@ -513,7 +515,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire the unused iopads to a constant */ print_verilog_comment( - fp, std::string("----- Wire unused FPGA I/Os to constants -----")); + fp, std::string("----- Wire unused FPGA I/Os to constants -----")); for (const ModulePortId& module_io_port_id : module_io_ports) { for (size_t io_index = 0; io_index < io_used[module_io_port_id].size(); ++io_index) { @@ -530,7 +532,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire to a contant */ BasicPort module_unused_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Set the port pin index */ module_unused_io_port.set_name(module_unused_io_port.get_name() + net_name_postfix); @@ -554,16 +556,16 @@ void print_verilog_testbench_connect_fpga_ios( * Note that: these codes are tuned for Icarus simulator!!! *******************************************************************/ void print_verilog_timeout_and_vcd( - std::fstream& fp, const std::string& module_name, - const std::string& vcd_fname, - const std::string& simulation_start_counter_name, - const std::string& error_counter_name, const float& simulation_time, - const bool& no_self_checking) { + std::fstream& fp, const std::string& module_name, + const std::string& vcd_fname, + const std::string& simulation_start_counter_name, + const std::string& error_counter_name, const float& simulation_time, + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_comment( - fp, std::string("----- Begin output waveform to VCD file-------")); + fp, std::string("----- Begin output waveform to VCD file-------")); fp << "\tinitial begin" << std::endl; fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl; @@ -571,7 +573,7 @@ void print_verilog_timeout_and_vcd( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("----- END output waveform to VCD file -------")); + fp, std::string("----- END output waveform to VCD file -------")); /* Add an empty line as splitter */ fp << std::endl; @@ -588,8 +590,8 @@ void print_verilog_timeout_and_vcd( fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; fp << "\t$display(\"Simulation start\");" << std::endl; print_verilog_comment( - fp, - std::string("----- Can be changed by the user for his/her need -------")); + fp, + std::string("----- Can be changed by the user for his/her need -------")); fp << "\t#" << std::setprecision(10) << simulation_time << std::endl; if (!no_self_checking) { @@ -618,8 +620,8 @@ void print_verilog_timeout_and_vcd( * Assume this is a single clock benchmark *******************************************************************/ std::vector generate_verilog_testbench_clock_port( - const std::vector& clock_port_names, - const std::string& default_clock_name) { + const std::vector& clock_port_names, + const std::string& default_clock_name) { std::vector clock_ports; if (0 == clock_port_names.size()) { clock_ports.push_back(BasicPort(default_clock_name, 1)); @@ -638,23 +640,23 @@ std::vector generate_verilog_testbench_clock_port( * Restriction: this function only supports single clock benchmarks! *******************************************************************/ void print_verilog_testbench_check( - std::fstream& fp, const std::string& simulation_start_counter_name, - const std::string& benchmark_port_postfix, - const std::string& fpga_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& config_done_name, const std::string& error_counter_name, - const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& default_clock_name) { + std::fstream& fp, const std::string& simulation_start_counter_name, + const std::string& benchmark_port_postfix, + const std::string& fpga_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& config_done_name, const std::string& error_counter_name, + const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& default_clock_name) { /* Validate the file stream */ valid_file_stream(fp); /* Add output autocheck */ print_verilog_comment( - fp, std::string("----- Begin checking output vectors -------")); + fp, std::string("----- Begin checking output vectors -------")); - std::vector clock_ports = - generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); + std::vector clock_ports = generate_verilog_testbench_clock_port( + clock_port_names, default_clock_name); print_verilog_comment(fp, std::string("----- Skip the first falling edge of " @@ -764,21 +766,21 @@ void print_verilog_testbench_check( * but be only used as a synchronizer in verification *******************************************************************/ void print_verilog_testbench_clock_stimuli( - std::fstream& fp, const PinConstraints& pin_constraints, - const SimulationSetting& simulation_parameters, - const std::vector& clock_ports) { + std::fstream& fp, const PinConstraints& pin_constraints, + const SimulationSetting& simulation_parameters, + const std::vector& clock_ports) { /* Validate the file stream */ valid_file_stream(fp); for (const BasicPort& clock_port : clock_ports) { print_verilog_comment(fp, std::string("----- Clock '") + - clock_port.get_name() + - std::string("' Initialization -------")); + clock_port.get_name() + + std::string("' Initialization -------")); /* Find the corresponding clock frequency from the simulation parameters */ float clk_freq_to_use = - (0.5 / simulation_parameters.default_operating_clock_frequency()) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.default_operating_clock_frequency()) / + VERILOG_SIM_TIMESCALE; /* Check pin constraints to see if this clock is constrained to a specific * pin If constrained, * - connect this clock to default values if it is set to be OPEN @@ -800,8 +802,8 @@ void print_verilog_testbench_clock_stimuli( if (pin_constraints.pin(pin_constraint) == simulation_parameters.clock_port(sim_clock_id)) { clk_freq_to_use = - (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / + VERILOG_SIM_TIMESCALE; } } } @@ -830,15 +832,15 @@ void print_verilog_testbench_clock_stimuli( * For clock signals, please use print_verilog_testbench_clock_stimuli *******************************************************************/ void print_verilog_testbench_random_stimuli( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, - const std::vector& clock_port_names, - const std::string& input_port_postfix, - const std::string& check_flag_port_postfix, - const std::vector& clock_ports, const bool& no_self_checking) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, + const std::vector& clock_port_names, + const std::string& input_port_postfix, + const std::string& check_flag_port_postfix, + const std::vector& clock_ports, const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -874,15 +876,15 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= 1'b0;" - << std::endl; + fp << "\t\t" << escapeNames(block_name + input_port_postfix) + << " <= 1'b0;" << std::endl; } } @@ -958,15 +960,15 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << escapeNames(block_name + input_port_postfix) << " <= $random;" - << std::endl; + fp << "\t\t" << escapeNames(block_name + input_port_postfix) + << " <= $random;" << std::endl; } } @@ -984,14 +986,14 @@ void print_verilog_testbench_random_stimuli( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_input_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const bool& include_clock_ports, const std::string& shared_input_port_postfix, - const bool& use_reg_port) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const bool& include_clock_ports, + const std::string& shared_input_port_postfix, const bool& use_reg_port) { /* Validate the file stream */ valid_file_stream(fp); @@ -1023,8 +1025,8 @@ void print_verilog_testbench_shared_input_ports( BasicPort input_port(block_name + shared_input_port_postfix, 1); /* For global ports, use wires; otherwise, use registers*/ if (false == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { if (use_reg_port) { fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; @@ -1048,9 +1050,9 @@ void print_verilog_testbench_shared_input_ports( * 2. the output ports (wires) for FPGA fabric *******************************************************************/ void print_verilog_testbench_shared_fpga_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& fpga_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& fpga_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1088,9 +1090,9 @@ void print_verilog_testbench_shared_fpga_output_ports( * 2. the output ports (wires) for benchmark instance *******************************************************************/ void print_verilog_testbench_shared_benchmark_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& benchmark_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& benchmark_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1112,7 +1114,7 @@ void print_verilog_testbench_shared_benchmark_output_ports( /* Each logical block assumes a single-width port */ BasicPort output_port( - std::string(block_name + benchmark_output_port_postfix), 1); + std::string(block_name + benchmark_output_port_postfix), 1); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; } @@ -1131,15 +1133,15 @@ void print_verilog_testbench_shared_benchmark_output_ports( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_check_flags( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& check_flag_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& check_flag_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); /* Instantiate register for output comparison */ print_verilog_comment( - fp, std::string("----- Output vectors checking flags -------")); + fp, std::string("----- Output vectors checking flags -------")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* We care only those logic blocks which are output I/Os */ if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { @@ -1174,30 +1176,30 @@ void print_verilog_testbench_shared_check_flags( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& shared_input_port_postfix, - const std::string& benchmark_output_port_postfix, - const std::string& fpga_output_port_postfix, - const std::string& check_flag_port_postfix, const bool& no_self_checking) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& shared_input_port_postfix, + const std::string& benchmark_output_port_postfix, + const std::string& fpga_output_port_postfix, + const std::string& check_flag_port_postfix, const bool& no_self_checking) { print_verilog_testbench_shared_input_ports( - fp, module_manager, module_name_map, global_ports, pin_constraints, - atom_ctx, netlist_annotation, clock_port_names, false, - shared_input_port_postfix, true); + fp, module_manager, module_name_map, global_ports, pin_constraints, + atom_ctx, netlist_annotation, clock_port_names, false, + shared_input_port_postfix, true); print_verilog_testbench_shared_fpga_output_ports( - fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); + fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); if (no_self_checking) { return; } print_verilog_testbench_shared_benchmark_output_ports( - fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); + fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); print_verilog_testbench_shared_check_flags(fp, atom_ctx, netlist_annotation, check_flag_port_postfix); @@ -1212,11 +1214,11 @@ void print_verilog_testbench_shared_ports( * in the graph of modules *******************************************************************/ static void rec_print_verilog_testbench_primitive_module_signal_initialization( - std::fstream& fp, const std::string& hie_path, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, - const std::vector& circuit_input_ports, - const ModuleManager& module_manager, const ModuleId& parent_module, - const ModuleId& primitive_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& hie_path, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const std::vector& circuit_input_ports, + const ModuleManager& module_manager, const ModuleId& parent_module, + const ModuleId& primitive_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1234,20 +1236,20 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) { std::string instance_name = module_manager.instance_name( - parent_module, child_module, child_instance); + parent_module, child_module, child_instance); /* Use default instanec name if not assigned */ if (true == instance_name.empty()) { instance_name = generate_instance_name( - module_manager.module_name(child_module), child_instance); + module_manager.module_name(child_module), child_instance); } std::string child_hie_path = hie_path + "." + instance_name; if (child_module != primitive_module) { rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, - module_manager, child_module, primitive_module, - deposit_random_values); + fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, + module_manager, child_module, primitive_module, + deposit_random_values); } else { /* If the child module is the primitive module, * we output the signal initialization codes for the input ports @@ -1255,7 +1257,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( VTR_ASSERT_SAFE(child_module == primitive_module); print_verilog_comment( - fp, std::string("------ BEGIN driver initialization -----")); + fp, std::string("------ BEGIN driver initialization -----")); fp << "\tinitial begin" << std::endl; for (const auto& input_port : circuit_input_ports) { @@ -1281,7 +1283,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("------ END driver initialization -----")); + fp, std::string("------ END driver initialization -----")); } } } @@ -1295,9 +1297,9 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( * - Logic gates (ONLY for MUX2) *******************************************************************/ void print_verilog_testbench_signal_initialization( - std::fstream& fp, const std::string& top_instance_name, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& top_instance_name, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, + const ModuleId& top_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1306,7 +1308,7 @@ void print_verilog_testbench_signal_initialization( /* Collect the input ports that require signal initialization */ std::map> - signal_init_circuit_ports; + signal_init_circuit_ports; for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_PASSGATE)) { @@ -1315,7 +1317,7 @@ void print_verilog_testbench_signal_initialization( * which is the first port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(0 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); } @@ -1328,7 +1330,7 @@ void print_verilog_testbench_signal_initialization( * which is the first two port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(1 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); signal_init_circuit_ports[model].push_back(input_ports[1]); @@ -1347,14 +1349,14 @@ void print_verilog_testbench_signal_initialization( /* Find the module id corresponding to the circuit model from module graph */ ModuleId primitive_module = module_manager.find_module( - circuit_lib.model_name(signal_init_circuit_model)); + circuit_lib.model_name(signal_init_circuit_model)); VTR_ASSERT(true == module_manager.valid_module_id(primitive_module)); /* Find all the instances created by the circuit model across the fabric*/ rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, top_instance_name, circuit_lib, signal_init_circuit_model, - signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, - top_module, primitive_module, deposit_random_values); + fp, top_instance_name, circuit_lib, signal_init_circuit_model, + signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, + top_module, primitive_module, deposit_random_values); } } From 70beaa63936aa03d144bdb912753d6be8ca4fb7f Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Tue, 5 Mar 2024 10:09:45 -0800 Subject: [PATCH 5/6] formatting --- .../fpga_verilog/verilog_testbench_utils.cpp | 321 +++++++++--------- 1 file changed, 160 insertions(+), 161 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 2e781afacc..72ce0dcaba 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -35,16 +35,16 @@ namespace openfpga { ); *******************************************************************/ void print_verilog_testbench_fpga_instance( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const ModuleId& core_module, - const std::string& top_instance_name, const std::string& net_postfix, - const IoNameMap& io_name_map, const bool& explicit_port_mapping) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const ModuleId& core_module, + const std::string& top_instance_name, const std::string& net_postfix, + const IoNameMap& io_name_map, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); /* Include defined top-level module */ print_verilog_comment( - fp, std::string("----- FPGA top-level module to be capsulated -----")); + fp, std::string("----- FPGA top-level module to be capsulated -----")); /* Precheck on the top module and decide if we need to consider I/O naming * - If we do have a fpga_core module added, and dut is fpga_top, we need a @@ -68,7 +68,7 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); BasicPort net_port = module_port; net_port.set_name(module_port.get_name() + net_postfix); port2port_name_map[module_port.get_name()] = net_port; @@ -81,11 +81,11 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); /* Bypass dummy port: the port does not exist at core module */ if (io_name_map.fpga_top_port_is_dummy(module_port)) { - ModulePortId core_module_port = module_manager.find_module_port( - core_module, module_port.get_name()); + ModulePortId core_module_port = + module_manager.find_module_port(core_module, module_port.get_name()); if (!module_manager.valid_module_port_id(core_module, core_module_port)) { /* Print the wire for the dummy port */ @@ -128,17 +128,16 @@ std::string escapeNames(const std::string& original) { * Instanciate the input benchmark module *******************************************************************/ void print_verilog_testbench_benchmark_instance( - std::fstream& fp, const std::string& module_name, - const std::string& instance_name, - const std::string& module_input_port_postfix, - const std::string& module_output_port_postfix, - const std::string& input_port_postfix, - const std::string& output_port_postfix, - const std::vector& clock_port_names, - const bool& include_clock_port_postfix, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const PinConstraints& pin_constraints, const BusGroup& bus_group, - const bool& use_explicit_port_map) { + std::fstream& fp, const std::string& module_name, + const std::string& instance_name, + const std::string& module_input_port_postfix, + const std::string& module_output_port_postfix, + const std::string& input_port_postfix, const std::string& output_port_postfix, + const std::vector& clock_port_names, + const bool& include_clock_port_postfix, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const BusGroup& bus_group, + const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -298,7 +297,7 @@ void print_verilog_testbench_benchmark_instance( fp << ", "; } std::string escapedName = - bus_group.pin_name(pin) + output_port_postfix; + bus_group.pin_name(pin) + output_port_postfix; escapedName = escapeNames(escapedName); fp << escapedName; pin_counter++; @@ -328,15 +327,15 @@ void print_verilog_testbench_benchmark_instance( * by default *******************************************************************/ void print_verilog_testbench_connect_fpga_ios( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const AtomContext& atom_ctx, - const PlacementContext& place_ctx, const IoLocationMap& io_location_map, - const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, - const std::string& net_name_postfix, - const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix, - const std::vector& clock_port_names, - const size_t& unused_io_value) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const AtomContext& atom_ctx, + const PlacementContext& place_ctx, const IoLocationMap& io_location_map, + const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, + const std::string& net_name_postfix, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, + const std::vector& clock_port_names, + const size_t& unused_io_value) { /* Validate the file stream */ valid_file_stream(fp); @@ -360,25 +359,25 @@ void print_verilog_testbench_connect_fpga_ios( std::map> io_used; for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); io_used[module_io_port_id] = - std::vector(module_io_port.get_width(), false); + std::vector(module_io_port.get_width(), false); } /* Type mapping between VPR block and Module port */ std::map - atom_block_type_to_module_port_type; + atom_block_type_to_module_port_type; atom_block_type_to_module_port_type[AtomBlockType::INPAD] = - ModuleManager::MODULE_GPIN_PORT; + ModuleManager::MODULE_GPIN_PORT; atom_block_type_to_module_port_type[AtomBlockType::OUTPAD] = - ModuleManager::MODULE_GPOUT_PORT; + ModuleManager::MODULE_GPOUT_PORT; /* See if this I/O should be wired to a benchmark input/output */ /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs * This brings convenience to checking functionality */ print_verilog_comment( - fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); + fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* Bypass non-I/O atom blocks ! */ @@ -392,17 +391,17 @@ void print_verilog_testbench_connect_fpga_ios( * or should find a GPOUT for OUTPAD */ std::pair mapped_module_io_info = - std::make_pair(ModulePortId::INVALID(), -1); + std::make_pair(ModulePortId::INVALID(), -1); for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, - module_io_port.get_name()); + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ if (size_t(-1) == temp_io_index) { @@ -413,28 +412,28 @@ void print_verilog_testbench_connect_fpga_ios( if (ModuleManager::MODULE_GPIO_PORT == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } /* If this is an INPAD, we can use an GPIN port (if available) */ if (atom_block_type_to_module_port_type[atom_ctx.nlist.block_type( - atom_blk)] == + atom_blk)] == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } } /* We must find a valid one */ VTR_ASSERT(true == module_manager.valid_module_port_id( - top_module, mapped_module_io_info.first)); + top_module, mapped_module_io_info.first)); VTR_ASSERT(size_t(-1) != mapped_module_io_info.second); /* Ensure that IO index is in range */ BasicPort module_mapped_io_port = - module_manager.module_port(top_module, mapped_module_io_info.first); + module_manager.module_port(top_module, mapped_module_io_info.first); size_t io_index = mapped_module_io_info.second; /* Set the port pin index */ @@ -484,24 +483,24 @@ void print_verilog_testbench_connect_fpga_ios( benchmark_io_port.set_name(block_name); } else { benchmark_io_port.set_name( - std::string(block_name + io_input_port_name_postfix)); + std::string(block_name + io_input_port_name_postfix)); } print_verilog_comment( - fp, std::string("----- Blif Benchmark input " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark input " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); } else { VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)); benchmark_io_port.set_name( - std::string(block_name + io_output_port_name_postfix)); + std::string(block_name + io_output_port_name_postfix)); print_verilog_comment( - fp, std::string("----- Blif Benchmark output " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark output " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); } @@ -515,7 +514,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire the unused iopads to a constant */ print_verilog_comment( - fp, std::string("----- Wire unused FPGA I/Os to constants -----")); + fp, std::string("----- Wire unused FPGA I/Os to constants -----")); for (const ModulePortId& module_io_port_id : module_io_ports) { for (size_t io_index = 0; io_index < io_used[module_io_port_id].size(); ++io_index) { @@ -532,7 +531,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire to a contant */ BasicPort module_unused_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Set the port pin index */ module_unused_io_port.set_name(module_unused_io_port.get_name() + net_name_postfix); @@ -556,16 +555,16 @@ void print_verilog_testbench_connect_fpga_ios( * Note that: these codes are tuned for Icarus simulator!!! *******************************************************************/ void print_verilog_timeout_and_vcd( - std::fstream& fp, const std::string& module_name, - const std::string& vcd_fname, - const std::string& simulation_start_counter_name, - const std::string& error_counter_name, const float& simulation_time, - const bool& no_self_checking) { + std::fstream& fp, const std::string& module_name, + const std::string& vcd_fname, + const std::string& simulation_start_counter_name, + const std::string& error_counter_name, const float& simulation_time, + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_comment( - fp, std::string("----- Begin output waveform to VCD file-------")); + fp, std::string("----- Begin output waveform to VCD file-------")); fp << "\tinitial begin" << std::endl; fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl; @@ -573,7 +572,7 @@ void print_verilog_timeout_and_vcd( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("----- END output waveform to VCD file -------")); + fp, std::string("----- END output waveform to VCD file -------")); /* Add an empty line as splitter */ fp << std::endl; @@ -590,8 +589,8 @@ void print_verilog_timeout_and_vcd( fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; fp << "\t$display(\"Simulation start\");" << std::endl; print_verilog_comment( - fp, - std::string("----- Can be changed by the user for his/her need -------")); + fp, + std::string("----- Can be changed by the user for his/her need -------")); fp << "\t#" << std::setprecision(10) << simulation_time << std::endl; if (!no_self_checking) { @@ -620,8 +619,8 @@ void print_verilog_timeout_and_vcd( * Assume this is a single clock benchmark *******************************************************************/ std::vector generate_verilog_testbench_clock_port( - const std::vector& clock_port_names, - const std::string& default_clock_name) { + const std::vector& clock_port_names, + const std::string& default_clock_name) { std::vector clock_ports; if (0 == clock_port_names.size()) { clock_ports.push_back(BasicPort(default_clock_name, 1)); @@ -640,23 +639,23 @@ std::vector generate_verilog_testbench_clock_port( * Restriction: this function only supports single clock benchmarks! *******************************************************************/ void print_verilog_testbench_check( - std::fstream& fp, const std::string& simulation_start_counter_name, - const std::string& benchmark_port_postfix, - const std::string& fpga_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& config_done_name, const std::string& error_counter_name, - const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& default_clock_name) { + std::fstream& fp, const std::string& simulation_start_counter_name, + const std::string& benchmark_port_postfix, + const std::string& fpga_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& config_done_name, const std::string& error_counter_name, + const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& default_clock_name) { /* Validate the file stream */ valid_file_stream(fp); /* Add output autocheck */ print_verilog_comment( - fp, std::string("----- Begin checking output vectors -------")); + fp, std::string("----- Begin checking output vectors -------")); - std::vector clock_ports = generate_verilog_testbench_clock_port( - clock_port_names, default_clock_name); + std::vector clock_ports = + generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); print_verilog_comment(fp, std::string("----- Skip the first falling edge of " @@ -766,21 +765,21 @@ void print_verilog_testbench_check( * but be only used as a synchronizer in verification *******************************************************************/ void print_verilog_testbench_clock_stimuli( - std::fstream& fp, const PinConstraints& pin_constraints, - const SimulationSetting& simulation_parameters, - const std::vector& clock_ports) { + std::fstream& fp, const PinConstraints& pin_constraints, + const SimulationSetting& simulation_parameters, + const std::vector& clock_ports) { /* Validate the file stream */ valid_file_stream(fp); for (const BasicPort& clock_port : clock_ports) { print_verilog_comment(fp, std::string("----- Clock '") + - clock_port.get_name() + - std::string("' Initialization -------")); + clock_port.get_name() + + std::string("' Initialization -------")); /* Find the corresponding clock frequency from the simulation parameters */ float clk_freq_to_use = - (0.5 / simulation_parameters.default_operating_clock_frequency()) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.default_operating_clock_frequency()) / + VERILOG_SIM_TIMESCALE; /* Check pin constraints to see if this clock is constrained to a specific * pin If constrained, * - connect this clock to default values if it is set to be OPEN @@ -802,8 +801,8 @@ void print_verilog_testbench_clock_stimuli( if (pin_constraints.pin(pin_constraint) == simulation_parameters.clock_port(sim_clock_id)) { clk_freq_to_use = - (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / + VERILOG_SIM_TIMESCALE; } } } @@ -832,15 +831,15 @@ void print_verilog_testbench_clock_stimuli( * For clock signals, please use print_verilog_testbench_clock_stimuli *******************************************************************/ void print_verilog_testbench_random_stimuli( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, - const std::vector& clock_port_names, - const std::string& input_port_postfix, - const std::string& check_flag_port_postfix, - const std::vector& clock_ports, const bool& no_self_checking) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, + const std::vector& clock_port_names, + const std::string& input_port_postfix, + const std::string& check_flag_port_postfix, + const std::vector& clock_ports, const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -876,8 +875,8 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } @@ -960,8 +959,8 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } @@ -986,14 +985,14 @@ void print_verilog_testbench_random_stimuli( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_input_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const bool& include_clock_ports, - const std::string& shared_input_port_postfix, const bool& use_reg_port) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const bool& include_clock_ports, const std::string& shared_input_port_postfix, + const bool& use_reg_port) { /* Validate the file stream */ valid_file_stream(fp); @@ -1025,8 +1024,8 @@ void print_verilog_testbench_shared_input_ports( BasicPort input_port(block_name + shared_input_port_postfix, 1); /* For global ports, use wires; otherwise, use registers*/ if (false == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { if (use_reg_port) { fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; @@ -1050,9 +1049,9 @@ void print_verilog_testbench_shared_input_ports( * 2. the output ports (wires) for FPGA fabric *******************************************************************/ void print_verilog_testbench_shared_fpga_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& fpga_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& fpga_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1090,9 +1089,9 @@ void print_verilog_testbench_shared_fpga_output_ports( * 2. the output ports (wires) for benchmark instance *******************************************************************/ void print_verilog_testbench_shared_benchmark_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& benchmark_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& benchmark_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1114,7 +1113,7 @@ void print_verilog_testbench_shared_benchmark_output_ports( /* Each logical block assumes a single-width port */ BasicPort output_port( - std::string(block_name + benchmark_output_port_postfix), 1); + std::string(block_name + benchmark_output_port_postfix), 1); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; } @@ -1133,15 +1132,15 @@ void print_verilog_testbench_shared_benchmark_output_ports( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_check_flags( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& check_flag_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& check_flag_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); /* Instantiate register for output comparison */ print_verilog_comment( - fp, std::string("----- Output vectors checking flags -------")); + fp, std::string("----- Output vectors checking flags -------")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* We care only those logic blocks which are output I/Os */ if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { @@ -1176,30 +1175,30 @@ void print_verilog_testbench_shared_check_flags( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& shared_input_port_postfix, - const std::string& benchmark_output_port_postfix, - const std::string& fpga_output_port_postfix, - const std::string& check_flag_port_postfix, const bool& no_self_checking) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& shared_input_port_postfix, + const std::string& benchmark_output_port_postfix, + const std::string& fpga_output_port_postfix, + const std::string& check_flag_port_postfix, const bool& no_self_checking) { print_verilog_testbench_shared_input_ports( - fp, module_manager, module_name_map, global_ports, pin_constraints, - atom_ctx, netlist_annotation, clock_port_names, false, - shared_input_port_postfix, true); + fp, module_manager, module_name_map, global_ports, pin_constraints, + atom_ctx, netlist_annotation, clock_port_names, false, + shared_input_port_postfix, true); print_verilog_testbench_shared_fpga_output_ports( - fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); + fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); if (no_self_checking) { return; } print_verilog_testbench_shared_benchmark_output_ports( - fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); + fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); print_verilog_testbench_shared_check_flags(fp, atom_ctx, netlist_annotation, check_flag_port_postfix); @@ -1214,11 +1213,11 @@ void print_verilog_testbench_shared_ports( * in the graph of modules *******************************************************************/ static void rec_print_verilog_testbench_primitive_module_signal_initialization( - std::fstream& fp, const std::string& hie_path, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, - const std::vector& circuit_input_ports, - const ModuleManager& module_manager, const ModuleId& parent_module, - const ModuleId& primitive_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& hie_path, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const std::vector& circuit_input_ports, + const ModuleManager& module_manager, const ModuleId& parent_module, + const ModuleId& primitive_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1236,20 +1235,20 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) { std::string instance_name = module_manager.instance_name( - parent_module, child_module, child_instance); + parent_module, child_module, child_instance); /* Use default instanec name if not assigned */ if (true == instance_name.empty()) { instance_name = generate_instance_name( - module_manager.module_name(child_module), child_instance); + module_manager.module_name(child_module), child_instance); } std::string child_hie_path = hie_path + "." + instance_name; if (child_module != primitive_module) { rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, - module_manager, child_module, primitive_module, - deposit_random_values); + fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, + module_manager, child_module, primitive_module, + deposit_random_values); } else { /* If the child module is the primitive module, * we output the signal initialization codes for the input ports @@ -1257,7 +1256,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( VTR_ASSERT_SAFE(child_module == primitive_module); print_verilog_comment( - fp, std::string("------ BEGIN driver initialization -----")); + fp, std::string("------ BEGIN driver initialization -----")); fp << "\tinitial begin" << std::endl; for (const auto& input_port : circuit_input_ports) { @@ -1283,7 +1282,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("------ END driver initialization -----")); + fp, std::string("------ END driver initialization -----")); } } } @@ -1297,9 +1296,9 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( * - Logic gates (ONLY for MUX2) *******************************************************************/ void print_verilog_testbench_signal_initialization( - std::fstream& fp, const std::string& top_instance_name, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& top_instance_name, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, + const ModuleId& top_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1308,7 +1307,7 @@ void print_verilog_testbench_signal_initialization( /* Collect the input ports that require signal initialization */ std::map> - signal_init_circuit_ports; + signal_init_circuit_ports; for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_PASSGATE)) { @@ -1317,7 +1316,7 @@ void print_verilog_testbench_signal_initialization( * which is the first port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(0 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); } @@ -1330,7 +1329,7 @@ void print_verilog_testbench_signal_initialization( * which is the first two port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(1 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); signal_init_circuit_ports[model].push_back(input_ports[1]); @@ -1349,14 +1348,14 @@ void print_verilog_testbench_signal_initialization( /* Find the module id corresponding to the circuit model from module graph */ ModuleId primitive_module = module_manager.find_module( - circuit_lib.model_name(signal_init_circuit_model)); + circuit_lib.model_name(signal_init_circuit_model)); VTR_ASSERT(true == module_manager.valid_module_id(primitive_module)); /* Find all the instances created by the circuit model across the fabric*/ rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, top_instance_name, circuit_lib, signal_init_circuit_model, - signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, - top_module, primitive_module, deposit_random_values); + fp, top_instance_name, circuit_lib, signal_init_circuit_model, + signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, + top_module, primitive_module, deposit_random_values); } } From a9f5545efda76095779da0e13e83da233848c5ea Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Tue, 5 Mar 2024 10:16:32 -0800 Subject: [PATCH 6/6] formatting --- .../fpga_verilog/verilog_testbench_utils.cpp | 319 +++++++++--------- 1 file changed, 159 insertions(+), 160 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 32075b4b1a..72ce0dcaba 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -35,16 +35,16 @@ namespace openfpga { ); *******************************************************************/ void print_verilog_testbench_fpga_instance( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const ModuleId& core_module, - const std::string& top_instance_name, const std::string& net_postfix, - const IoNameMap& io_name_map, const bool& explicit_port_mapping) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const ModuleId& core_module, + const std::string& top_instance_name, const std::string& net_postfix, + const IoNameMap& io_name_map, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); /* Include defined top-level module */ print_verilog_comment( - fp, std::string("----- FPGA top-level module to be capsulated -----")); + fp, std::string("----- FPGA top-level module to be capsulated -----")); /* Precheck on the top module and decide if we need to consider I/O naming * - If we do have a fpga_core module added, and dut is fpga_top, we need a @@ -68,7 +68,7 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); BasicPort net_port = module_port; net_port.set_name(module_port.get_name() + net_postfix); port2port_name_map[module_port.get_name()] = net_port; @@ -81,11 +81,11 @@ void print_verilog_testbench_fpga_instance( for (const ModulePortId& module_port_id : module_manager.module_ports(top_module)) { BasicPort module_port = - module_manager.module_port(top_module, module_port_id); + module_manager.module_port(top_module, module_port_id); /* Bypass dummy port: the port does not exist at core module */ if (io_name_map.fpga_top_port_is_dummy(module_port)) { - ModulePortId core_module_port = module_manager.find_module_port( - core_module, module_port.get_name()); + ModulePortId core_module_port = + module_manager.find_module_port(core_module, module_port.get_name()); if (!module_manager.valid_module_port_id(core_module, core_module_port)) { /* Print the wire for the dummy port */ @@ -128,17 +128,16 @@ std::string escapeNames(const std::string& original) { * Instanciate the input benchmark module *******************************************************************/ void print_verilog_testbench_benchmark_instance( - std::fstream& fp, const std::string& module_name, - const std::string& instance_name, - const std::string& module_input_port_postfix, - const std::string& module_output_port_postfix, - const std::string& input_port_postfix, - const std::string& output_port_postfix, - const std::vector& clock_port_names, - const bool& include_clock_port_postfix, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const PinConstraints& pin_constraints, const BusGroup& bus_group, - const bool& use_explicit_port_map) { + std::fstream& fp, const std::string& module_name, + const std::string& instance_name, + const std::string& module_input_port_postfix, + const std::string& module_output_port_postfix, + const std::string& input_port_postfix, const std::string& output_port_postfix, + const std::vector& clock_port_names, + const bool& include_clock_port_postfix, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const BusGroup& bus_group, + const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -328,15 +327,15 @@ void print_verilog_testbench_benchmark_instance( * by default *******************************************************************/ void print_verilog_testbench_connect_fpga_ios( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleId& top_module, const AtomContext& atom_ctx, - const PlacementContext& place_ctx, const IoLocationMap& io_location_map, - const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, - const std::string& net_name_postfix, - const std::string& io_input_port_name_postfix, - const std::string& io_output_port_name_postfix, - const std::vector& clock_port_names, - const size_t& unused_io_value) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleId& top_module, const AtomContext& atom_ctx, + const PlacementContext& place_ctx, const IoLocationMap& io_location_map, + const VprNetlistAnnotation& netlist_annotation, const BusGroup& bus_group, + const std::string& net_name_postfix, + const std::string& io_input_port_name_postfix, + const std::string& io_output_port_name_postfix, + const std::vector& clock_port_names, + const size_t& unused_io_value) { /* Validate the file stream */ valid_file_stream(fp); @@ -360,25 +359,25 @@ void print_verilog_testbench_connect_fpga_ios( std::map> io_used; for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); io_used[module_io_port_id] = - std::vector(module_io_port.get_width(), false); + std::vector(module_io_port.get_width(), false); } /* Type mapping between VPR block and Module port */ std::map - atom_block_type_to_module_port_type; + atom_block_type_to_module_port_type; atom_block_type_to_module_port_type[AtomBlockType::INPAD] = - ModuleManager::MODULE_GPIN_PORT; + ModuleManager::MODULE_GPIN_PORT; atom_block_type_to_module_port_type[AtomBlockType::OUTPAD] = - ModuleManager::MODULE_GPOUT_PORT; + ModuleManager::MODULE_GPOUT_PORT; /* See if this I/O should be wired to a benchmark input/output */ /* Add signals from blif benchmark and short-wire them to FPGA I/O PADs * This brings convenience to checking functionality */ print_verilog_comment( - fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); + fp, std::string("----- Link BLIF Benchmark I/Os to FPGA I/Os -----")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* Bypass non-I/O atom blocks ! */ @@ -392,17 +391,17 @@ void print_verilog_testbench_connect_fpga_ios( * or should find a GPOUT for OUTPAD */ std::pair mapped_module_io_info = - std::make_pair(ModulePortId::INVALID(), -1); + std::make_pair(ModulePortId::INVALID(), -1); for (const ModulePortId& module_io_port_id : module_io_ports) { const BasicPort& module_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Find the index of the mapped GPIO in top-level FPGA fabric */ size_t temp_io_index = io_location_map.io_index( - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, - place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, - module_io_port.get_name()); + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y, + place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile, + module_io_port.get_name()); /* Bypass invalid index (not mapped to this GPIO port) */ if (size_t(-1) == temp_io_index) { @@ -413,28 +412,28 @@ void print_verilog_testbench_connect_fpga_ios( if (ModuleManager::MODULE_GPIO_PORT == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } /* If this is an INPAD, we can use an GPIN port (if available) */ if (atom_block_type_to_module_port_type[atom_ctx.nlist.block_type( - atom_blk)] == + atom_blk)] == module_manager.port_type(top_module, module_io_port_id)) { mapped_module_io_info = - std::make_pair(module_io_port_id, temp_io_index); + std::make_pair(module_io_port_id, temp_io_index); break; } } /* We must find a valid one */ VTR_ASSERT(true == module_manager.valid_module_port_id( - top_module, mapped_module_io_info.first)); + top_module, mapped_module_io_info.first)); VTR_ASSERT(size_t(-1) != mapped_module_io_info.second); /* Ensure that IO index is in range */ BasicPort module_mapped_io_port = - module_manager.module_port(top_module, mapped_module_io_info.first); + module_manager.module_port(top_module, mapped_module_io_info.first); size_t io_index = mapped_module_io_info.second; /* Set the port pin index */ @@ -484,24 +483,24 @@ void print_verilog_testbench_connect_fpga_ios( benchmark_io_port.set_name(block_name); } else { benchmark_io_port.set_name( - std::string(block_name + io_input_port_name_postfix)); + std::string(block_name + io_input_port_name_postfix)); } print_verilog_comment( - fp, std::string("----- Blif Benchmark input " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark input " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, module_mapped_io_port, benchmark_io_port, false); } else { VTR_ASSERT(AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)); benchmark_io_port.set_name( - std::string(block_name + io_output_port_name_postfix)); + std::string(block_name + io_output_port_name_postfix)); print_verilog_comment( - fp, std::string("----- Blif Benchmark output " + block_name + - " is mapped to FPGA IOPAD " + - module_mapped_io_port.get_name() + "[" + - std::to_string(io_index) + "] -----")); + fp, std::string("----- Blif Benchmark output " + block_name + + " is mapped to FPGA IOPAD " + + module_mapped_io_port.get_name() + "[" + + std::to_string(io_index) + "] -----")); print_verilog_wire_connection(fp, benchmark_io_port, module_mapped_io_port, false); } @@ -515,7 +514,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire the unused iopads to a constant */ print_verilog_comment( - fp, std::string("----- Wire unused FPGA I/Os to constants -----")); + fp, std::string("----- Wire unused FPGA I/Os to constants -----")); for (const ModulePortId& module_io_port_id : module_io_ports) { for (size_t io_index = 0; io_index < io_used[module_io_port_id].size(); ++io_index) { @@ -532,7 +531,7 @@ void print_verilog_testbench_connect_fpga_ios( /* Wire to a contant */ BasicPort module_unused_io_port = - module_manager.module_port(top_module, module_io_port_id); + module_manager.module_port(top_module, module_io_port_id); /* Set the port pin index */ module_unused_io_port.set_name(module_unused_io_port.get_name() + net_name_postfix); @@ -556,16 +555,16 @@ void print_verilog_testbench_connect_fpga_ios( * Note that: these codes are tuned for Icarus simulator!!! *******************************************************************/ void print_verilog_timeout_and_vcd( - std::fstream& fp, const std::string& module_name, - const std::string& vcd_fname, - const std::string& simulation_start_counter_name, - const std::string& error_counter_name, const float& simulation_time, - const bool& no_self_checking) { + std::fstream& fp, const std::string& module_name, + const std::string& vcd_fname, + const std::string& simulation_start_counter_name, + const std::string& error_counter_name, const float& simulation_time, + const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); print_verilog_comment( - fp, std::string("----- Begin output waveform to VCD file-------")); + fp, std::string("----- Begin output waveform to VCD file-------")); fp << "\tinitial begin" << std::endl; fp << "\t\t$dumpfile(\"" << vcd_fname << "\");" << std::endl; @@ -573,7 +572,7 @@ void print_verilog_timeout_and_vcd( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("----- END output waveform to VCD file -------")); + fp, std::string("----- END output waveform to VCD file -------")); /* Add an empty line as splitter */ fp << std::endl; @@ -590,8 +589,8 @@ void print_verilog_timeout_and_vcd( fp << "\t$timeformat(-9, 2, \"ns\", 20);" << std::endl; fp << "\t$display(\"Simulation start\");" << std::endl; print_verilog_comment( - fp, - std::string("----- Can be changed by the user for his/her need -------")); + fp, + std::string("----- Can be changed by the user for his/her need -------")); fp << "\t#" << std::setprecision(10) << simulation_time << std::endl; if (!no_self_checking) { @@ -620,8 +619,8 @@ void print_verilog_timeout_and_vcd( * Assume this is a single clock benchmark *******************************************************************/ std::vector generate_verilog_testbench_clock_port( - const std::vector& clock_port_names, - const std::string& default_clock_name) { + const std::vector& clock_port_names, + const std::string& default_clock_name) { std::vector clock_ports; if (0 == clock_port_names.size()) { clock_ports.push_back(BasicPort(default_clock_name, 1)); @@ -640,23 +639,23 @@ std::vector generate_verilog_testbench_clock_port( * Restriction: this function only supports single clock benchmarks! *******************************************************************/ void print_verilog_testbench_check( - std::fstream& fp, const std::string& simulation_start_counter_name, - const std::string& benchmark_port_postfix, - const std::string& fpga_port_postfix, - const std::string& check_flag_port_postfix, - const std::string& config_done_name, const std::string& error_counter_name, - const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& default_clock_name) { + std::fstream& fp, const std::string& simulation_start_counter_name, + const std::string& benchmark_port_postfix, + const std::string& fpga_port_postfix, + const std::string& check_flag_port_postfix, + const std::string& config_done_name, const std::string& error_counter_name, + const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& default_clock_name) { /* Validate the file stream */ valid_file_stream(fp); /* Add output autocheck */ print_verilog_comment( - fp, std::string("----- Begin checking output vectors -------")); + fp, std::string("----- Begin checking output vectors -------")); - std::vector clock_ports = generate_verilog_testbench_clock_port( - clock_port_names, default_clock_name); + std::vector clock_ports = + generate_verilog_testbench_clock_port(clock_port_names, default_clock_name); print_verilog_comment(fp, std::string("----- Skip the first falling edge of " @@ -766,21 +765,21 @@ void print_verilog_testbench_check( * but be only used as a synchronizer in verification *******************************************************************/ void print_verilog_testbench_clock_stimuli( - std::fstream& fp, const PinConstraints& pin_constraints, - const SimulationSetting& simulation_parameters, - const std::vector& clock_ports) { + std::fstream& fp, const PinConstraints& pin_constraints, + const SimulationSetting& simulation_parameters, + const std::vector& clock_ports) { /* Validate the file stream */ valid_file_stream(fp); for (const BasicPort& clock_port : clock_ports) { print_verilog_comment(fp, std::string("----- Clock '") + - clock_port.get_name() + - std::string("' Initialization -------")); + clock_port.get_name() + + std::string("' Initialization -------")); /* Find the corresponding clock frequency from the simulation parameters */ float clk_freq_to_use = - (0.5 / simulation_parameters.default_operating_clock_frequency()) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.default_operating_clock_frequency()) / + VERILOG_SIM_TIMESCALE; /* Check pin constraints to see if this clock is constrained to a specific * pin If constrained, * - connect this clock to default values if it is set to be OPEN @@ -802,8 +801,8 @@ void print_verilog_testbench_clock_stimuli( if (pin_constraints.pin(pin_constraint) == simulation_parameters.clock_port(sim_clock_id)) { clk_freq_to_use = - (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / - VERILOG_SIM_TIMESCALE; + (0.5 / simulation_parameters.clock_frequency(sim_clock_id)) / + VERILOG_SIM_TIMESCALE; } } } @@ -832,15 +831,15 @@ void print_verilog_testbench_clock_stimuli( * For clock signals, please use print_verilog_testbench_clock_stimuli *******************************************************************/ void print_verilog_testbench_random_stimuli( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const ModuleManager& module_manager, const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, - const std::vector& clock_port_names, - const std::string& input_port_postfix, - const std::string& check_flag_port_postfix, - const std::vector& clock_ports, const bool& no_self_checking) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, + const std::vector& clock_port_names, + const std::string& input_port_postfix, + const std::string& check_flag_port_postfix, + const std::vector& clock_ports, const bool& no_self_checking) { /* Validate the file stream */ valid_file_stream(fp); @@ -876,8 +875,8 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } @@ -960,8 +959,8 @@ void print_verilog_testbench_random_stimuli( * fabric because their stimulus cannot be random */ if (true == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { continue; } @@ -986,14 +985,14 @@ void print_verilog_testbench_random_stimuli( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_input_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const bool& include_clock_ports, - const std::string& shared_input_port_postfix, const bool& use_reg_port) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const bool& include_clock_ports, const std::string& shared_input_port_postfix, + const bool& use_reg_port) { /* Validate the file stream */ valid_file_stream(fp); @@ -1025,8 +1024,8 @@ void print_verilog_testbench_shared_input_ports( BasicPort input_port(block_name + shared_input_port_postfix, 1); /* For global ports, use wires; otherwise, use registers*/ if (false == port_is_fabric_global_reset_port( - global_ports, module_manager, module_name_map, - pin_constraints.net_pin(block_name))) { + global_ports, module_manager, module_name_map, + pin_constraints.net_pin(block_name))) { if (use_reg_port) { fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; @@ -1050,9 +1049,9 @@ void print_verilog_testbench_shared_input_ports( * 2. the output ports (wires) for FPGA fabric *******************************************************************/ void print_verilog_testbench_shared_fpga_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& fpga_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& fpga_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1090,9 +1089,9 @@ void print_verilog_testbench_shared_fpga_output_ports( * 2. the output ports (wires) for benchmark instance *******************************************************************/ void print_verilog_testbench_shared_benchmark_output_ports( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& benchmark_output_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& benchmark_output_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); @@ -1114,7 +1113,7 @@ void print_verilog_testbench_shared_benchmark_output_ports( /* Each logical block assumes a single-width port */ BasicPort output_port( - std::string(block_name + benchmark_output_port_postfix), 1); + std::string(block_name + benchmark_output_port_postfix), 1); fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, output_port) << ";" << std::endl; } @@ -1133,15 +1132,15 @@ void print_verilog_testbench_shared_benchmark_output_ports( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_check_flags( - std::fstream& fp, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::string& check_flag_port_postfix) { + std::fstream& fp, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::string& check_flag_port_postfix) { /* Validate the file stream */ valid_file_stream(fp); /* Instantiate register for output comparison */ print_verilog_comment( - fp, std::string("----- Output vectors checking flags -------")); + fp, std::string("----- Output vectors checking flags -------")); for (const AtomBlockId& atom_blk : atom_ctx.nlist.blocks()) { /* We care only those logic blocks which are output I/Os */ if (AtomBlockType::OUTPAD != atom_ctx.nlist.block_type(atom_blk)) { @@ -1176,30 +1175,30 @@ void print_verilog_testbench_shared_check_flags( * same input vectors *******************************************************************/ void print_verilog_testbench_shared_ports( - std::fstream& fp, const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricGlobalPortInfo& global_ports, - const PinConstraints& pin_constraints, const AtomContext& atom_ctx, - const VprNetlistAnnotation& netlist_annotation, - const std::vector& clock_port_names, - const std::string& shared_input_port_postfix, - const std::string& benchmark_output_port_postfix, - const std::string& fpga_output_port_postfix, - const std::string& check_flag_port_postfix, const bool& no_self_checking) { + std::fstream& fp, const ModuleManager& module_manager, + const ModuleNameMap& module_name_map, + const FabricGlobalPortInfo& global_ports, + const PinConstraints& pin_constraints, const AtomContext& atom_ctx, + const VprNetlistAnnotation& netlist_annotation, + const std::vector& clock_port_names, + const std::string& shared_input_port_postfix, + const std::string& benchmark_output_port_postfix, + const std::string& fpga_output_port_postfix, + const std::string& check_flag_port_postfix, const bool& no_self_checking) { print_verilog_testbench_shared_input_ports( - fp, module_manager, module_name_map, global_ports, pin_constraints, - atom_ctx, netlist_annotation, clock_port_names, false, - shared_input_port_postfix, true); + fp, module_manager, module_name_map, global_ports, pin_constraints, + atom_ctx, netlist_annotation, clock_port_names, false, + shared_input_port_postfix, true); print_verilog_testbench_shared_fpga_output_ports( - fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); + fp, atom_ctx, netlist_annotation, fpga_output_port_postfix); if (no_self_checking) { return; } print_verilog_testbench_shared_benchmark_output_ports( - fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); + fp, atom_ctx, netlist_annotation, benchmark_output_port_postfix); print_verilog_testbench_shared_check_flags(fp, atom_ctx, netlist_annotation, check_flag_port_postfix); @@ -1214,11 +1213,11 @@ void print_verilog_testbench_shared_ports( * in the graph of modules *******************************************************************/ static void rec_print_verilog_testbench_primitive_module_signal_initialization( - std::fstream& fp, const std::string& hie_path, - const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, - const std::vector& circuit_input_ports, - const ModuleManager& module_manager, const ModuleId& parent_module, - const ModuleId& primitive_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& hie_path, + const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, + const std::vector& circuit_input_ports, + const ModuleManager& module_manager, const ModuleId& parent_module, + const ModuleId& primitive_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1236,20 +1235,20 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( for (const size_t& child_instance : module_manager.child_module_instances(parent_module, child_module)) { std::string instance_name = module_manager.instance_name( - parent_module, child_module, child_instance); + parent_module, child_module, child_instance); /* Use default instanec name if not assigned */ if (true == instance_name.empty()) { instance_name = generate_instance_name( - module_manager.module_name(child_module), child_instance); + module_manager.module_name(child_module), child_instance); } std::string child_hie_path = hie_path + "." + instance_name; if (child_module != primitive_module) { rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, - module_manager, child_module, primitive_module, - deposit_random_values); + fp, child_hie_path, circuit_lib, circuit_model, circuit_input_ports, + module_manager, child_module, primitive_module, + deposit_random_values); } else { /* If the child module is the primitive module, * we output the signal initialization codes for the input ports @@ -1257,7 +1256,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( VTR_ASSERT_SAFE(child_module == primitive_module); print_verilog_comment( - fp, std::string("------ BEGIN driver initialization -----")); + fp, std::string("------ BEGIN driver initialization -----")); fp << "\tinitial begin" << std::endl; for (const auto& input_port : circuit_input_ports) { @@ -1283,7 +1282,7 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( fp << "\tend" << std::endl; print_verilog_comment( - fp, std::string("------ END driver initialization -----")); + fp, std::string("------ END driver initialization -----")); } } } @@ -1297,9 +1296,9 @@ static void rec_print_verilog_testbench_primitive_module_signal_initialization( * - Logic gates (ONLY for MUX2) *******************************************************************/ void print_verilog_testbench_signal_initialization( - std::fstream& fp, const std::string& top_instance_name, - const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, - const ModuleId& top_module, const bool& deposit_random_values) { + std::fstream& fp, const std::string& top_instance_name, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, + const ModuleId& top_module, const bool& deposit_random_values) { /* Validate the file stream */ valid_file_stream(fp); @@ -1308,7 +1307,7 @@ void print_verilog_testbench_signal_initialization( /* Collect the input ports that require signal initialization */ std::map> - signal_init_circuit_ports; + signal_init_circuit_ports; for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_PASSGATE)) { @@ -1317,7 +1316,7 @@ void print_verilog_testbench_signal_initialization( * which is the first port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(0 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); } @@ -1330,7 +1329,7 @@ void print_verilog_testbench_signal_initialization( * which is the first two port, i.e., the datapath inputs */ std::vector input_ports = - circuit_lib.model_input_ports(model); + circuit_lib.model_input_ports(model); VTR_ASSERT(1 < input_ports.size()); signal_init_circuit_ports[model].push_back(input_ports[0]); signal_init_circuit_ports[model].push_back(input_ports[1]); @@ -1349,14 +1348,14 @@ void print_verilog_testbench_signal_initialization( /* Find the module id corresponding to the circuit model from module graph */ ModuleId primitive_module = module_manager.find_module( - circuit_lib.model_name(signal_init_circuit_model)); + circuit_lib.model_name(signal_init_circuit_model)); VTR_ASSERT(true == module_manager.valid_module_id(primitive_module)); /* Find all the instances created by the circuit model across the fabric*/ rec_print_verilog_testbench_primitive_module_signal_initialization( - fp, top_instance_name, circuit_lib, signal_init_circuit_model, - signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, - top_module, primitive_module, deposit_random_values); + fp, top_instance_name, circuit_lib, signal_init_circuit_model, + signal_init_circuit_ports.at(signal_init_circuit_model), module_manager, + top_module, primitive_module, deposit_random_values); } }