From 250aafe02d2ebc06f2b593af5065d60de2b3bbf0 Mon Sep 17 00:00:00 2001 From: romangauchi Date: Sun, 30 Jan 2022 22:29:32 -0700 Subject: [PATCH 1/3] [SOFA_PLUS] fix the default OpenFPGA task testbench/simulation --- .../config/task.conf | 37 +++++++++++++++++++ .../generate_testbench.openfpga | 2 +- 2 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf diff --git a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf new file mode 100644 index 0000000..4b7fb78 --- /dev/null +++ b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=yosys_vpr +arch_variable_file=${PATH:TASK_DIR}/design_variables.yml + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml +openfpga_vpr_device_layout=12x12 +openfpga_vpr_route_chan_width=60 + +[ARCHITECTURES] +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml + +[BENCHMARKS] +bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v + +[SYNTHESIS_PARAM] +bench0_top = counter + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= diff --git a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga index 8ac671b..b51d0fb 100644 --- a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/generate_testbench.openfpga @@ -45,7 +45,7 @@ write_fabric_bitstream --format plain_text --file fabric_bitstream.bit write_fabric_bitstream --format xml --file fabric_bitstream.xml write_full_testbench --file ./SRC \ - --bitstream fabric_bitstream.bit + --bitstream fabric_bitstream.bit \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --explicit_port_mapping From 568de2497bd0b971042685ff4c40b9d086275dbd Mon Sep 17 00:00:00 2001 From: romangauchi Date: Mon, 31 Jan 2022 11:34:26 -0700 Subject: [PATCH 2/3] [SOFA] fix typos in the 'generate_testbench.openfpga' script causing the unknown 'write_verilog_testbench' command error' --- .../FPGA1212_SOFA_CHD_task/generate_testbench.openfpga | 2 +- .../FPGA1212_SOFA_HD_task/generate_testbench.openfpga | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga index 59b4638..83a16c1 100644 --- a/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/generate_testbench.openfpga @@ -54,7 +54,7 @@ write_fabric_bitstream --file fabric_bitstream.xml --format xml # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC \ - --bitstream fabric_bitstream.bit + --bitstream fabric_bitstream.bit \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge diff --git a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga index 49a224f..64d6fcc 100644 --- a/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga +++ b/FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/generate_testbench.openfpga @@ -55,7 +55,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts write_full_testbench --file ./SRC \ - --bitstream fabric_bitstream.bit + --bitstream fabric_bitstream.bit \ --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ --explicit_port_mapping # Exclude signal initialization since it does not help simulator converge From bc43b6b9b30e8fc1fc8647c13261f8402bc9de8b Mon Sep 17 00:00:00 2001 From: romangauchi Date: Fri, 4 Feb 2022 13:27:45 -0700 Subject: [PATCH 3/3] [SOFA_PLUS] remove 'the task.conf', which must be generated with the 'make runOpenFPGA' command --- .../config/task.conf | 37 ------------------- 1 file changed, 37 deletions(-) delete mode 100644 FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf diff --git a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf b/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf deleted file mode 100644 index 4b7fb78..0000000 --- a/FPGA1212_SOFA_PLUS_HD_PNR/FPGA1212_SOFA_PLUS_HD_task/config/task.conf +++ /dev/null @@ -1,37 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 1*60 -fpga_flow=yosys_vpr -arch_variable_file=${PATH:TASK_DIR}/design_variables.yml - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:TASK_DIR}/generate_testbench.openfpga -openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -external_fabric_key_file=${PATH:TASK_DIR}/arch/fabric_key.xml -openfpga_vpr_device_layout=12x12 -openfpga_vpr_route_chan_width=60 - -[ARCHITECTURES] -arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml - -[BENCHMARKS] -bench0=${PATH:TASK_DIR}/BENCHMARK/counter/counter.v - -[SYNTHESIS_PARAM] -bench0_top = counter - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -#end_flow_with_test=