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As Vivado's version changes, the version Modelsim has compiled may differ from the version generated, creating conflicts that do not have any meaning on RTL simulations.
Xilinx's blk_mem_gen ip core, as used in this project, is a very simple core to simulate on a RTL level - it is only a look-up table. A solution may be to generate a modelsim-friendly version for each machine_pkg that is selected by hdlmake while generating a simulation Makefile.
The text was updated successfully, but these errors were encountered:
As Vivado's version changes, the version Modelsim has compiled may differ from the version generated, creating conflicts that do not have any meaning on RTL simulations.
Xilinx's blk_mem_gen ip core, as used in this project, is a very simple core to simulate on a RTL level - it is only a look-up table. A solution may be to generate a modelsim-friendly version for each machine_pkg that is selected by hdlmake while generating a simulation Makefile.
The text was updated successfully, but these errors were encountered: