From d5a78a26d05eb7ecfcae201a4e11911ca2ed074d Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 14 Aug 2023 16:57:07 -0300 Subject: [PATCH 01/26] afc_ref_fofb_ctrl_gen.vhd: acquire RTM-LAMP setpoints We only have room for the first 8 channels, which is fine since channels 9-11 aren't being used. --- hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 7f79090d..4f784d40 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -2246,12 +2246,15 @@ begin end generate; end generate; + -- PI setpoint for the first 8 channels, which are the ones being used atm. gen_rtm_ac_num_cores : for i in 0 to c_ACQ_NUM_CORES-1 generate - acq_rtmlamp_data(i)( - (c_RTMLAMP_CHANNELS+c_RTMLAMP_CHANNELS+1)*to_integer(c_FACQ_CHANNELS(c_ACQ_RTM_LAMP_ID).atom_width)-1 + gen_rtmlamp_dbg_pi_ctrl_sp : for j in 2*c_RTMLAMP_CHANNELS to 2*c_RTMLAMP_CHANNELS+7 generate + acq_rtmlamp_data(i)( + (j+1)*to_integer(c_FACQ_CHANNELS(c_ACQ_RTM_LAMP_ID).atom_width)-1 downto - (c_RTMLAMP_CHANNELS+c_RTMLAMP_CHANNELS)*to_integer(c_FACQ_CHANNELS(c_ACQ_RTM_LAMP_ID).atom_width)) - <= rtmlamp_dbg_pi_ctrl_sp(0); + j*to_integer(c_FACQ_CHANNELS(c_ACQ_RTM_LAMP_ID).atom_width)) + <= rtmlamp_dbg_pi_ctrl_sp(j-2*c_RTMLAMP_CHANNELS); + end generate; end generate; -------------------- From 5e0fab74e90d927985cfdc2388c9dfb3e81e8023 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Fri, 29 Sep 2023 12:33:12 -0300 Subject: [PATCH 02/26] Increase FOFB Gain fractional width This gain is always < 1 and > -1,so we can increase the fractional part and reduce the integer part to increase its precision. The gain width is kept the same. --- hdl/modules/fofb_processing/dot_prod_pkg.vhd | 4 ++-- hdl/testbench/xwb_fofb_processing/fofb_gains.dat | 16 ++++++++-------- .../xwb_fofb_processing_tb.vhd | 8 +++++--- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/hdl/modules/fofb_processing/dot_prod_pkg.vhd b/hdl/modules/fofb_processing/dot_prod_pkg.vhd index 7bdd7f7f..6d30a1ec 100644 --- a/hdl/modules/fofb_processing/dot_prod_pkg.vhd +++ b/hdl/modules/fofb_processing/dot_prod_pkg.vhd @@ -35,8 +35,8 @@ package dot_prod_pkg is type t_fofb_processing_sp_decim_arr is array (natural range <>) of signed(31 downto 0); type t_fofb_processing_sp_decim_ratio_arr is array (natural range <>) of integer range 0 to c_FOFB_SP_DECIM_MAX_RATIO; - constant c_FOFB_GAIN_INT_WIDTH : natural := 3; - constant c_FOFB_GAIN_FRAC_WIDTH : natural := 12; + constant c_FOFB_GAIN_INT_WIDTH : natural := 0; + constant c_FOFB_GAIN_FRAC_WIDTH : natural := 15; constant c_FOFB_GAIN_WIDTH : natural := c_FOFB_GAIN_INT_WIDTH + c_FOFB_GAIN_FRAC_WIDTH + 1; constant c_FOFB_WB_GAIN_WIDTH : natural := 32; type t_fofb_processing_gain_arr is array (natural range <>) of signed(c_FOFB_GAIN_WIDTH-1 downto 0); diff --git a/hdl/testbench/xwb_fofb_processing/fofb_gains.dat b/hdl/testbench/xwb_fofb_processing/fofb_gains.dat index b83cecba..8d302cdc 100644 --- a/hdl/testbench/xwb_fofb_processing/fofb_gains.dat +++ b/hdl/testbench/xwb_fofb_processing/fofb_gains.dat @@ -2,11 +2,11 @@ 0.25 -0.5 0.5 --1.0 -1.0 --1.5 -1.5 --2.0 -2.0 --2.5 -2.5 +-0.1 +0.1 +-0.08 +0.08 +-0.15 +0.15 +-0.99 +0.99 diff --git a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd index 19ea9d66..0632cac1 100644 --- a/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd +++ b/hdl/testbench/xwb_fofb_processing/xwb_fofb_processing_tb.vhd @@ -205,6 +205,7 @@ begin variable expec_fofb_proc_sp_arr : real_vector(g_CHANNELS-1 downto 0) := (others => 0.0); variable sp_err : real := 0.0; + variable sp_diff : real := 0.0; variable expec_fofb_proc_sp_decim_arr : real_vector(g_CHANNELS-1 downto 0) := (others => 0.0); @@ -513,16 +514,17 @@ begin for i in 0 to g_CHANNELS-1 loop - -- TODO: this may be problematic for smaller setpoint values sp_err := abs((real(to_integer(sp_arr(i))) / floor(expec_fofb_proc_sp_arr(i))) - 1.0); + sp_diff := abs(real(to_integer(sp_arr(i))) - expec_fofb_proc_sp_arr(i)); report "channel " & to_string(i) & ": " & "setpoint: " & to_string(to_integer(sp_arr(i))) & " (expected: " & - to_string(integer(floor(expec_fofb_proc_sp_arr(i)))) & ")" + to_string(integer(floor(expec_fofb_proc_sp_arr(i)))) & ")" & " difference: " & + to_string(sp_diff) severity note; - if sp_err > 0.01 then + if sp_err > 0.01 and sp_diff > 2.0 then report "error: " & to_string(sp_err) & " is too large (> 1%)!" severity error; else From 72f58305c4d288a4810f229193ae5460d0d766a6 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Wed, 20 Sep 2023 17:29:44 -0300 Subject: [PATCH 03/26] fofb_shaper_filt: add module Shaper filters intended to equalize the open-loop response among all controllers. --- hdl/ip_cores/infra-cores | 2 +- hdl/modules/Manifest.py | 3 +- hdl/modules/fofb_ctrl_pkg.vhd | 38 + hdl/modules/fofb_shaper_filt/Manifest.py | 5 + .../fofb_shaper_filt/cheby/build_cheby.sh | 4 + .../cheby/doc/wb_fofb_shaper_filt_regs.html | 1472 +++++++++++++++++ .../cheby/wb_fofb_shaper_filt_regs.cheby | 87 + .../cheby/wb_fofb_shaper_filt_regs.h | 114 ++ .../cheby/wb_fofb_shaper_filt_regs.vhd | 1009 +++++++++++ .../fofb_shaper_filt/fofb_shaper_filt_pkg.vhd | 35 + .../fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 397 +++++ .../wb_fofb_shaper_filt_regs_consts_pkg.vhd | 75 + .../xwb_fofb_shaper_filt/Manifest.py | 15 + .../fofb_shaper_filt_coeffs.dat | 12 + .../fofb_shaper_filt_x_y.dat | 200 +++ .../xwb_fofb_shaper_filt/ghdl/.gitignore | 4 + .../xwb_fofb_shaper_filt/ghdl/Manifest.py | 11 + .../xwb_fofb_shaper_filt_tb.vhd | 225 +++ 18 files changed, 3706 insertions(+), 2 deletions(-) create mode 100644 hdl/modules/fofb_shaper_filt/Manifest.py create mode 100755 hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh create mode 100644 hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html create mode 100644 hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby create mode 100644 hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h create mode 100644 hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd create mode 100644 hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd create mode 100644 hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd create mode 100644 hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/Manifest.py create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_x_y.dat create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/ghdl/.gitignore create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index a1034c04..29c38f10 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit a1034c04875eb49ac2ab82f4d37a07c72892bcd9 +Subproject commit 29c38f10c5faba590e5bbb5f2529daa79f063466 diff --git a/hdl/modules/Manifest.py b/hdl/modules/Manifest.py index 5201fcd9..a500f7ad 100644 --- a/hdl/modules/Manifest.py +++ b/hdl/modules/Manifest.py @@ -3,6 +3,7 @@ modules = { "local": [ "fofb_ctrl_wrapper", "fofb_processing", - "fofb_sys_id" + "fofb_sys_id", + "fofb_shaper_filt" ] } diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index 6059c1b3..88382e33 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -640,6 +640,27 @@ package fofb_ctrl_pkg is ); end component; + component xwb_fofb_shaper_filt is + generic ( + g_CHANNELS : natural; + g_ARITH_EXTRA_BITS : natural; + g_IFCS_EXTRA_BITS : natural; + g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; + g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; + g_WITH_EXTRA_WB_REG : boolean := false + ); + port ( + clk_i : in std_logic; + rst_n_i : in std_logic; + sp_arr_i : in t_sp_arr(g_CHANNELS-1 DOWNTO 0); + sp_valid_arr_i : in std_logic_vector(g_CHANNELS-1 DOWNTO 0); + filt_sp_arr_o : out t_sp_arr(g_CHANNELS-1 DOWNTO 0); + filt_sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 DOWNTO 0); + wb_slv_i : in t_wishbone_slave_in; + wb_slv_o : out t_wishbone_slave_out + ); + end component xwb_fofb_shaper_filt; + component fofb_processing_dcc_adapter is generic ( -- DCC packet FIFO depth @@ -748,6 +769,23 @@ package fofb_ctrl_pkg is date => x"20230504", name => "FOFB_SYS_ID_REGS "))); + -- FOFB shaper filters + constant c_xwb_fofb_shaper_filter_regs_sdb : t_sdb_device := ( + abi_class => x"0000", -- undocumented device + abi_ver_major => x"00", + abi_ver_minor => x"01", + wbd_endian => c_sdb_endian_big, + wbd_width => x"4", -- 32-bit port granularity (0100) + sdb_component => ( + addr_first => x"0000000000000000", + addr_last => x"000000000000FFFF", + product => ( + vendor_id => x"1000000000001215", -- LNLS + device_id => x"f65559b2", -- Last 8 chars of "FOFB_SHAPER_REGS" md5sum + version => x"00000001", + date => x"20230922", + name => "FOFB_SHAPER_REGS "))); + end fofb_ctrl_pkg; package body fofb_ctrl_pkg is diff --git a/hdl/modules/fofb_shaper_filt/Manifest.py b/hdl/modules/fofb_shaper_filt/Manifest.py new file mode 100644 index 00000000..f7b436ce --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/Manifest.py @@ -0,0 +1,5 @@ +files = [ + "cheby/wb_fofb_shaper_filt_regs.vhd", + "xwb_fofb_shaper_filt.vhd", + "fofb_shaper_filt_pkg.vhd" +] diff --git a/hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh b/hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh new file mode 100755 index 00000000..4121ce35 --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/build_cheby.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +mkdir -p doc +cheby -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd diff --git a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html new file mode 100644 index 00000000..850fb4d2 --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html @@ -0,0 +1,1472 @@ + + +wb_fofb_shaper_filt_regs + + + +

wb_fofb_shaper_filt_regs

+

Interface to FOFB IIR shaper filters regs

+

1. Memory map summary

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HW addressTypeNameHDL prefixC prefix
0x0000-0x0fffBLOCKchchch
0x0000-0x00ffBLOCKch.0ch_0ch.0
0x0000-0x00ffMEMORYch.0.coeffsch_0_coeffsch.0.coeffs
+0x0000REGch.0.coeffs.valch_0_coeffs_valch.0.coeffs.val
0x0100-0x01ffBLOCKch.1ch_1ch.1
0x0100-0x01ffMEMORYch.1.coeffsch_1_coeffsch.1.coeffs
+0x0100REGch.1.coeffs.valch_1_coeffs_valch.1.coeffs.val
0x0200-0x02ffBLOCKch.2ch_2ch.2
0x0200-0x02ffMEMORYch.2.coeffsch_2_coeffsch.2.coeffs
+0x0200REGch.2.coeffs.valch_2_coeffs_valch.2.coeffs.val
0x0300-0x03ffBLOCKch.3ch_3ch.3
0x0300-0x03ffMEMORYch.3.coeffsch_3_coeffsch.3.coeffs
+0x0300REGch.3.coeffs.valch_3_coeffs_valch.3.coeffs.val
0x0400-0x04ffBLOCKch.4ch_4ch.4
0x0400-0x04ffMEMORYch.4.coeffsch_4_coeffsch.4.coeffs
+0x0400REGch.4.coeffs.valch_4_coeffs_valch.4.coeffs.val
0x0500-0x05ffBLOCKch.5ch_5ch.5
0x0500-0x05ffMEMORYch.5.coeffsch_5_coeffsch.5.coeffs
+0x0500REGch.5.coeffs.valch_5_coeffs_valch.5.coeffs.val
0x0600-0x06ffBLOCKch.6ch_6ch.6
0x0600-0x06ffMEMORYch.6.coeffsch_6_coeffsch.6.coeffs
+0x0600REGch.6.coeffs.valch_6_coeffs_valch.6.coeffs.val
0x0700-0x07ffBLOCKch.7ch_7ch.7
0x0700-0x07ffMEMORYch.7.coeffsch_7_coeffsch.7.coeffs
+0x0700REGch.7.coeffs.valch_7_coeffs_valch.7.coeffs.val
0x0800-0x08ffBLOCKch.8ch_8ch.8
0x0800-0x08ffMEMORYch.8.coeffsch_8_coeffsch.8.coeffs
+0x0800REGch.8.coeffs.valch_8_coeffs_valch.8.coeffs.val
0x0900-0x09ffBLOCKch.9ch_9ch.9
0x0900-0x09ffMEMORYch.9.coeffsch_9_coeffsch.9.coeffs
+0x0900REGch.9.coeffs.valch_9_coeffs_valch.9.coeffs.val
0x0a00-0x0affBLOCKch.10ch_10ch.10
0x0a00-0x0affMEMORYch.10.coeffsch_10_coeffsch.10.coeffs
+0x0a00REGch.10.coeffs.valch_10_coeffs_valch.10.coeffs.val
0x0b00-0x0bffBLOCKch.11ch_11ch.11
0x0b00-0x0bffMEMORYch.11.coeffsch_11_coeffsch.11.coeffs
+0x0b00REGch.11.coeffs.valch_11_coeffs_valch.11.coeffs.val
0x1000REGmax_filt_ordermax_filt_ordermax_filt_order
0x1004REGcoeffs_fp_reprcoeffs_fp_reprcoeffs_fp_repr
0x1008REGctlctlctl
+ +

2. Register description

+ +

2.1. ch.0.coeffs.val

+ + + + + +
HW prefix:ch_0_coeffs_val
HW address:0x0
C prefix:ch.0.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.2. ch.1.coeffs.val

+ + + + + +
HW prefix:ch_1_coeffs_val
HW address:0x100
C prefix:ch.1.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.3. ch.2.coeffs.val

+ + + + + +
HW prefix:ch_2_coeffs_val
HW address:0x200
C prefix:ch.2.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.4. ch.3.coeffs.val

+ + + + + +
HW prefix:ch_3_coeffs_val
HW address:0x300
C prefix:ch.3.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.5. ch.4.coeffs.val

+ + + + + +
HW prefix:ch_4_coeffs_val
HW address:0x400
C prefix:ch.4.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.6. ch.5.coeffs.val

+ + + + + +
HW prefix:ch_5_coeffs_val
HW address:0x500
C prefix:ch.5.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.7. ch.6.coeffs.val

+ + + + + +
HW prefix:ch_6_coeffs_val
HW address:0x600
C prefix:ch.6.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.8. ch.7.coeffs.val

+ + + + + +
HW prefix:ch_7_coeffs_val
HW address:0x700
C prefix:ch.7.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.9. ch.8.coeffs.val

+ + + + + +
HW prefix:ch_8_coeffs_val
HW address:0x800
C prefix:ch.8.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.10. ch.9.coeffs.val

+ + + + + +
HW prefix:ch_9_coeffs_val
HW address:0x900
C prefix:ch.9.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.11. ch.10.coeffs.val

+ + + + + +
HW prefix:ch_10_coeffs_val
HW address:0xa00
C prefix:ch.10.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.12. ch.11.coeffs.val

+ + + + + +
HW prefix:ch_11_coeffs_val
HW address:0xb00
C prefix:ch.11.coeffs.val
C block offset:0x0
+

+Coefficient value using 'coeffs_fp_repr' fixed-point
representation. It should be aligned to the left.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
val[31:24]
2322212019181716
val[23:16]
15141312111098
val[15:8]
76543210
val[7:0]
+
    +
  • +val +[rw]: Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + +
+ +

2.13. max_filt_order

+ + + + + +
HW prefix:max_filt_order
HW address:0x1000
C prefix:max_filt_order
C block offset:0x1000
+

+Maximum filter order supported by the gateware.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
max_filt_order[31:24]
2322212019181716
max_filt_order[23:16]
15141312111098
max_filt_order[15:8]
76543210
max_filt_order[7:0]
+
    +
  • +max_filt_order +[ro]: Maximum filter order supported by the gateware. + +
+ +

2.14. coeffs_fp_repr

+ + + + + +
HW prefix:coeffs_fp_repr
HW address:0x1004
C prefix:coeffs_fp_repr
C block offset:0x1004
+

+Fixed-point signed representation of coefficients.
The coefficients should be aligned to the left. The fixed-point
position is then given by 32 - 'int_width' (i.e. one should divide
this register's content by 2**{32 - 'int_width'} to get the
represented decimal number.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
------frac_width[4:3]
76543210
frac_width[2:0]int_width[4:0]
+
    +
  • +int_width +[ro]: Integer width (accounting for the signal bit). + +
  • +frac_width +[ro]: Fractionary width. + +
+ +

2.15. ctl

+ + + + + +
HW prefix:ctl
HW address:0x1008
C prefix:ctl
C block offset:0x1008
+

+Control register.
+

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3130292827262524
--------
2322212019181716
--------
15141312111098
--------
76543210
-------eff_coeffs
+
    +
  • +eff_coeffs +[rw]: Strobe for effectivating (i.e. updating) coefficients. + +
    write 0: no effect
    write 1: effectivates coefficients (this bit autoclears) +
+ + + + diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby new file mode 100644 index 00000000..440ad34b --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby @@ -0,0 +1,87 @@ +memory-map: + bus: wb-32-be + name: wb_fofb_shaper_filt_regs + description: Interface to FOFB IIR shaper filters regs + x-hdl: + busgroup: True + iogroup: wb_fofb_shaper_filt_regs_ifc + children: + - repeat: + name: ch + count: 12 + children: + - memory: + name: coeffs + memsize: 200 + description: | + Coefficients for the ceil('max_filt_order'/2) IIR internal + biquads. + + Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). + The 'coeffs' array should be populated in the following manner: + + coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + + This array acts like a 'shadow' for the real coefficients and is + only effectivated when '1' is written to 'eff_coeffs' bit of + 'ctl' register. + + NOTE: This ABI supports up to 20th order filters, but only the + coefficients corresponding to the first 'max_filt_order' filters + are meaningful for the gateware. + children: + - reg: + name: val + width: 32 + access: rw + description: | + Coefficient value using 'coeffs_fp_repr' fixed-point + representation. It should be aligned to the left. + - reg: + name: max_filt_order + width: 32 + access: ro + description: | + Maximum filter order supported by the gateware. + - reg: + name: coeffs_fp_repr + width: 32 + access: ro + description: | + Fixed-point signed representation of coefficients. + The coefficients should be aligned to the left. The fixed-point + position is then given by 32 - 'int_width' (i.e. one should divide + this register's content by 2**{32 - 'int_width'} to get the + represented decimal number. + children: + - field: + name: int_width + range: 4-0 + description: | + Integer width (accounting for the signal bit). + - field: + name: frac_width + range: 9-5 + description: | + Fractionary width. + - reg: + name: ctl + width: 32 + access: rw + description: | + Control register. + children: + - field: + name: eff_coeffs + x-hdl: + type: autoclear + range: 0 + description: | + Strobe for effectivating (i.e. updating) coefficients. + comment: | + write 0: no effect + write 1: effectivates coefficients (this bit autoclears) diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h new file mode 100644 index 00000000..a9c0e267 --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h @@ -0,0 +1,114 @@ +#ifndef __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__ +#define __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__ +#define WB_FOFB_SHAPER_FILT_REGS_SIZE 4108 /* 0x100c */ + +/* None */ +#define WB_FOFB_SHAPER_FILT_REGS_CH 0x0UL +#define WB_FOFB_SHAPER_FILT_REGS_CH_SIZE 256 /* 0x100 */ + +/* Coefficients for the ceil('max_filt_order'/2) IIR internal +biquads. + +Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). +The 'coeffs' array should be populated in the following manner: + + coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + +This array acts like a 'shadow' for the real coefficients and is +only effectivated when '1' is written to 'eff_coeffs' bit of +'ctl' register. + +NOTE: This ABI supports up to 20th order filters, but only the +coefficients corresponding to the first 'max_filt_order' filters +are meaningful for the gateware. + */ +#define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS 0x0UL +#define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS_SIZE 4 /* 0x4 */ + +/* Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + */ +#define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS_VAL 0x0UL + +/* Maximum filter order supported by the gateware. + */ +#define WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER 0x1000UL + +/* Fixed-point signed representation of coefficients. +The coefficients should be aligned to the left. The fixed-point +position is then given by 32 - 'int_width' (i.e. one should divide +this register's content by 2**{32 - 'int_width'} to get the +represented decimal number. + */ +#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR 0x1004UL +#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_MASK 0x1fUL +#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_SHIFT 0 +#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_MASK 0x3e0UL +#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_SHIFT 5 + +/* Control register. + */ +#define WB_FOFB_SHAPER_FILT_REGS_CTL 0x1008UL +#define WB_FOFB_SHAPER_FILT_REGS_CTL_EFF_COEFFS 0x1UL + +#ifndef __ASSEMBLER__ +struct wb_fofb_shaper_filt_regs { + /* [0x0]: REPEAT (no description) */ + struct ch { + /* [0x0]: MEMORY Coefficients for the ceil('max_filt_order'/2) IIR internal +biquads. + +Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). +The 'coeffs' array should be populated in the following manner: + + coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + +This array acts like a 'shadow' for the real coefficients and is +only effectivated when '1' is written to 'eff_coeffs' bit of +'ctl' register. + +NOTE: This ABI supports up to 20th order filters, but only the +coefficients corresponding to the first 'max_filt_order' filters +are meaningful for the gateware. + */ + struct coeffs { + /* [0x0]: REG (rw) Coefficient value using 'coeffs_fp_repr' fixed-point +representation. It should be aligned to the left. + */ + uint32_t val; + } coeffs[50]; + + /* padding to: 0 words */ + uint32_t __padding_0[14]; + } ch[12]; + + /* padding to: 0 words */ + uint32_t __padding_0[256]; + + /* [0x1000]: REG (ro) Maximum filter order supported by the gateware. + */ + uint32_t max_filt_order; + + /* [0x1004]: REG (ro) Fixed-point signed representation of coefficients. +The coefficients should be aligned to the left. The fixed-point +position is then given by 32 - 'int_width' (i.e. one should divide +this register's content by 2**{32 - 'int_width'} to get the +represented decimal number. + */ + uint32_t coeffs_fp_repr; + + /* [0x1008]: REG (rw) Control register. + */ + uint32_t ctl; +}; +#endif /* !__ASSEMBLER__*/ + +#endif /* __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__ */ diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd new file mode 100644 index 00000000..8aff157e --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd @@ -0,0 +1,1009 @@ +-- Do not edit. Generated by cheby 1.6.dev0 using these options: +-- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd +-- Generated on Fri Sep 22 15:10:27 2023 by guilherme.ricioli + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_pkg.all; +use work.cheby_pkg.all; + +package wb_fofb_shaper_filt_regs_pkg is + type t_wb_fofb_shaper_filt_regs_ifc_master_out is record + ch_0_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_1_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_2_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_3_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_4_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_5_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_6_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_7_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_8_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_9_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_10_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ch_11_coeffs_val_dat_o : std_logic_vector(31 downto 0); + ctl_eff_coeffs : std_logic; + end record t_wb_fofb_shaper_filt_regs_ifc_master_out; + subtype t_wb_fofb_shaper_filt_regs_ifc_slave_in is t_wb_fofb_shaper_filt_regs_ifc_master_out; + + type t_wb_fofb_shaper_filt_regs_ifc_slave_out is record + ch_0_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_0_coeffs_val_rd_i : std_logic; + ch_1_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_1_coeffs_val_rd_i : std_logic; + ch_2_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_2_coeffs_val_rd_i : std_logic; + ch_3_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_3_coeffs_val_rd_i : std_logic; + ch_4_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_4_coeffs_val_rd_i : std_logic; + ch_5_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_5_coeffs_val_rd_i : std_logic; + ch_6_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_6_coeffs_val_rd_i : std_logic; + ch_7_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_7_coeffs_val_rd_i : std_logic; + ch_8_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_8_coeffs_val_rd_i : std_logic; + ch_9_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_9_coeffs_val_rd_i : std_logic; + ch_10_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_10_coeffs_val_rd_i : std_logic; + ch_11_coeffs_adr_i : std_logic_vector(5 downto 0); + ch_11_coeffs_val_rd_i : std_logic; + max_filt_order : std_logic_vector(31 downto 0); + coeffs_fp_repr_int_width : std_logic_vector(4 downto 0); + coeffs_fp_repr_frac_width : std_logic_vector(4 downto 0); + end record t_wb_fofb_shaper_filt_regs_ifc_slave_out; + subtype t_wb_fofb_shaper_filt_regs_ifc_master_in is t_wb_fofb_shaper_filt_regs_ifc_slave_out; + +end wb_fofb_shaper_filt_regs_pkg; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.wishbone_pkg.all; +use work.cheby_pkg.all; +use work.wb_fofb_shaper_filt_regs_pkg.all; + +entity wb_fofb_shaper_filt_regs is + port ( + rst_n_i : in std_logic; + clk_i : in std_logic; + wb_i : in t_wishbone_slave_in; + wb_o : out t_wishbone_slave_out; + -- Wires and registers + wb_fofb_shaper_filt_regs_ifc_i : in t_wb_fofb_shaper_filt_regs_ifc_master_in; + wb_fofb_shaper_filt_regs_ifc_o : out t_wb_fofb_shaper_filt_regs_ifc_master_out + ); +end wb_fofb_shaper_filt_regs; + +architecture syn of wb_fofb_shaper_filt_regs is + signal adr_int : std_logic_vector(12 downto 2); + signal rd_req_int : std_logic; + signal wr_req_int : std_logic; + signal rd_ack_int : std_logic; + signal wr_ack_int : std_logic; + signal wb_en : std_logic; + signal ack_int : std_logic; + signal wb_rip : std_logic; + signal wb_wip : std_logic; + signal ch_0_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_0_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_0_coeffs_val_rreq : std_logic; + signal ch_0_coeffs_val_rack : std_logic; + signal ch_0_coeffs_val_int_wr : std_logic; + signal ch_1_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_1_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_1_coeffs_val_rreq : std_logic; + signal ch_1_coeffs_val_rack : std_logic; + signal ch_1_coeffs_val_int_wr : std_logic; + signal ch_2_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_2_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_2_coeffs_val_rreq : std_logic; + signal ch_2_coeffs_val_rack : std_logic; + signal ch_2_coeffs_val_int_wr : std_logic; + signal ch_3_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_3_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_3_coeffs_val_rreq : std_logic; + signal ch_3_coeffs_val_rack : std_logic; + signal ch_3_coeffs_val_int_wr : std_logic; + signal ch_4_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_4_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_4_coeffs_val_rreq : std_logic; + signal ch_4_coeffs_val_rack : std_logic; + signal ch_4_coeffs_val_int_wr : std_logic; + signal ch_5_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_5_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_5_coeffs_val_rreq : std_logic; + signal ch_5_coeffs_val_rack : std_logic; + signal ch_5_coeffs_val_int_wr : std_logic; + signal ch_6_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_6_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_6_coeffs_val_rreq : std_logic; + signal ch_6_coeffs_val_rack : std_logic; + signal ch_6_coeffs_val_int_wr : std_logic; + signal ch_7_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_7_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_7_coeffs_val_rreq : std_logic; + signal ch_7_coeffs_val_rack : std_logic; + signal ch_7_coeffs_val_int_wr : std_logic; + signal ch_8_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_8_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_8_coeffs_val_rreq : std_logic; + signal ch_8_coeffs_val_rack : std_logic; + signal ch_8_coeffs_val_int_wr : std_logic; + signal ch_9_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_9_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_9_coeffs_val_rreq : std_logic; + signal ch_9_coeffs_val_rack : std_logic; + signal ch_9_coeffs_val_int_wr : std_logic; + signal ch_10_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_10_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_10_coeffs_val_rreq : std_logic; + signal ch_10_coeffs_val_rack : std_logic; + signal ch_10_coeffs_val_int_wr : std_logic; + signal ch_11_coeffs_val_int_dato : std_logic_vector(31 downto 0); + signal ch_11_coeffs_val_ext_dat : std_logic_vector(31 downto 0); + signal ch_11_coeffs_val_rreq : std_logic; + signal ch_11_coeffs_val_rack : std_logic; + signal ch_11_coeffs_val_int_wr : std_logic; + signal ctl_eff_coeffs_reg : std_logic; + signal ctl_wreq : std_logic; + signal ctl_wack : std_logic; + signal rd_ack_d0 : std_logic; + signal rd_dat_d0 : std_logic_vector(31 downto 0); + signal wr_req_d0 : std_logic; + signal wr_adr_d0 : std_logic_vector(12 downto 2); + signal wr_dat_d0 : std_logic_vector(31 downto 0); + signal wr_sel_d0 : std_logic_vector(3 downto 0); + signal ch_0_coeffs_wr : std_logic; + signal ch_0_coeffs_wreq : std_logic; + signal ch_0_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_1_coeffs_wr : std_logic; + signal ch_1_coeffs_wreq : std_logic; + signal ch_1_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_2_coeffs_wr : std_logic; + signal ch_2_coeffs_wreq : std_logic; + signal ch_2_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_3_coeffs_wr : std_logic; + signal ch_3_coeffs_wreq : std_logic; + signal ch_3_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_4_coeffs_wr : std_logic; + signal ch_4_coeffs_wreq : std_logic; + signal ch_4_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_5_coeffs_wr : std_logic; + signal ch_5_coeffs_wreq : std_logic; + signal ch_5_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_6_coeffs_wr : std_logic; + signal ch_6_coeffs_wreq : std_logic; + signal ch_6_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_7_coeffs_wr : std_logic; + signal ch_7_coeffs_wreq : std_logic; + signal ch_7_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_8_coeffs_wr : std_logic; + signal ch_8_coeffs_wreq : std_logic; + signal ch_8_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_9_coeffs_wr : std_logic; + signal ch_9_coeffs_wreq : std_logic; + signal ch_9_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_10_coeffs_wr : std_logic; + signal ch_10_coeffs_wreq : std_logic; + signal ch_10_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_11_coeffs_wr : std_logic; + signal ch_11_coeffs_wreq : std_logic; + signal ch_11_coeffs_adr_int : std_logic_vector(5 downto 0); +begin + + -- WB decode signals + adr_int <= wb_i.adr(12 downto 2); + wb_en <= wb_i.cyc and wb_i.stb; + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_rip <= '0'; + else + wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int; + end if; + end if; + end process; + rd_req_int <= (wb_en and not wb_i.we) and not wb_rip; + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + wb_wip <= '0'; + else + wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int; + end if; + end if; + end process; + wr_req_int <= (wb_en and wb_i.we) and not wb_wip; + + ack_int <= rd_ack_int or wr_ack_int; + wb_o.ack <= ack_int; + wb_o.stall <= not ack_int and wb_en; + wb_o.rty <= '0'; + wb_o.err <= '0'; + + -- pipelining for wr-in+rd-out + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + rd_ack_int <= '0'; + wr_req_d0 <= '0'; + else + rd_ack_int <= rd_ack_d0; + wb_o.dat <= rd_dat_d0; + wr_req_d0 <= wr_req_int; + wr_adr_d0 <= adr_int; + wr_dat_d0 <= wb_i.dat; + wr_sel_d0 <= wb_i.sel; + end if; + end if; + end process; + + -- Memory ch_0_coeffs + process (adr_int, wr_adr_d0, ch_0_coeffs_wr) begin + if ch_0_coeffs_wr = '1' then + ch_0_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_0_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_0_coeffs_wreq <= ch_0_coeffs_val_int_wr; + ch_0_coeffs_wr <= ch_0_coeffs_wreq; + ch_0_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_0_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_0_coeffs_val_int_dato, + rd_a_i => ch_0_coeffs_val_rreq, + wr_a_i => ch_0_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_0_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_0_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_0_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_0_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_0_coeffs_val_rack <= '0'; + else + ch_0_coeffs_val_rack <= ch_0_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_1_coeffs + process (adr_int, wr_adr_d0, ch_1_coeffs_wr) begin + if ch_1_coeffs_wr = '1' then + ch_1_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_1_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_1_coeffs_wreq <= ch_1_coeffs_val_int_wr; + ch_1_coeffs_wr <= ch_1_coeffs_wreq; + ch_1_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_1_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_1_coeffs_val_int_dato, + rd_a_i => ch_1_coeffs_val_rreq, + wr_a_i => ch_1_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_1_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_1_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_1_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_1_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_1_coeffs_val_rack <= '0'; + else + ch_1_coeffs_val_rack <= ch_1_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_2_coeffs + process (adr_int, wr_adr_d0, ch_2_coeffs_wr) begin + if ch_2_coeffs_wr = '1' then + ch_2_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_2_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_2_coeffs_wreq <= ch_2_coeffs_val_int_wr; + ch_2_coeffs_wr <= ch_2_coeffs_wreq; + ch_2_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_2_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_2_coeffs_val_int_dato, + rd_a_i => ch_2_coeffs_val_rreq, + wr_a_i => ch_2_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_2_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_2_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_2_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_2_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_2_coeffs_val_rack <= '0'; + else + ch_2_coeffs_val_rack <= ch_2_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_3_coeffs + process (adr_int, wr_adr_d0, ch_3_coeffs_wr) begin + if ch_3_coeffs_wr = '1' then + ch_3_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_3_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_3_coeffs_wreq <= ch_3_coeffs_val_int_wr; + ch_3_coeffs_wr <= ch_3_coeffs_wreq; + ch_3_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_3_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_3_coeffs_val_int_dato, + rd_a_i => ch_3_coeffs_val_rreq, + wr_a_i => ch_3_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_3_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_3_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_3_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_3_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_3_coeffs_val_rack <= '0'; + else + ch_3_coeffs_val_rack <= ch_3_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_4_coeffs + process (adr_int, wr_adr_d0, ch_4_coeffs_wr) begin + if ch_4_coeffs_wr = '1' then + ch_4_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_4_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_4_coeffs_wreq <= ch_4_coeffs_val_int_wr; + ch_4_coeffs_wr <= ch_4_coeffs_wreq; + ch_4_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_4_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_4_coeffs_val_int_dato, + rd_a_i => ch_4_coeffs_val_rreq, + wr_a_i => ch_4_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_4_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_4_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_4_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_4_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_4_coeffs_val_rack <= '0'; + else + ch_4_coeffs_val_rack <= ch_4_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_5_coeffs + process (adr_int, wr_adr_d0, ch_5_coeffs_wr) begin + if ch_5_coeffs_wr = '1' then + ch_5_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_5_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_5_coeffs_wreq <= ch_5_coeffs_val_int_wr; + ch_5_coeffs_wr <= ch_5_coeffs_wreq; + ch_5_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_5_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_5_coeffs_val_int_dato, + rd_a_i => ch_5_coeffs_val_rreq, + wr_a_i => ch_5_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_5_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_5_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_5_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_5_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_coeffs_val_rack <= '0'; + else + ch_5_coeffs_val_rack <= ch_5_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_6_coeffs + process (adr_int, wr_adr_d0, ch_6_coeffs_wr) begin + if ch_6_coeffs_wr = '1' then + ch_6_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_6_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_6_coeffs_wreq <= ch_6_coeffs_val_int_wr; + ch_6_coeffs_wr <= ch_6_coeffs_wreq; + ch_6_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_6_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_6_coeffs_val_int_dato, + rd_a_i => ch_6_coeffs_val_rreq, + wr_a_i => ch_6_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_6_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_6_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_6_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_6_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_coeffs_val_rack <= '0'; + else + ch_6_coeffs_val_rack <= ch_6_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_7_coeffs + process (adr_int, wr_adr_d0, ch_7_coeffs_wr) begin + if ch_7_coeffs_wr = '1' then + ch_7_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_7_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_7_coeffs_wreq <= ch_7_coeffs_val_int_wr; + ch_7_coeffs_wr <= ch_7_coeffs_wreq; + ch_7_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_7_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_7_coeffs_val_int_dato, + rd_a_i => ch_7_coeffs_val_rreq, + wr_a_i => ch_7_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_7_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_7_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_7_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_7_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_coeffs_val_rack <= '0'; + else + ch_7_coeffs_val_rack <= ch_7_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_8_coeffs + process (adr_int, wr_adr_d0, ch_8_coeffs_wr) begin + if ch_8_coeffs_wr = '1' then + ch_8_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_8_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_8_coeffs_wreq <= ch_8_coeffs_val_int_wr; + ch_8_coeffs_wr <= ch_8_coeffs_wreq; + ch_8_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_8_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_8_coeffs_val_int_dato, + rd_a_i => ch_8_coeffs_val_rreq, + wr_a_i => ch_8_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_8_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_8_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_8_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_8_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_coeffs_val_rack <= '0'; + else + ch_8_coeffs_val_rack <= ch_8_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_9_coeffs + process (adr_int, wr_adr_d0, ch_9_coeffs_wr) begin + if ch_9_coeffs_wr = '1' then + ch_9_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_9_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_9_coeffs_wreq <= ch_9_coeffs_val_int_wr; + ch_9_coeffs_wr <= ch_9_coeffs_wreq; + ch_9_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_9_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_9_coeffs_val_int_dato, + rd_a_i => ch_9_coeffs_val_rreq, + wr_a_i => ch_9_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_9_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_9_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_9_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_9_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_coeffs_val_rack <= '0'; + else + ch_9_coeffs_val_rack <= ch_9_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_10_coeffs + process (adr_int, wr_adr_d0, ch_10_coeffs_wr) begin + if ch_10_coeffs_wr = '1' then + ch_10_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_10_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_10_coeffs_wreq <= ch_10_coeffs_val_int_wr; + ch_10_coeffs_wr <= ch_10_coeffs_wreq; + ch_10_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_10_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_10_coeffs_val_int_dato, + rd_a_i => ch_10_coeffs_val_rreq, + wr_a_i => ch_10_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_10_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_10_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_10_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_10_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_coeffs_val_rack <= '0'; + else + ch_10_coeffs_val_rack <= ch_10_coeffs_val_rreq; + end if; + end if; + end process; + + -- Memory ch_11_coeffs + process (adr_int, wr_adr_d0, ch_11_coeffs_wr) begin + if ch_11_coeffs_wr = '1' then + ch_11_coeffs_adr_int <= wr_adr_d0(7 downto 2); + else + ch_11_coeffs_adr_int <= adr_int(7 downto 2); + end if; + end process; + ch_11_coeffs_wreq <= ch_11_coeffs_val_int_wr; + ch_11_coeffs_wr <= ch_11_coeffs_wreq; + ch_11_coeffs_val_raminst: cheby_dpssram + generic map ( + g_data_width => 32, + g_size => 64, + g_addr_width => 6, + g_dual_clock => '0', + g_use_bwsel => '1' + ) + port map ( + clk_a_i => clk_i, + clk_b_i => clk_i, + addr_a_i => ch_11_coeffs_adr_int, + bwsel_a_i => wr_sel_d0, + data_a_i => wr_dat_d0, + data_a_o => ch_11_coeffs_val_int_dato, + rd_a_i => ch_11_coeffs_val_rreq, + wr_a_i => ch_11_coeffs_val_int_wr, + addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_11_coeffs_adr_i, + bwsel_b_i => (others => '1'), + data_b_i => ch_11_coeffs_val_ext_dat, + data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_11_coeffs_val_dat_o, + rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_11_coeffs_val_rd_i, + wr_b_i => '0' + ); + + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_coeffs_val_rack <= '0'; + else + ch_11_coeffs_val_rack <= ch_11_coeffs_val_rreq; + end if; + end if; + end process; + + -- Register max_filt_order + + -- Register coeffs_fp_repr + + -- Register ctl + wb_fofb_shaper_filt_regs_ifc_o.ctl_eff_coeffs <= ctl_eff_coeffs_reg; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ctl_eff_coeffs_reg <= '0'; + ctl_wack <= '0'; + else + if ctl_wreq = '1' then + ctl_eff_coeffs_reg <= wr_dat_d0(0); + else + ctl_eff_coeffs_reg <= '0'; + end if; + ctl_wack <= ctl_wreq; + end if; + end if; + end process; + + -- Process for write requests. + process (wr_adr_d0, wr_req_d0, ctl_wack) begin + ch_0_coeffs_val_int_wr <= '0'; + ch_1_coeffs_val_int_wr <= '0'; + ch_2_coeffs_val_int_wr <= '0'; + ch_3_coeffs_val_int_wr <= '0'; + ch_4_coeffs_val_int_wr <= '0'; + ch_5_coeffs_val_int_wr <= '0'; + ch_6_coeffs_val_int_wr <= '0'; + ch_7_coeffs_val_int_wr <= '0'; + ch_8_coeffs_val_int_wr <= '0'; + ch_9_coeffs_val_int_wr <= '0'; + ch_10_coeffs_val_int_wr <= '0'; + ch_11_coeffs_val_int_wr <= '0'; + ctl_wreq <= '0'; + case wr_adr_d0(12 downto 8) is + when "00000" => + -- Memory ch_0_coeffs + ch_0_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00001" => + -- Memory ch_1_coeffs + ch_1_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00010" => + -- Memory ch_2_coeffs + ch_2_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00011" => + -- Memory ch_3_coeffs + ch_3_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00100" => + -- Memory ch_4_coeffs + ch_4_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00101" => + -- Memory ch_5_coeffs + ch_5_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00110" => + -- Memory ch_6_coeffs + ch_6_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "00111" => + -- Memory ch_7_coeffs + ch_7_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01000" => + -- Memory ch_8_coeffs + ch_8_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01001" => + -- Memory ch_9_coeffs + ch_9_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01010" => + -- Memory ch_10_coeffs + ch_10_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "01011" => + -- Memory ch_11_coeffs + ch_11_coeffs_val_int_wr <= wr_req_d0; + wr_ack_int <= wr_req_d0; + when "10000" => + case wr_adr_d0(7 downto 2) is + when "000000" => + -- Reg max_filt_order + wr_ack_int <= wr_req_d0; + when "000001" => + -- Reg coeffs_fp_repr + wr_ack_int <= wr_req_d0; + when "000010" => + -- Reg ctl + ctl_wreq <= wr_req_d0; + wr_ack_int <= ctl_wack; + when others => + wr_ack_int <= wr_req_d0; + end case; + when others => + wr_ack_int <= wr_req_d0; + end case; + end process; + + -- Process for read requests. + process (adr_int, ch_0_coeffs_val_int_dato, rd_req_int, ch_0_coeffs_val_rack, + ch_1_coeffs_val_int_dato, ch_1_coeffs_val_rack, + ch_2_coeffs_val_int_dato, ch_2_coeffs_val_rack, + ch_3_coeffs_val_int_dato, ch_3_coeffs_val_rack, + ch_4_coeffs_val_int_dato, ch_4_coeffs_val_rack, + ch_5_coeffs_val_int_dato, ch_5_coeffs_val_rack, + ch_6_coeffs_val_int_dato, ch_6_coeffs_val_rack, + ch_7_coeffs_val_int_dato, ch_7_coeffs_val_rack, + ch_8_coeffs_val_int_dato, ch_8_coeffs_val_rack, + ch_9_coeffs_val_int_dato, ch_9_coeffs_val_rack, + ch_10_coeffs_val_int_dato, ch_10_coeffs_val_rack, + ch_11_coeffs_val_int_dato, ch_11_coeffs_val_rack, + wb_fofb_shaper_filt_regs_ifc_i.max_filt_order, + wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_int_width, + wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_frac_width) begin + -- By default ack read requests + rd_dat_d0 <= (others => 'X'); + ch_0_coeffs_val_rreq <= '0'; + ch_1_coeffs_val_rreq <= '0'; + ch_2_coeffs_val_rreq <= '0'; + ch_3_coeffs_val_rreq <= '0'; + ch_4_coeffs_val_rreq <= '0'; + ch_5_coeffs_val_rreq <= '0'; + ch_6_coeffs_val_rreq <= '0'; + ch_7_coeffs_val_rreq <= '0'; + ch_8_coeffs_val_rreq <= '0'; + ch_9_coeffs_val_rreq <= '0'; + ch_10_coeffs_val_rreq <= '0'; + ch_11_coeffs_val_rreq <= '0'; + case adr_int(12 downto 8) is + when "00000" => + -- Memory ch_0_coeffs + rd_dat_d0 <= ch_0_coeffs_val_int_dato; + ch_0_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_0_coeffs_val_rack; + when "00001" => + -- Memory ch_1_coeffs + rd_dat_d0 <= ch_1_coeffs_val_int_dato; + ch_1_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_1_coeffs_val_rack; + when "00010" => + -- Memory ch_2_coeffs + rd_dat_d0 <= ch_2_coeffs_val_int_dato; + ch_2_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_2_coeffs_val_rack; + when "00011" => + -- Memory ch_3_coeffs + rd_dat_d0 <= ch_3_coeffs_val_int_dato; + ch_3_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_3_coeffs_val_rack; + when "00100" => + -- Memory ch_4_coeffs + rd_dat_d0 <= ch_4_coeffs_val_int_dato; + ch_4_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_4_coeffs_val_rack; + when "00101" => + -- Memory ch_5_coeffs + rd_dat_d0 <= ch_5_coeffs_val_int_dato; + ch_5_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_5_coeffs_val_rack; + when "00110" => + -- Memory ch_6_coeffs + rd_dat_d0 <= ch_6_coeffs_val_int_dato; + ch_6_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_6_coeffs_val_rack; + when "00111" => + -- Memory ch_7_coeffs + rd_dat_d0 <= ch_7_coeffs_val_int_dato; + ch_7_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_7_coeffs_val_rack; + when "01000" => + -- Memory ch_8_coeffs + rd_dat_d0 <= ch_8_coeffs_val_int_dato; + ch_8_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_8_coeffs_val_rack; + when "01001" => + -- Memory ch_9_coeffs + rd_dat_d0 <= ch_9_coeffs_val_int_dato; + ch_9_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_9_coeffs_val_rack; + when "01010" => + -- Memory ch_10_coeffs + rd_dat_d0 <= ch_10_coeffs_val_int_dato; + ch_10_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_10_coeffs_val_rack; + when "01011" => + -- Memory ch_11_coeffs + rd_dat_d0 <= ch_11_coeffs_val_int_dato; + ch_11_coeffs_val_rreq <= rd_req_int; + rd_ack_d0 <= ch_11_coeffs_val_rack; + when "10000" => + case adr_int(7 downto 2) is + when "000000" => + -- Reg max_filt_order + rd_ack_d0 <= rd_req_int; + rd_dat_d0 <= wb_fofb_shaper_filt_regs_ifc_i.max_filt_order; + when "000001" => + -- Reg coeffs_fp_repr + rd_ack_d0 <= rd_req_int; + rd_dat_d0(4 downto 0) <= wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_int_width; + rd_dat_d0(9 downto 5) <= wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_frac_width; + rd_dat_d0(31 downto 10) <= (others => '0'); + when "000010" => + -- Reg ctl + rd_ack_d0 <= rd_req_int; + rd_dat_d0(0) <= '0'; + rd_dat_d0(31 downto 1) <= (others => '0'); + when others => + rd_ack_d0 <= rd_req_int; + end case; + when others => + rd_ack_d0 <= rd_req_int; + end case; + end process; +end syn; diff --git a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd new file mode 100644 index 00000000..6e56693c --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd @@ -0,0 +1,35 @@ +-------------------------------------------------------------------------------- +-- Title : FOFB shaper filters package +-- Project : fofb-ctrl-gw +-------------------------------------------------------------------------------- +-- File : fofb_shaper_filt_pkg.vhd +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Generic +-- Standard : VHDL'08 +-------------------------------------------------------------------------------- +-- Description: Package for FOFB shaper filters stuff. +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-09-28 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.fixed_pkg.ALL; + +LIBRARY work; +USE work.wishbone_pkg.ALL; + +PACKAGE fofb_shaper_filt_pkg IS + -- The maximum filter order supported + CONSTANT c_MAX_FILT_ORDER : NATURAL := 10; + + -- The signed fixed-point representation of filters' coefficients + CONSTANT c_COEFF_INT_WIDTH : NATURAL := 2; + CONSTANT c_COEFF_FRAC_WIDTH : NATURAL := 16; +END PACKAGE fofb_shaper_filt_pkg; diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd new file mode 100644 index 00000000..1416957b --- /dev/null +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -0,0 +1,397 @@ +-------------------------------------------------------------------------------- +-- Title : FOFB Shaper Filters Wrapper +-- Project : fofb-ctrl-gw +-------------------------------------------------------------------------------- +-- File : xwb_fofb_shaper_filt.vhd +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Generic +-- Standard : VHDL'08 +-------------------------------------------------------------------------------- +-- Description: Instantiates FOFB shaper filters and exposes coefficients +-- settings on a Wishbone bus. +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-09-28 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.fixed_pkg.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY work; +USE work.ifc_common_pkg.ALL; +USE work.fofb_ctrl_pkg.ALL; +USE work.fofb_shaper_filt_pkg.ALL; +USE work.wb_fofb_shaper_filt_regs_pkg.ALL; +USE work.wishbone_pkg.ALL; + +ENTITY xwb_fofb_shaper_filt IS + GENERIC ( + -- Number of channels + g_CHANNELS : NATURAL; + + -- Extra bits for biquads' internal arithmetic + g_ARITH_EXTRA_BITS : NATURAL; + -- Extra bits for between-biquads cascade interfaces + g_IFCS_EXTRA_BITS : NATURAL; + + -- Wishbone generics + g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; + g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; + g_WITH_EXTRA_WB_REG : BOOLEAN := FALSE + ); + PORT ( + -- Clock + clk_i : IN STD_LOGIC; + -- Reset + rst_n_i : IN STD_LOGIC; + + -- Setpoints array + sp_arr_i : IN t_sp_arr(g_CHANNELS-1 DOWNTO 0); + -- Setpoints valid array + sp_valid_arr_i : IN STD_LOGIC_VECTOR(g_CHANNELS-1 DOWNTO 0); + + -- Filtered setpoints array + filt_sp_arr_o : OUT t_sp_arr(g_CHANNELS-1 DOWNTO 0); + -- Filtered setpoints valid array + filt_sp_valid_arr_o : OUT STD_LOGIC_VECTOR(g_CHANNELS-1 DOWNTO 0); + + -- Wishbone interface + wb_slv_i : IN t_wishbone_slave_in; + wb_slv_o : OUT t_wishbone_slave_out + ); +END ENTITY xwb_fofb_shaper_filt; + +ARCHITECTURE behave OF xwb_fofb_shaper_filt IS + TYPE t_iir_filts_x_or_y IS ARRAY (NATURAL RANGE <>) of SFIXED; + TYPE t_fofb_shaper_filt_coeffs IS + ARRAY (NATURAL RANGE <>) OF t_iir_filt_coeffs; + + TYPE t_wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat IS + ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 downto 0); + + -- Number of bits in Wishbone register interface + -- +2 to account for BYTE addressing + CONSTANT c_PERIPH_ADDR_SIZE : NATURAL := 2+2; + + CONSTANT c_MAX_CHANNELS : NATURAL := 12; + + CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; + CONSTANT c_NUM_OF_COEFFS_PER_FILT : NATURAL := 5*c_NUM_OF_BIQUADS_PER_FILT; + + -- The signed fixed-point representation of coefficients is aligned to the + -- left in Wishbone registers + PURE FUNCTION f_parse_wb_coeff(wb_coeff : STD_LOGIC_VECTOR) + RETURN SFIXED IS + BEGIN + RETURN to_sfixed(wb_coeff(31 DOWNTO + 32-(c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH)), c_COEFF_INT_WIDTH-1, + -c_COEFF_FRAC_WIDTH); + END f_parse_wb_coeff; + + SIGNAL iir_filts_x, iir_filts_y : t_iir_filts_x_or_y(g_CHANNELS-1 DOWNTO 0)( + c_SP_WIDTH-1 DOWNTO -1); + + -- Wishbone signals + SIGNAL wb_slv_adp_in : t_wishbone_master_in; + SIGNAL wb_slv_adp_out : t_wishbone_master_out; + SIGNAL resized_addr : STD_LOGIC_VECTOR(c_WISHBONE_ADDRESS_WIDTH-1 DOWNTO 0); + SIGNAL wb_slave_in : t_wishbone_slave_in_array(0 DOWNTO 0); + SIGNAL wb_slave_out : t_wishbone_slave_out_array(0 DOWNTO 0); + -- Extra Wishbone registering stage + SIGNAL wb_slave_in_d1 : t_wishbone_slave_in_array(0 DOWNTO 0); + SIGNAL wb_slave_out_d1 : t_wishbone_slave_out_array(0 DOWNTO 0); + + SIGNAL wb_fofb_shaper_filt_regs_ifc_master_in : + t_wb_fofb_shaper_filt_regs_ifc_master_in; + SIGNAL wb_fofb_shaper_filt_regs_ifc_master_out : + t_wb_fofb_shaper_filt_regs_ifc_master_out; + SIGNAL wb_fofb_shaper_filt_regs_ifc_coeffs_adr : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat : + t_wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(c_MAX_CHANNELS-1 DOWNTO 0); + + SIGNAL state : NATURAL RANGE 0 TO 2 := 0; + SIGNAL coeffs : t_fofb_shaper_filt_coeffs(g_CHANNELS-1 DOWNTO 0)( + c_NUM_OF_BIQUADS_PER_FILT-1 DOWNTO 0)( + b0(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), + b1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), + b2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), + a1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), + a2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH)); +BEGIN + ASSERT c_MAX_FILT_ORDER <= 20 + REPORT "ABI supports up to 20th order filters" + SEVERITY ERROR; + + ASSERT c_COEFF_INT_WIDTH > 1 and c_COEFF_FRAC_WIDTH > 1 and + c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH <= 32 + REPORT "ABI supports at most 32-bits coefficients (c_COEFF_INT_WIDTH + " & + "c_COEFF_FRAC_WIDTH). Also, the SFIXED type requires each of these" & + "to be at least 1." + SEVERITY ERROR; + + PROCESS(clk_i) IS + VARIABLE v_biquad_idx : NATURAL RANGE 0 to c_NUM_OF_BIQUADS_PER_FILT-1 := 0; + VARIABLE v_coeff_idx : NATURAL RANGE 0 to c_NUM_OF_COEFFS_PER_FILT-1 := 0; + BEGIN + IF rising_edge(clk_i) THEN + IF rst_n_i = '0' THEN + state <= 0; + v_coeff_idx := 0; + ELSE + CASE state IS + -- Waits for strobe signal + WHEN 0 => + IF wb_fofb_shaper_filt_regs_ifc_master_out.ctl_eff_coeffs THEN + state <= 1; + END IF; + v_coeff_idx := 0; + + -- Waits for coefficients RAMs' output update + WHEN 1 => + state <= 2; + + -- Effectivates (i.e. updates) coefficients + -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads. Each of these + -- takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). Each iir_filt + -- has a dedicated RAM holding its coefficients. These RAMs are + -- populated in the following manner: + -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + -- coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + -- coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + -- coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + -- coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + -- RAMs are accessed in parallel. + WHEN 2 => + v_biquad_idx := v_coeff_idx/5; + FOR ch IN 0 TO g_CHANNELS-1 + LOOP + CASE v_coeff_idx REM 5 IS + WHEN 0 => + coeffs(ch)(v_biquad_idx).b0 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); + + WHEN 1 => + coeffs(ch)(v_biquad_idx).b1 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); + + + WHEN 2 => + coeffs(ch)(v_biquad_idx).b2 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); + + WHEN 3 => + coeffs(ch)(v_biquad_idx).a1 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); + + WHEN 4 => + coeffs(ch)(v_biquad_idx).a2 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); + + WHEN OTHERS => + END CASE; + END LOOP; + + IF v_coeff_idx = c_NUM_OF_COEFFS_PER_FILT-1 THEN + state <= 0; + ELSE + v_coeff_idx := v_coeff_idx + 1; + state <= 1; + END IF; + END CASE; + + -- Addresses coefficients RAMs + -- The state machine above computes the address and waits a cycle for + -- output to update + wb_fofb_shaper_filt_regs_ifc_coeffs_adr <= + STD_LOGIC_VECTOR(to_unsigned(v_coeff_idx, + wb_fofb_shaper_filt_regs_ifc_coeffs_adr'LENGTH)); + END IF; + END IF; + END PROCESS; + + gen_iir_filts : FOR idx IN 0 TO g_CHANNELS-1 + GENERATE + cmp_iir_filt : iir_filt + GENERIC MAP ( + g_MAX_FILT_ORDER => c_MAX_FILT_ORDER, + g_X_INT_WIDTH => c_SP_WIDTH, + g_X_FRAC_WIDTH => 1, -- see note below + g_COEFF_INT_WIDTH => c_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => c_COEFF_FRAC_WIDTH, + g_Y_INT_WIDTH => c_SP_WIDTH, + g_Y_FRAC_WIDTH => 1, -- see note below + g_ARITH_EXTRA_BITS => g_ARITH_EXTRA_BITS, + g_IFCS_EXTRA_BITS => g_IFCS_EXTRA_BITS + ) + PORT MAP ( + clk_i => clk_i, + rst_n_i => rst_n_i, + x_i => iir_filts_x(idx), + x_valid_i => sp_valid_arr_i(idx), + coeffs_i => coeffs(idx), + y_o => iir_filts_y(idx), + y_valid_o => filt_sp_valid_arr_o(idx) + ); + + -- see note below + iir_filts_x(idx) <= to_sfixed(sp_arr_i(idx), c_SP_WIDTH-1, -1); + filt_sp_arr_o(idx) <= to_signed(iir_filts_y(idx), c_SP_WIDTH); + + -- NOTE: SFIXED type must have at least 1 fractionary digit + END GENERATE gen_iir_filts; + + cmp_wb_fofb_shaper_filt_regs : ENTITY work.wb_fofb_shaper_filt_regs + PORT MAP ( + clk_i => clk_i, + rst_n_i => rst_n_i, + wb_i => wb_slv_adp_out, + wb_o => wb_slv_adp_in, + wb_fofb_shaper_filt_regs_ifc_i => wb_fofb_shaper_filt_regs_ifc_master_in, + wb_fofb_shaper_filt_regs_ifc_o => wb_fofb_shaper_filt_regs_ifc_master_out + ); + + -- Extra Wishbone registering stage for ease timing + -- NOTE: It effectively cuts the bandwidth in half! + gen_with_extra_wb_reg : IF g_WITH_EXTRA_WB_REG GENERATE + cmp_register_link : xwb_register_link -- puts a register of delay between + PORT MAP ( -- crossbars + clk_sys_i => clk_i, + rst_n_i => rst_n_i, + slave_i => wb_slave_in_d1(0), + slave_o => wb_slave_out_d1(0), + master_i => wb_slave_out(0), + master_o => wb_slave_in(0) + ); + + wb_slave_in_d1(0) <= wb_slv_i; + wb_slv_o <= wb_slave_out_d1(0); + ELSE GENERATE + -- External master connection + wb_slave_in(0) <= wb_slv_i; + wb_slv_o <= wb_slave_out(0); + END GENERATE; + + -- Wishbone slave adapter + cmp_slave_adapter : wb_slave_adapter + GENERIC MAP ( + g_MASTER_USE_STRUCT => TRUE, + g_MASTER_MODE => PIPELINED, + -- TODO: it seems that using cheby without wbgen compatibility requires + -- g_MASTER_GRANULARITY to be byte + g_MASTER_GRANULARITY => BYTE, + g_SLAVE_USE_STRUCT => FALSE, + g_SLAVE_MODE => g_INTERFACE_MODE, + g_SLAVE_GRANULARITY => g_ADDRESS_GRANULARITY + ) + PORT MAP ( + clk_sys_i => clk_i, + rst_n_i => rst_n_i, + master_i => wb_slv_adp_in, + master_o => wb_slv_adp_out, + sl_adr_i => resized_addr, + sl_dat_i => wb_slave_in(0).dat, + sl_sel_i => wb_slave_in(0).sel, + sl_cyc_i => wb_slave_in(0).cyc, + sl_stb_i => wb_slave_in(0).stb, + sl_we_i => wb_slave_in(0).we, + sl_dat_o => wb_slave_out(0).dat, + sl_ack_o => wb_slave_out(0).ack, + sl_rty_o => wb_slave_out(0).rty, + sl_err_o => wb_slave_out(0).err, + sl_stall_o => wb_slave_out(0).stall + ); + + gen_wb_slave_in_addr_conn : IF g_ADDRESS_GRANULARITY = WORD GENERATE + -- By doing this zeroing we avoid the issue related to BYTE -> WORD + -- conversion slave addressing (possibly performed by the slave adapter + -- component) in which a bit in the MSB of the peripheral addressing part + -- (31 DOWNTO c_PERIPH_ADDR_SIZE in our case) is shifted to the internal + -- register adressing part (c_PERIPH_ADDR_SIZE-1 DOWNTO 0 in our case). + -- Therefore, possibly changing the these bits! + resized_addr(c_PERIPH_ADDR_SIZE-1 DOWNTO 0) <= + wb_slave_in(0).adr(c_PERIPH_ADDR_SIZE-1 DOWNTO 0); + resized_addr(c_WISHBONE_ADDRESS_WIDTH-1 DOWNTO c_PERIPH_ADDR_SIZE) <= + (OTHERS => '0'); + ELSE GENERATE + resized_addr <= wb_slave_in(0).adr; + END GENERATE; + + wb_fofb_shaper_filt_regs_ifc_master_in.ch_0_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_0_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_1_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_1_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_2_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_2_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_3_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_3_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_4_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_4_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_5_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_5_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_6_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_6_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_7_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_7_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_8_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_8_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_9_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_9_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_10_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_10_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_11_coeffs_adr_i <= + wb_fofb_shaper_filt_regs_ifc_coeffs_adr; + wb_fofb_shaper_filt_regs_ifc_master_in.ch_11_coeffs_val_rd_i <= '0'; + wb_fofb_shaper_filt_regs_ifc_master_in.max_filt_order <= + STD_LOGIC_VECTOR(to_unsigned(c_MAX_FILT_ORDER, + wb_fofb_shaper_filt_regs_ifc_master_in.max_filt_order'LENGTH)); + wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_int_width <= + STD_LOGIC_VECTOR(to_unsigned(c_COEFF_INT_WIDTH, + wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_int_width'LENGTH)); + wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_frac_width <= + STD_LOGIC_VECTOR(to_unsigned(c_COEFF_FRAC_WIDTH, + wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_frac_width'LENGTH)); + + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(0) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_0_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(1) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_1_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(2) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_2_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(3) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_3_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(4) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_4_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(5) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_5_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(6) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_6_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(7) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_7_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(8) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_8_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(9) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_9_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(10) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_10_coeffs_val_dat_o; + wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(11) <= + wb_fofb_shaper_filt_regs_ifc_master_out.ch_11_coeffs_val_dat_o; +END ARCHITECTURE behave; diff --git a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd new file mode 100644 index 00000000..cbfe4a05 --- /dev/null +++ b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd @@ -0,0 +1,75 @@ +-- Do not edit. Generated by cheby 1.6.dev0 using these options: +-- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd +-- Generated on Fri Sep 22 15:10:27 2023 by guilherme.ricioli + +package wb_fofb_shaper_filt_regs_consts_pkg is + constant c_WB_FOFB_SHAPER_FILT_REGS_SIZE : Natural := 4108; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_SIZE : Natural := 4096; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_ADDR : Natural := 16#100#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_COEFFS_ADDR : Natural := 16#100#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_ADDR : Natural := 16#200#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_COEFFS_ADDR : Natural := 16#200#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_ADDR : Natural := 16#300#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_COEFFS_ADDR : Natural := 16#300#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_ADDR : Natural := 16#400#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_COEFFS_ADDR : Natural := 16#400#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_ADDR : Natural := 16#500#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_COEFFS_ADDR : Natural := 16#500#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_ADDR : Natural := 16#600#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_COEFFS_ADDR : Natural := 16#600#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_ADDR : Natural := 16#700#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_COEFFS_ADDR : Natural := 16#700#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_ADDR : Natural := 16#800#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_COEFFS_ADDR : Natural := 16#800#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_ADDR : Natural := 16#900#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_COEFFS_ADDR : Natural := 16#900#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_ADDR : Natural := 16#a00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_COEFFS_ADDR : Natural := 16#a00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_ADDR : Natural := 16#b00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_ADDR : Natural := 16#b00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_SIZE : Natural := 4; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_VAL_ADDR : Natural := 16#0#; + constant c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR : Natural := 16#1000#; + constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_ADDR : Natural := 16#1004#; + constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET : Natural := 0; + constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET : Natural := 5; + constant c_WB_FOFB_SHAPER_FILT_REGS_CTL_ADDR : Natural := 16#1008#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CTL_EFF_COEFFS_OFFSET : Natural := 0; +end package wb_fofb_shaper_filt_regs_consts_pkg; diff --git a/hdl/testbench/xwb_fofb_shaper_filt/Manifest.py b/hdl/testbench/xwb_fofb_shaper_filt/Manifest.py new file mode 100644 index 00000000..b9eeff45 --- /dev/null +++ b/hdl/testbench/xwb_fofb_shaper_filt/Manifest.py @@ -0,0 +1,15 @@ +files = [ + "xwb_fofb_shaper_filt_tb.vhd", + "../../sim/sim_wishbone.vhd", + "../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd", + "../fofb_tb_pkg.vhd", +] + +modules = { + "local" : [ + "../../ip_cores/CommsCtrlFPGA", + "../../ip_cores/general-cores", + "../../ip_cores/infra-cores", + "../../modules", + ], +} diff --git a/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat new file mode 100644 index 00000000..aa4deb88 --- /dev/null +++ b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat @@ -0,0 +1,12 @@ +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 +2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 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-1.11022302e-16 7.29453817e-01 diff --git a/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_x_y.dat b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_x_y.dat new file mode 100644 index 00000000..422788ad --- /dev/null +++ b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_x_y.dat @@ -0,0 +1,200 @@ + 29569 29569 29569 29569 29569 29569 29569 29569 29569 29569 29569 29569 86 86 86 86 86 86 86 86 86 86 86 86 + 18584 18584 18584 18584 18584 18584 18584 18584 18584 18584 18584 18584 910 910 910 910 910 910 910 910 910 910 910 910 +-12503 -12503 -12503 -12503 -12503 -12503 -12503 -12503 -12503 -12503 -12503 -12503 4241 4241 4241 4241 4241 4241 4241 4241 4241 4241 4241 4241 + 26626 26626 26626 26626 26626 26626 26626 26626 26626 26626 26626 26626 11194 11194 11194 11194 11194 11194 11194 11194 11194 11194 11194 11194 + 3471 3471 3471 3471 3471 3471 3471 3471 3471 3471 3471 3471 17865 17865 17865 17865 17865 17865 17865 17865 17865 17865 17865 17865 + 1210 1210 1210 1210 1210 1210 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b/hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py new file mode 100644 index 00000000..ae0285c6 --- /dev/null +++ b/hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py @@ -0,0 +1,11 @@ +action = "simulation" +sim_tool = "ghdl" +ghdl_opt = "--std=08 -frelaxed" + +target = "xilinx" +syn_device = "xc7a200t" + +top_module = "xwb_fofb_shaper_filt_tb" +modules = {"local" : ["../"]} + +sim_post_cmd = "ghdl -r --std=08 %s --wave=%s.ghw --assert-level=error" % (top_module, top_module) diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd new file mode 100644 index 00000000..9ec22342 --- /dev/null +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -0,0 +1,225 @@ +-------------------------------------------------------------------------------- +-- Title : Testbench for the FOFB Shaper Filters Wrapper +-------------------------------------------------------------------------------- +-- Author : Guilherme Ricioli +-- Company : CNPEM, LNLS - GIE +-- Platform : Simulation +-- Standard : VHDL'08 +-------------------------------------------------------------------------------- +-- Description : +-------------------------------------------------------------------------------- +-- Copyright (c) 2023 CNPEM +-- Licensed under GNU Lesser General Public License (LGPL) v3.0 +-------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2023-09-26 1.0 guilherme.ricioli Created +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.fixed_pkg.ALL; +USE ieee.numeric_std.ALL; +USE ieee.std_logic_1164.ALL; + +LIBRARY std; +USE std.env.finish; +USE std.textio.ALL; + +LIBRARY work; +USE work.fofb_ctrl_pkg.ALL; +USE work.fofb_shaper_filt_pkg.ALL; +USE work.fofb_tb_pkg.ALL; +USE work.sim_wishbone.ALL; +USE work.wishbone_pkg.ALL; +USE work.wb_fofb_shaper_filt_regs_consts_pkg.ALL; + +ENTITY xwb_fofb_shaper_filt_tb IS + GENERIC ( + -- Number of channels + g_CHANNELS : NATURAL := 12; + + -- File containing filters' coefficients + g_TEST_COEFFS_FILENAME : STRING := "../fofb_shaper_filt_coeffs.dat"; + -- File containing the values for x and the expected values for y + g_TEST_X_Y_FILENAME : STRING := "../fofb_shaper_filt_x_y.dat"; + + -- Extra bits for biquads' internal arithmetic + g_ARITH_EXTRA_BITS : NATURAL := 0; + -- Extra bits for between-biquads cascade interfaces + g_IFCS_EXTRA_BITS : NATURAL := 4 + ); +END ENTITY xwb_fofb_shaper_filt_tb; + +ARCHITECTURE test OF xwb_fofb_shaper_filt_tb IS + CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; + CONSTANT c_NUM_OF_COEFFS_PER_FILT : NATURAL := 5*c_NUM_OF_BIQUADS_PER_FILT; + CONSTANT c_SYS_CLOCK_FREQ : NATURAL := 100_000_000; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rst_n : STD_LOGIC := '1'; + SIGNAL sp_arr, filt_sp_arr : t_sp_arr(g_CHANNELS-1 DOWNTO 0); + SIGNAL sp_valid_arr, filt_sp_valid_arr : + STD_LOGIC_VECTOR(g_CHANNELS-1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL wb_slave_i : t_wishbone_slave_in; + SIGNAL wb_slave_o : t_wishbone_slave_out; + +BEGIN + f_gen_clk(c_SYS_CLOCK_FREQ, clk); + + PROCESS + FILE fin : TEXT; + VARIABLE lin : LINE; + VARIABLE v_wb_addr : NATURAL := 0; + VARIABLE v_wb_dat : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + VARIABLE v_coeff : REAL; + VARIABLE v_x_or_y : INTEGER; + BEGIN + init(wb_slave_i); + f_wait_cycles(clk, 10); + + rst_n <= '0'; + f_wait_cycles(clk, 10); + rst_n <= '1'; + f_wait_cycles(clk, 1); + + -- Reads maximum filter order + read32_pl(clk, wb_slave_i, wb_slave_o, + c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR, v_wb_dat); + + ASSERT to_integer(UNSIGNED(v_wb_dat)) = c_MAX_FILT_ORDER + REPORT + "UNEXPECTED MAXIMUM FILTER ORDER: " + & NATURAL'image(to_integer(UNSIGNED(v_wb_dat))) + & " (EXPECTED: " + & NATURAL'image(c_MAX_FILT_ORDER) & ")" + SEVERITY ERROR; + + -- Read coefficients' fixed-point representation + read32_pl(clk, wb_slave_i, wb_slave_o, + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_ADDR, v_wb_dat); + + ASSERT to_integer(UNSIGNED(v_wb_dat( + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET-1 DOWNTO + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET))) = + c_COEFF_INT_WIDTH + REPORT + "UNEXPECTED COEFFICIENTS' INTEGER WIDTH: " + & NATURAL'image(to_integer(UNSIGNED(v_wb_dat( + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET-1 DOWNTO + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET)))) + & " (EXPECTED: " + & NATURAL'image(c_COEFF_INT_WIDTH) & ")" + SEVERITY ERROR; + + -- TODO: +4 hardcoded + ASSERT to_integer(UNSIGNED(v_wb_dat( + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET+4 DOWNTO + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET))) = + c_COEFF_FRAC_WIDTH + REPORT + "UNEXPECTED COEFFICIENTS' FRACTIONARY WIDTH: " + & NATURAL'image(to_integer(UNSIGNED(v_wb_dat( + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET+4 DOWNTO + c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET)))) + & " (EXPECTED: " + & NATURAL'image(c_COEFF_FRAC_WIDTH) & ")" + SEVERITY ERROR; + + -- Load filter coefficients + file_open(fin, g_TEST_COEFFS_FILENAME, read_mode); + FOR ch_idx IN 0 TO g_CHANNELS-1 + LOOP + v_wb_addr := c_WB_FOFB_SHAPER_FILT_REGS_CH_ADDR + + ch_idx*c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE; + + readline(fin, lin); + FOR coeff_idx IN 0 TO c_NUM_OF_COEFFS_PER_FILT-1 + LOOP + read(lin, v_coeff); + -- The signed fixed-point representation of coefficients is aligned to + -- the left in Wishbone registers + v_wb_dat := ( + 31 DOWNTO 32-(c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH) => + to_slv(to_sfixed(v_coeff, c_COEFF_INT_WIDTH-1, + -c_COEFF_FRAC_WIDTH)), + OTHERS => '0'); + write32_pl(clk, wb_slave_i, wb_slave_o, v_wb_addr, v_wb_dat); + + v_wb_addr := v_wb_addr + c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE; + END LOOP; + END LOOP; + file_close(fin); + + -- Effectivate (update) filter coefficients + v_wb_dat := (c_WB_FOFB_SHAPER_FILT_REGS_CTL_EFF_COEFFS_OFFSET => '1', + OTHERS => '0'); + write32_pl(clk, wb_slave_i, wb_slave_o, c_WB_FOFB_SHAPER_FILT_REGS_CTL_ADDR, + v_wb_dat); + + -- Wait for coefficients to be effectivated + -- Coefficients RAMs are accessed in parallel and each of the + -- c_NUM_OF_COEFFS_PER_FILT coefficients takes 2 cycles for being + -- effectivated. The +1 is accounting for the command detection cycle. + f_wait_cycles(clk, 2*c_NUM_OF_COEFFS_PER_FILT+1); + + file_open(fin, g_TEST_X_Y_FILENAME, read_mode); + WHILE NOT endfile(fin) + LOOP + readline(fin, lin); + + FOR ch_idx IN 0 TO g_CHANNELS-1 + LOOP + read(lin, v_x_or_y); + sp_arr(ch_idx) <= to_signed(v_x_or_y, sp_arr(ch_idx)'LENGTH); + sp_valid_arr(ch_idx) <= '1'; + END LOOP; + f_wait_cycles(clk, 1); + + FOR ch_idx IN 0 TO g_CHANNELS-1 + LOOP + sp_valid_arr(ch_idx) <= '0'; + END LOOP; + f_wait_clocked_signal(clk, filt_sp_valid_arr(0), '1'); + + FOR ch_idx IN 0 TO g_CHANNELS-1 + LOOP + read(lin, v_x_or_y); + IF ABS(REAL(to_integer(filt_sp_arr(ch_idx)))/REAL(v_x_or_y) - 1.0) > + 0.01 THEN + REPORT + "TOO LARGE ERROR (> 1%): " + & INTEGER'image(to_integer(filt_sp_arr(ch_idx))) + & " (EXPECTED: " + & INTEGER'image(v_x_or_y) & ")" + SEVERITY ERROR; + END IF; + END LOOP; + END LOOP; + file_close(fin); + + REPORT "SUCCESS!" + SEVERITY NOTE; + + finish; + END PROCESS; + + UUT : xwb_fofb_shaper_filt + GENERIC MAP ( + g_CHANNELS => g_CHANNELS, + g_ARITH_EXTRA_BITS => g_ARITH_EXTRA_BITS, + g_IFCS_EXTRA_BITS => g_IFCS_EXTRA_BITS, + g_INTERFACE_MODE => PIPELINED, + g_ADDRESS_GRANULARITY => BYTE, + g_WITH_EXTRA_WB_REG => FALSE + ) + PORT MAP ( + clk_i => clk, + rst_n_i => rst_n, + sp_arr_i => sp_arr, + sp_valid_arr_i => sp_valid_arr, + filt_sp_arr_o => filt_sp_arr, + filt_sp_valid_arr_o => filt_sp_valid_arr, + wb_slv_i => wb_slave_i, + wb_slv_o => wb_slave_o + ); +END ARCHITECTURE test; From c80c4f0f965158b1fa7a9c96bb25a1f1f97bfa90 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 22 Sep 2023 14:39:05 -0300 Subject: [PATCH 04/26] afc_ref_fofb_ctrl_gen.vhd: instantiate shaper filters --- .../afc_ref_fofb_ctrl_gen.vhd | 43 +++++++++++++++++-- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 4f784d40..cbdf8e43 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -499,6 +499,15 @@ architecture top of afc_ref_fofb_ctrl_gen is signal distort_bpm_pos_flat_y : t_bpm_pos_arr(c_MAX_NUM_BPM_POS_PER_FLAT-1 downto 0); signal distort_bpm_pos_flat_y_rcvd : std_logic_vector(c_MAX_NUM_BPM_POS_PER_FLAT-1 downto 0); + ----------------------------------------------------------------------------- + -- FOFB shaper filters signals + ----------------------------------------------------------------------------- + constant c_FOFB_SHAPER_FILT_ARITH_EXTRA_BITS : natural := 0; + constant c_FOFB_SHAPER_FILT_IFCS_EXTRA_BITS : natural := 4; + + signal filt_distort_fofb_proc_sp_arr : t_sp_arr(c_FOFB_CHANNELS-1 DOWNTO 0); + signal filt_distort_fofb_proc_sp_valid_arr : std_logic_vector(c_FOFB_CHANNELS-1 DOWNTO 0); + ----------------------------------------------------------------------------- -- RTM signals ----------------------------------------------------------------------------- @@ -839,8 +848,9 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_RTM_LAMP_ID : natural := 2; constant c_FOFB_PROCESSING_ID : natural := 3; constant c_FOFB_SYS_ID_ID : natural := 4; - -- +2 for accounting for FOFB processing and FOFB system identification cores - constant c_USER_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES + 2; + constant c_FOFB_SHAPER_FILT_ID : natural := 5; + -- +3 is accounting for FOFB {processing, system identification, shaper filter} cores + constant c_USER_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES + 3; constant c_RTM_LAMP_SDB : boolean := (g_RTM = "RTMLAMP"); constant c_USER_SDB_RECORD_ARRAY : t_sdb_record_array(c_USER_NUM_CORES-1 downto 0) := @@ -849,7 +859,8 @@ architecture top of afc_ref_fofb_ctrl_gen is c_FOFB_CC_P2P_ID => f_sdb_auto_device(c_xwb_fofb_cc_regs_sdb, true), c_RTM_LAMP_ID => f_sdb_auto_device(c_xwb_rtm_lamp_regs_sdb, c_RTM_LAMP_SDB), c_FOFB_PROCESSING_ID => f_sdb_auto_device(c_xwb_fofb_processing_regs_sdb, true), - c_FOFB_SYS_ID_ID => f_sdb_auto_device(c_xwb_fofb_sys_id_regs_sdb, true) + c_FOFB_SYS_ID_ID => f_sdb_auto_device(c_xwb_fofb_sys_id_regs_sdb, true), + c_FOFB_SHAPER_FILT_ID => f_sdb_auto_device(c_xwb_fofb_shaper_filter_regs_sdb, true) ); ----------------------------------------------------------------------------- @@ -1894,6 +1905,30 @@ begin wb_slv_o => user_wb_in(c_FOFB_SYS_ID_ID) ); + ---------------------------------------------------------------------- + -- FOFB SHAPER FILTERS -- + ---------------------------------------------------------------------- + + cmp_xwb_fofb_shaper_filt : xwb_fofb_shaper_filt + generic map ( + g_CHANNELS => c_FOFB_CHANNELS, + g_ARITH_EXTRA_BITS => c_FOFB_SHAPER_FILT_ARITH_EXTRA_BITS, + g_IFCS_EXTRA_BITS => c_FOFB_SHAPER_FILT_IFCS_EXTRA_BITS, + g_INTERFACE_MODE => PIPELINED, + g_ADDRESS_GRANULARITY => BYTE, + g_WITH_EXTRA_WB_REG => false + ) + port map ( + clk_i => clk_sys, + rst_n_i => clk_sys_rstn, + sp_arr_i => distort_fofb_proc_sp_arr, + sp_valid_arr_i => distort_fofb_proc_sp_valid_arr, + filt_sp_arr_o => filt_distort_fofb_proc_sp_arr, + filt_sp_valid_arr_o => filt_distort_fofb_proc_sp_valid_arr, + wb_slv_i => user_wb_out(c_FOFB_SHAPER_FILT_ID), + wb_slv_o => user_wb_in(c_FOFB_SHAPER_FILT_ID) + ); + ---------------------------------------------------------------------- -- RTM 8SFP OHWR -- ---------------------------------------------------------------------- @@ -2198,7 +2233,7 @@ begin -- Convert signed elements to std_logic_vector gen_conv_pi_sp: for i in 0 to c_FOFB_CHANNELS-1 generate - pi_sp_ext(i) <= std_logic_vector(distort_fofb_proc_sp_arr(i)); + pi_sp_ext(i) <= std_logic_vector(filt_distort_fofb_proc_sp_arr(i)); end generate; ---------------------------------------------------------------------- From f73158b2c86861579a371adf8a5ade0a8b43f76e Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 5 May 2023 14:26:06 -0300 Subject: [PATCH 05/26] afc_ref_fofb_ctrl_gen.vhd: add sys id filtered acq channel Uses the same format as the regular sys id channel. Except for the setpoints, which are filtered, probes the same signals as sys id debug (aka sys id applied) channel. --- .../afc_ref_fofb_ctrl_gen.vhd | 38 +++++++++++++++++-- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index cbdf8e43..4df6eabd 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -507,6 +507,7 @@ architecture top of afc_ref_fofb_ctrl_gen is signal filt_distort_fofb_proc_sp_arr : t_sp_arr(c_FOFB_CHANNELS-1 DOWNTO 0); signal filt_distort_fofb_proc_sp_valid_arr : std_logic_vector(c_FOFB_CHANNELS-1 DOWNTO 0); + signal syncd_acq_sys_id_filtered : std_logic := '0'; ----------------------------------------------------------------------------- -- RTM signals @@ -737,9 +738,10 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_ACQ_DCC_ID : natural := 1; constant c_ACQ_SYS_ID_ID : natural := 2; constant c_ACQ_SYS_ID_DEBUG_ID : natural := 3; + constant c_ACQ_SYS_ID_FILT_ID : natural := 4; -- Number of channels per acquisition core - constant c_ACQ_NUM_CHANNELS : natural := 4; + constant c_ACQ_NUM_CHANNELS : natural := 5; -- The way the triggers were conceived, you have a single logical trigger for -- each ACQ channel. Since we don't use all of those channels, we can use the @@ -777,7 +779,8 @@ architecture top of afc_ref_fofb_ctrl_gen is c_ACQ_RTM_LAMP_ID => c_FACQ_PARAMS_RTM_LAMP, c_ACQ_DCC_ID => c_FACQ_PARAMS_DCC, c_ACQ_SYS_ID_ID => c_FACQ_PARAMS_SYS_ID, - c_ACQ_SYS_ID_DEBUG_ID => c_FACQ_PARAMS_SYS_ID + c_ACQ_SYS_ID_DEBUG_ID => c_FACQ_PARAMS_SYS_ID, + c_ACQ_SYS_ID_FILT_ID => c_FACQ_PARAMS_SYS_ID ); signal acq_chan_array : t_facq_chan_array2d(c_ACQ_NUM_CORES-1 downto 0, c_ACQ_NUM_CHANNELS-1 downto 0); @@ -1856,6 +1859,16 @@ begin sync_pulse_o => syncd_acq_sys_id_debug ); + cmp_acq_sys_id_filtered_pulse_syncr : pulse_syncr + port map ( + clk_i => clk_sys, + rst_n_i => clk_sys_rstn, + clr_i => '0', + pulse_i => trig_pulse_rcv(c_TRIG_MUX_SYS_ID_ID, c_ACQ_SYS_ID_FILT_ID).pulse, + sync_i => filt_distort_fofb_proc_sp_valid_arr(0), -- all valids are synced + sync_pulse_o => syncd_acq_sys_id_filtered + ); + cmp_trig_sys_id_eff_regs_pulse_syncr : pulse_syncr port map ( clk_i => clk_sys, @@ -1881,10 +1894,10 @@ begin bpm_pos_i => fofb_proc_bpm_pos, bpm_pos_index_i => fofb_proc_bpm_pos_index, bpm_pos_valid_i => fofb_proc_bpm_pos_valid, - bpm_pos_flat_clear_i => distort_fofb_proc_sp_valid_arr(0), -- all valids are synced + bpm_pos_flat_clear_i => filt_distort_fofb_proc_sp_valid_arr(0), -- all valids are synced sp_arr_i => t_sp_arr(fofb_proc_sp_arr), sp_valid_arr_i => fofb_proc_sp_valid_arr, - prbs_valid_i => distort_fofb_proc_sp_valid_arr(0), -- all valids are synced + prbs_valid_i => filt_distort_fofb_proc_sp_valid_arr(0), -- all valids are synced trig_i => syncd_trig_sys_id_eff_regs, bpm_pos_flat_x_o => bpm_pos_flat_x, bpm_pos_flat_x_rcvd_o => bpm_pos_flat_x_rcvd, @@ -2360,6 +2373,23 @@ begin acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_DEBUG_ID).dvalid <= distort_fofb_proc_sp_valid_arr(0); -- all valids are synced acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_DEBUG_ID).trig <= syncd_acq_sys_id_debug; + -- SYS ID filtered channel + acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_FILT_ID).val(to_integer(c_FACQ_CHANNELS(c_ACQ_SYS_ID_FILT_ID).width)-1 downto 0) <= + std_logic_vector(to_unsigned(0, 287)) & -- Padding with 0s (1023 downto 737) + prbs & -- PRBS (736) + distort_bpm_pos_flat_x_rcvd & distort_bpm_pos_flat_y_rcvd & -- Flatenizers' 'received' flag (735 downto 720, 2x8) + f_fofb_cc_packet_to_slv(acq_dcc_fmc_packet)(def_PacketTimeframeCntr16MSB downto def_PacketTimeframeCntr16LSB) & -- Timeframe counter (719 downto 704, 1x16) + -- NOTE: These 16-bit values are being swapped at each 2 so they end up being allocated on RAM in descending order after ACQ endianness procedures. + std_logic_vector(filt_distort_fofb_proc_sp_arr(10)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(11)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(8)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(9)) & -- FOFB channels distorted and filtered setpoints 11-0 (703 downto 512, 12x16) + std_logic_vector(filt_distort_fofb_proc_sp_arr(6)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(7)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(4)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(5)) & + std_logic_vector(filt_distort_fofb_proc_sp_arr(2)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(3)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(0)) & std_logic_vector(filt_distort_fofb_proc_sp_arr(1)) & + std_logic_vector(distort_bpm_pos_flat_y(7)) & std_logic_vector(distort_bpm_pos_flat_y(6)) & std_logic_vector(distort_bpm_pos_flat_y(5)) & std_logic_vector(distort_bpm_pos_flat_y(4)) & -- P2P BPM y distorted positions 7-0 (511 downto 256, 8x32) + std_logic_vector(distort_bpm_pos_flat_y(3)) & std_logic_vector(distort_bpm_pos_flat_y(2)) & std_logic_vector(distort_bpm_pos_flat_y(1)) & std_logic_vector(distort_bpm_pos_flat_y(0)) & + std_logic_vector(distort_bpm_pos_flat_x(7)) & std_logic_vector(distort_bpm_pos_flat_x(6)) & std_logic_vector(distort_bpm_pos_flat_x(5)) & std_logic_vector(distort_bpm_pos_flat_x(4)) & -- P2P BPM x distorted positions 7-0 (255 downto 0, 8x32) + std_logic_vector(distort_bpm_pos_flat_x(3)) & std_logic_vector(distort_bpm_pos_flat_x(2)) & std_logic_vector(distort_bpm_pos_flat_x(1)) & std_logic_vector(distort_bpm_pos_flat_x(0)); + acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_FILT_ID).dvalid <= filt_distort_fofb_proc_sp_valid_arr(0); -- all valids are synced + acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_FILT_ID).trig <= syncd_acq_sys_id_filtered; + ---------------------------------------------------------------------- -- Trigger -- ---------------------------------------------------------------------- From 3763db362209251a39410a9e706ce09897cdead4 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 11 Dec 2023 14:17:27 -0300 Subject: [PATCH 06/26] xwb_fofb_shaper_filt.vhd: add support for busy flags Internal IIR filters aren't pipelined, so busy flags should be exposed. However, no busy-checking is done in top-level atm. --- hdl/ip_cores/infra-cores | 2 +- hdl/modules/fofb_ctrl_pkg.vhd | 1 + hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 4 ++++ .../xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd | 3 +++ hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd | 1 + 5 files changed, 10 insertions(+), 1 deletion(-) diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index 29c38f10..25f90e66 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit 29c38f10c5faba590e5bbb5f2529daa79f063466 +Subproject commit 25f90e660774795da65e62b7a3e1693520f94de8 diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index 88382e33..ca2edc60 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -654,6 +654,7 @@ package fofb_ctrl_pkg is rst_n_i : in std_logic; sp_arr_i : in t_sp_arr(g_CHANNELS-1 DOWNTO 0); sp_valid_arr_i : in std_logic_vector(g_CHANNELS-1 DOWNTO 0); + busy_arr_o : out std_logic_vector(g_CHANNELS-1 DOWNTO 0); filt_sp_arr_o : out t_sp_arr(g_CHANNELS-1 DOWNTO 0); filt_sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 DOWNTO 0); wb_slv_i : in t_wishbone_slave_in; diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index 1416957b..b3449dc0 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -57,6 +57,9 @@ ENTITY xwb_fofb_shaper_filt IS -- Setpoints valid array sp_valid_arr_i : IN STD_LOGIC_VECTOR(g_CHANNELS-1 DOWNTO 0); + -- Busy flag array + busy_arr_o : OUT STD_LOGIC_VECTOR(g_CHANNELS-1 DOWNTO 0); + -- Filtered setpoints array filt_sp_arr_o : OUT t_sp_arr(g_CHANNELS-1 DOWNTO 0); -- Filtered setpoints valid array @@ -237,6 +240,7 @@ BEGIN x_i => iir_filts_x(idx), x_valid_i => sp_valid_arr_i(idx), coeffs_i => coeffs(idx), + busy_o => busy_arr_o(idx), y_o => iir_filts_y(idx), y_valid_o => filt_sp_valid_arr_o(idx) ); diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index 9ec22342..529e8cc4 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -57,6 +57,7 @@ ARCHITECTURE test OF xwb_fofb_shaper_filt_tb IS SIGNAL clk : STD_LOGIC := '0'; SIGNAL rst_n : STD_LOGIC := '1'; + SIGNAL busy_arr : STD_LOGIC_VECTOR(g_CHANNELS-1 DOWNTO 0); SIGNAL sp_arr, filt_sp_arr : t_sp_arr(g_CHANNELS-1 DOWNTO 0); SIGNAL sp_valid_arr, filt_sp_valid_arr : STD_LOGIC_VECTOR(g_CHANNELS-1 DOWNTO 0) := (OTHERS => '0'); @@ -171,6 +172,7 @@ BEGIN LOOP read(lin, v_x_or_y); sp_arr(ch_idx) <= to_signed(v_x_or_y, sp_arr(ch_idx)'LENGTH); + f_wait_clocked_signal(clk, busy_arr(0), '0'); sp_valid_arr(ch_idx) <= '1'; END LOOP; f_wait_cycles(clk, 1); @@ -217,6 +219,7 @@ BEGIN rst_n_i => rst_n, sp_arr_i => sp_arr, sp_valid_arr_i => sp_valid_arr, + busy_arr_o => busy_arr, filt_sp_arr_o => filt_sp_arr, filt_sp_valid_arr_o => filt_sp_valid_arr, wb_slv_i => wb_slave_i, diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 4df6eabd..2c5d68fe 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -1936,6 +1936,7 @@ begin rst_n_i => clk_sys_rstn, sp_arr_i => distort_fofb_proc_sp_arr, sp_valid_arr_i => distort_fofb_proc_sp_valid_arr, + busy_arr_o => open, filt_sp_arr_o => filt_distort_fofb_proc_sp_arr, filt_sp_valid_arr_o => filt_distort_fofb_proc_sp_valid_arr, wb_slv_i => user_wb_out(c_FOFB_SHAPER_FILT_ID), From 106009439e9f999053ae59aa3e1ac15246a24d62 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 2 Oct 2023 14:16:56 -0300 Subject: [PATCH 07/26] afc_ref_fofb_ctrl_gen.vhd: remove DCC acq cores These cores were used in for debugging DCC/FOFB commissioning. However, DCC is pretty stable by now and we don't plan to develop new features for it. The new logical trigger assignment is +-------------------------------------------------------+ | CHANNEL INDEX | FUNCTION | CORE | +-------------------------------------------------------+ | 0 | ACQ RTM LAMP | RTM LAMP | | 1 | ACQ SYS ID | SYS ID | | 2 | ACQ SYS ID DEBUG | SYS ID | | 3 | ACQ SYS ID FILT | SYS ID | | 4 | EFF RTM LAMP SP | RTM LAMP | | 5 | EFF SYS ID REGS | SYS ID | +-------------------------------------------------------+ --- .../afc_ref_fofb_ctrl_gen.vhd | 74 ++----------------- 1 file changed, 6 insertions(+), 68 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 2c5d68fe..166b3ddb 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -716,13 +716,11 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_ACQ_FIFO_SIZE : natural := 256; -- Number of acquisition cores - constant c_ACQ_NUM_CORES : natural := c_NUM_FOFC_CC_CORES + c_RTM_LAMP_NUM_CORES + c_NUM_SYS_ID_CORES; + constant c_ACQ_NUM_CORES : natural := c_RTM_LAMP_NUM_CORES + c_NUM_SYS_ID_CORES; -- Acquisition core IDs constant c_ACQ_CORE_RTM_LAMP_ID : natural := 0; - constant c_ACQ_CORE_CC_FMC_OR_RTM_ID : natural := 1; - constant c_ACQ_CORE_CC_P2P_ID : natural := 2; - constant c_ACQ_CORE_SYS_ID_ID : natural := 3; + constant c_ACQ_CORE_SYS_ID_ID : natural := 1; -- Type of DDR3 core interface constant c_DDR_INTERFACE_TYPE : string := "AXIS"; @@ -735,13 +733,12 @@ architecture top of afc_ref_fofb_ctrl_gen is -- Acquisition channels IDs constant c_ACQ_RTM_LAMP_ID : natural := 0; - constant c_ACQ_DCC_ID : natural := 1; - constant c_ACQ_SYS_ID_ID : natural := 2; - constant c_ACQ_SYS_ID_DEBUG_ID : natural := 3; - constant c_ACQ_SYS_ID_FILT_ID : natural := 4; + constant c_ACQ_SYS_ID_ID : natural := 1; + constant c_ACQ_SYS_ID_DEBUG_ID : natural := 2; + constant c_ACQ_SYS_ID_FILT_ID : natural := 3; -- Number of channels per acquisition core - constant c_ACQ_NUM_CHANNELS : natural := 5; + constant c_ACQ_NUM_CHANNELS : natural := 4; -- The way the triggers were conceived, you have a single logical trigger for -- each ACQ channel. Since we don't use all of those channels, we can use the @@ -777,7 +774,6 @@ architecture top of afc_ref_fofb_ctrl_gen is constant c_FACQ_CHANNELS : t_facq_chan_param_array(c_ACQ_NUM_CHANNELS-1 downto 0) := ( c_ACQ_RTM_LAMP_ID => c_FACQ_PARAMS_RTM_LAMP, - c_ACQ_DCC_ID => c_FACQ_PARAMS_DCC, c_ACQ_SYS_ID_ID => c_FACQ_PARAMS_SYS_ID, c_ACQ_SYS_ID_DEBUG_ID => c_FACQ_PARAMS_SYS_ID, c_ACQ_SYS_ID_FILT_ID => c_FACQ_PARAMS_SYS_ID @@ -808,8 +804,6 @@ architecture top of afc_ref_fofb_ctrl_gen is -- Trigger core IDs -- These IDs should be kept in sync with the ACQ core IDs constant c_TRIG_MUX_RTM_LAMP_ID : natural := c_ACQ_CORE_RTM_LAMP_ID; - constant c_TRIG_MUX_CC_FMC_ID : natural := c_ACQ_CORE_CC_FMC_OR_RTM_ID; - constant c_TRIG_MUX_CC_P2P_ID : natural := c_ACQ_CORE_CC_P2P_ID; constant c_TRIG_MUX_SYS_ID_ID : natural := c_ACQ_CORE_SYS_ID_ID; constant c_TRIG_MUX_NUM_CORES : natural := c_ACQ_NUM_CORES; @@ -1537,10 +1531,6 @@ begin end generate; - -- Trigger signal for DCC timeframe_start. - -- Trigger pulses are synch'ed with the respective fs_clk - fai_sim_trigger(c_FOFB_CC_FMC_OR_RTM_ID) <= trig_pulse_rcv(c_TRIG_MUX_CC_FMC_ID, c_TRIG_MUX_FOFB_SYNC_ID).pulse; - cmp_fofb_ctrl_wrapper_0 : xwb_fofb_ctrl_wrapper generic map ( @@ -1699,10 +1689,6 @@ begin fofb_ref_clk_p(c_FOFB_CC_P2P_ID) <= clk_fp2_clk1_p; fofb_ref_clk_n(c_FOFB_CC_P2P_ID) <= clk_fp2_clk1_n; - -- Trigger signal for DCC timeframe_start. - -- Trigger pulses are synch'ed with the respective fs_clk - fai_sim_trigger(c_FOFB_CC_P2P_ID) <= trig_pulse_rcv(c_TRIG_MUX_CC_P2P_ID, c_TRIG_MUX_FOFB_SYNC_ID).pulse; - cmp_fofb_ctrl_wrapper_1 : xwb_fofb_ctrl_wrapper generic map ( @@ -2254,12 +2240,6 @@ begin -- Acquisition -- ---------------------------------------------------------------------- - fs_clk_array(c_ACQ_CORE_CC_FMC_OR_RTM_ID) <= clk_sys; - fs_rst_n_array(c_ACQ_CORE_CC_FMC_OR_RTM_ID) <= clk_sys_rstn; - - fs_clk_array(c_ACQ_CORE_CC_P2P_ID) <= fofb_userclk(c_FOFB_CC_P2P_ID); - fs_rst_n_array(c_ACQ_CORE_CC_P2P_ID) <= fofb_userrst_n(c_FOFB_CC_P2P_ID); - fs_clk_array(c_ACQ_CORE_RTM_LAMP_ID) <= clk_sys; fs_rst_n_array(c_ACQ_CORE_RTM_LAMP_ID) <= clk_sys_rstn; @@ -2320,26 +2300,6 @@ begin -- ACQ Core 1 -------------------- - -- DCC FMC - acq_chan_array(c_ACQ_CORE_CC_FMC_OR_RTM_ID, c_ACQ_DCC_ID).val(to_integer(c_FACQ_CHANNELS(c_ACQ_DCC_ID).width)-1 downto 0) <= - std_logic_vector(fofb_proc_sp_arr(6)) & std_logic_vector(fofb_proc_sp_arr(7)) & std_logic_vector(fofb_proc_sp_arr(4)) & std_logic_vector(fofb_proc_sp_arr(5)) & - std_logic_vector(fofb_proc_sp_arr(2)) & std_logic_vector(fofb_proc_sp_arr(3)) & std_logic_vector(fofb_proc_sp_arr(0)) & std_logic_vector(fofb_proc_sp_arr(1)) & f_fofb_cc_packet_to_slv(acq_dcc_fmc_packet); - acq_chan_array(c_ACQ_CORE_CC_FMC_OR_RTM_ID, c_ACQ_DCC_ID).dvalid <= acq_dcc_fmc_valid; - acq_chan_array(c_ACQ_CORE_CC_FMC_OR_RTM_ID, c_ACQ_DCC_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_CC_FMC_ID, c_ACQ_DCC_ID).pulse; -- TODO: is this on the right clock domain? - - -------------------- - -- ACQ Core 2 - -------------------- - -- DCC P2P - acq_chan_array(c_ACQ_CORE_CC_P2P_ID, c_ACQ_DCC_ID).val(to_integer(c_FACQ_CHANNELS(c_ACQ_DCC_ID).width)-1 downto 0) <= - std_logic_vector(to_unsigned(0, 128)) & fofb_fod_dat(c_FOFB_CC_P2P_ID); - acq_chan_array(c_ACQ_CORE_CC_P2P_ID, c_ACQ_DCC_ID).dvalid <= fofb_fod_dat_val(c_FOFB_CC_P2P_ID)(0); - acq_chan_array(c_ACQ_CORE_CC_P2P_ID, c_ACQ_DCC_ID).trig <= trig_pulse_rcv(c_TRIG_MUX_CC_P2P_ID, c_ACQ_DCC_ID).pulse; - - -------------------- - -- ACQ Core 3 - -------------------- - -- SYS ID channel acq_chan_array(c_ACQ_CORE_SYS_ID_ID, c_ACQ_SYS_ID_ID).val(to_integer(c_FACQ_CHANNELS(c_ACQ_SYS_ID_ID).width)-1 downto 0) <= std_logic_vector(to_unsigned(0, 287)) & -- [DEBUG] Padding with 0s (1023 downto 737) @@ -2398,34 +2358,12 @@ begin trig_ref_clk <= clk_trig_ref; trig_ref_rst_n <= clk_trig_ref_rstn; - -- Assign trigger pulses to trigger channel interfaces - trig_acq_channel(c_TRIG_MUX_CC_FMC_ID, c_TRIG_RCV_INTERN_CHAN_0_ID).pulse <= - timeframe_start(c_FOFB_CC_FMC_OR_RTM_ID); - trig_acq_channel(c_TRIG_MUX_CC_FMC_ID, c_TRIG_RCV_INTERN_CHAN_1_ID).pulse <= - timeframe_end(c_FOFB_CC_FMC_OR_RTM_ID); - - trig_acq_channel(c_TRIG_MUX_CC_P2P_ID, c_TRIG_RCV_INTERN_CHAN_0_ID).pulse <= - timeframe_start(c_FOFB_CC_P2P_ID); - trig_acq_channel(c_TRIG_MUX_CC_P2P_ID, c_TRIG_RCV_INTERN_CHAN_1_ID).pulse <= - timeframe_end(c_FOFB_CC_P2P_ID); - -- FIXME: remove it -- trig_acq_channel(c_TRIG_MUX_RTM_LAMP_ID, c_TRIG_RCV_INTERN_CHAN_0_ID).pulse <= -- rtmlamp_adc_start; -- trig_acq_channel(c_TRIG_MUX_RTM_LAMP_ID, c_TRIG_RCV_INTERN_CHAN_1_ID).pulse <= -- rtmlamp_dac_start; - -- Assign intern triggers to trigger module - trig_rcv_intern(c_TRIG_MUX_CC_FMC_ID, c_TRIG_RCV_INTERN_CHAN_0_ID) <= - trig_acq_channel(c_TRIG_MUX_CC_FMC_ID, c_TRIG_RCV_INTERN_CHAN_0_ID); - trig_rcv_intern(c_TRIG_MUX_CC_FMC_ID, c_TRIG_RCV_INTERN_CHAN_1_ID) <= - trig_acq_channel(c_TRIG_MUX_CC_FMC_ID, c_TRIG_RCV_INTERN_CHAN_1_ID); - - trig_rcv_intern(c_TRIG_MUX_CC_P2P_ID, c_TRIG_RCV_INTERN_CHAN_0_ID) <= - trig_acq_channel(c_TRIG_MUX_CC_P2P_ID, c_TRIG_RCV_INTERN_CHAN_0_ID); - trig_rcv_intern(c_TRIG_MUX_CC_P2P_ID, c_TRIG_RCV_INTERN_CHAN_1_ID) <= - trig_acq_channel(c_TRIG_MUX_CC_P2P_ID, c_TRIG_RCV_INTERN_CHAN_1_ID); - trig_rcv_intern(c_TRIG_MUX_RTM_LAMP_ID, c_TRIG_RCV_INTERN_CHAN_0_ID) <= trig_acq_channel(c_TRIG_MUX_RTM_LAMP_ID, c_TRIG_RCV_INTERN_CHAN_0_ID); trig_rcv_intern(c_TRIG_MUX_RTM_LAMP_ID, c_TRIG_RCV_INTERN_CHAN_1_ID) <= From 300f6509271628f0af6a9b94f1c377ef15791bd4 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 28 Mar 2024 10:50:42 -0300 Subject: [PATCH 08/26] infra-cores: update submodule Optimizations for easing timing closure. --- hdl/ip_cores/infra-cores | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index 25f90e66..a11f5cbb 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit 25f90e660774795da65e62b7a3e1693520f94de8 +Subproject commit a11f5cbb7848939f7dd67cbee0601728450cd1d9 From b6cec8ed1e9da30985552ae44d30781baba3204a Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Tue, 9 Apr 2024 10:49:34 -0300 Subject: [PATCH 09/26] cheby: don't instantiate RAM for coeffs Instead of instantiating a "shadow" RAM for holding the coefficients, simply access'em through a RAM interface. This optmizes resource usage and might ease timing closure. NOTE: The ABI wasn't broken. The only thing that's changed is the removal of the control register (no need to effectivate the coefficients anymore). --- hdl/modules/fofb_ctrl_pkg.vhd | 4 +- .../cheby/doc/wb_fofb_shaper_filt_regs.html | 107 -- .../cheby/wb_fofb_shaper_filt_regs.cheby | 25 +- .../cheby/wb_fofb_shaper_filt_regs.h | 19 +- .../cheby/wb_fofb_shaper_filt_regs.vhd | 1224 +++++++---------- .../fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 309 ++--- .../wb_fofb_shaper_filt_regs_consts_pkg.vhd | 6 +- .../xwb_fofb_shaper_filt_tb.vhd | 32 +- 8 files changed, 657 insertions(+), 1069 deletions(-) diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index ca2edc60..45127647 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -774,7 +774,7 @@ package fofb_ctrl_pkg is constant c_xwb_fofb_shaper_filter_regs_sdb : t_sdb_device := ( abi_class => x"0000", -- undocumented device abi_ver_major => x"00", - abi_ver_minor => x"01", + abi_ver_minor => x"02", wbd_endian => c_sdb_endian_big, wbd_width => x"4", -- 32-bit port granularity (0100) sdb_component => ( @@ -784,7 +784,7 @@ package fofb_ctrl_pkg is vendor_id => x"1000000000001215", -- LNLS device_id => x"f65559b2", -- Last 8 chars of "FOFB_SHAPER_REGS" md5sum version => x"00000001", - date => x"20230922", + date => x"20240411", name => "FOFB_SHAPER_REGS "))); end fofb_ctrl_pkg; diff --git a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html index 850fb4d2..ad18e508 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html +++ b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html @@ -325,13 +325,6 @@

1. Memory map summary

coeffs_fp_repr coeffs_fp_repr - -0x1008 -REG -ctl -ctl -ctl -

2. Register description

@@ -1366,106 +1359,6 @@

2.14. coeffs_fp_repr

[ro]: Fractionary width. - -

2.15. ctl

- - - - - -
HW prefix:ctl
HW address:0x1008
C prefix:ctl
C block offset:0x1008
-

-Control register.
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3130292827262524
--------
2322212019181716
--------
15141312111098
--------
76543210
-------eff_coeffs
-
    -
  • -eff_coeffs -[rw]: Strobe for effectivating (i.e. updating) coefficients. - -
    write 0: no effect
    write 1: effectivates coefficients (this bit autoclears) -
diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby index 440ad34b..b584cd1c 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby @@ -3,8 +3,7 @@ memory-map: name: wb_fofb_shaper_filt_regs description: Interface to FOFB IIR shaper filters regs x-hdl: - busgroup: True - iogroup: wb_fofb_shaper_filt_regs_ifc + busgroup: true children: - repeat: name: ch @@ -13,6 +12,7 @@ memory-map: - memory: name: coeffs memsize: 200 + interface: sram description: | Coefficients for the ceil('max_filt_order'/2) IIR internal biquads. @@ -26,10 +26,6 @@ memory-map: coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} - This array acts like a 'shadow' for the real coefficients and is - only effectivated when '1' is written to 'eff_coeffs' bit of - 'ctl' register. - NOTE: This ABI supports up to 20th order filters, but only the coefficients corresponding to the first 'max_filt_order' filters are meaningful for the gateware. @@ -68,20 +64,3 @@ memory-map: range: 9-5 description: | Fractionary width. - - reg: - name: ctl - width: 32 - access: rw - description: | - Control register. - children: - - field: - name: eff_coeffs - x-hdl: - type: autoclear - range: 0 - description: | - Strobe for effectivating (i.e. updating) coefficients. - comment: | - write 0: no effect - write 1: effectivates coefficients (this bit autoclears) diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h index a9c0e267..6984809c 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h @@ -1,6 +1,6 @@ #ifndef __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__ #define __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__ -#define WB_FOFB_SHAPER_FILT_REGS_SIZE 4108 /* 0x100c */ +#define WB_FOFB_SHAPER_FILT_REGS_SIZE 4104 /* 0x1008 */ /* None */ #define WB_FOFB_SHAPER_FILT_REGS_CH 0x0UL @@ -18,10 +18,6 @@ The 'coeffs' array should be populated in the following manner: coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} -This array acts like a 'shadow' for the real coefficients and is -only effectivated when '1' is written to 'eff_coeffs' bit of -'ctl' register. - NOTE: This ABI supports up to 20th order filters, but only the coefficients corresponding to the first 'max_filt_order' filters are meaningful for the gateware. @@ -50,11 +46,6 @@ represented decimal number. #define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_MASK 0x3e0UL #define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_SHIFT 5 -/* Control register. - */ -#define WB_FOFB_SHAPER_FILT_REGS_CTL 0x1008UL -#define WB_FOFB_SHAPER_FILT_REGS_CTL_EFF_COEFFS 0x1UL - #ifndef __ASSEMBLER__ struct wb_fofb_shaper_filt_regs { /* [0x0]: REPEAT (no description) */ @@ -71,10 +62,6 @@ The 'coeffs' array should be populated in the following manner: coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} -This array acts like a 'shadow' for the real coefficients and is -only effectivated when '1' is written to 'eff_coeffs' bit of -'ctl' register. - NOTE: This ABI supports up to 20th order filters, but only the coefficients corresponding to the first 'max_filt_order' filters are meaningful for the gateware. @@ -104,10 +91,6 @@ this register's content by 2**{32 - 'int_width'} to get the represented decimal number. */ uint32_t coeffs_fp_repr; - - /* [0x1008]: REG (rw) Control register. - */ - uint32_t ctl; }; #endif /* !__ASSEMBLER__*/ diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd index 8aff157e..621218aa 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd @@ -1,71 +1,12 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Fri Sep 22 15:10:27 2023 by guilherme.ricioli +-- Generated on Tue Apr 09 10:23:32 2024 by guilherme.ricioli library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.wishbone_pkg.all; -use work.cheby_pkg.all; - -package wb_fofb_shaper_filt_regs_pkg is - type t_wb_fofb_shaper_filt_regs_ifc_master_out is record - ch_0_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_1_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_2_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_3_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_4_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_5_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_6_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_7_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_8_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_9_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_10_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ch_11_coeffs_val_dat_o : std_logic_vector(31 downto 0); - ctl_eff_coeffs : std_logic; - end record t_wb_fofb_shaper_filt_regs_ifc_master_out; - subtype t_wb_fofb_shaper_filt_regs_ifc_slave_in is t_wb_fofb_shaper_filt_regs_ifc_master_out; - - type t_wb_fofb_shaper_filt_regs_ifc_slave_out is record - ch_0_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_0_coeffs_val_rd_i : std_logic; - ch_1_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_1_coeffs_val_rd_i : std_logic; - ch_2_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_2_coeffs_val_rd_i : std_logic; - ch_3_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_3_coeffs_val_rd_i : std_logic; - ch_4_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_4_coeffs_val_rd_i : std_logic; - ch_5_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_5_coeffs_val_rd_i : std_logic; - ch_6_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_6_coeffs_val_rd_i : std_logic; - ch_7_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_7_coeffs_val_rd_i : std_logic; - ch_8_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_8_coeffs_val_rd_i : std_logic; - ch_9_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_9_coeffs_val_rd_i : std_logic; - ch_10_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_10_coeffs_val_rd_i : std_logic; - ch_11_coeffs_adr_i : std_logic_vector(5 downto 0); - ch_11_coeffs_val_rd_i : std_logic; - max_filt_order : std_logic_vector(31 downto 0); - coeffs_fp_repr_int_width : std_logic_vector(4 downto 0); - coeffs_fp_repr_frac_width : std_logic_vector(4 downto 0); - end record t_wb_fofb_shaper_filt_regs_ifc_slave_out; - subtype t_wb_fofb_shaper_filt_regs_ifc_master_in is t_wb_fofb_shaper_filt_regs_ifc_slave_out; - -end wb_fofb_shaper_filt_regs_pkg; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use work.wishbone_pkg.all; -use work.cheby_pkg.all; -use work.wb_fofb_shaper_filt_regs_pkg.all; entity wb_fofb_shaper_filt_regs is port ( @@ -73,9 +14,95 @@ entity wb_fofb_shaper_filt_regs is clk_i : in std_logic; wb_i : in t_wishbone_slave_in; wb_o : out t_wishbone_slave_out; - -- Wires and registers - wb_fofb_shaper_filt_regs_ifc_i : in t_wb_fofb_shaper_filt_regs_ifc_master_in; - wb_fofb_shaper_filt_regs_ifc_o : out t_wb_fofb_shaper_filt_regs_ifc_master_out + + -- SRAM bus ch_0_coeffs + ch_0_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_0_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_0_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_0_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_1_coeffs + ch_1_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_1_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_1_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_1_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_2_coeffs + ch_2_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_2_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_2_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_2_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_3_coeffs + ch_3_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_3_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_3_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_3_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_4_coeffs + ch_4_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_4_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_4_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_4_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_5_coeffs + ch_5_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_5_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_5_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_5_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_6_coeffs + ch_6_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_6_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_6_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_6_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_7_coeffs + ch_7_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_7_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_7_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_7_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_8_coeffs + ch_8_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_8_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_8_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_8_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_9_coeffs + ch_9_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_9_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_9_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_9_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_10_coeffs + ch_10_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_10_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_10_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_10_coeffs_wr_o : out std_logic; + + -- SRAM bus ch_11_coeffs + ch_11_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_11_coeffs_data_i : in std_logic_vector(31 downto 0); + ch_11_coeffs_data_o : out std_logic_vector(31 downto 0); + ch_11_coeffs_wr_o : out std_logic; + + -- Maximum filter order supported by the gateware. + + max_filt_order_i : in std_logic_vector(31 downto 0); + + -- Fixed-point signed representation of coefficients. + -- The coefficients should be aligned to the left. The fixed-point + -- position is then given by 32 - 'int_width' (i.e. one should divide + -- this register's content by 2**{32 - 'int_width'} to get the + -- represented decimal number. + + -- Integer width (accounting for the signal bit). + + coeffs_fp_repr_int_width_i : in std_logic_vector(4 downto 0); + -- Fractionary width. + + coeffs_fp_repr_frac_width_i : in std_logic_vector(4 downto 0) ); end wb_fofb_shaper_filt_regs; @@ -89,111 +116,59 @@ architecture syn of wb_fofb_shaper_filt_regs is signal ack_int : std_logic; signal wb_rip : std_logic; signal wb_wip : std_logic; - signal ch_0_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_0_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_0_coeffs_val_rreq : std_logic; - signal ch_0_coeffs_val_rack : std_logic; - signal ch_0_coeffs_val_int_wr : std_logic; - signal ch_1_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_1_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_1_coeffs_val_rreq : std_logic; - signal ch_1_coeffs_val_rack : std_logic; - signal ch_1_coeffs_val_int_wr : std_logic; - signal ch_2_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_2_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_2_coeffs_val_rreq : std_logic; - signal ch_2_coeffs_val_rack : std_logic; - signal ch_2_coeffs_val_int_wr : std_logic; - signal ch_3_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_3_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_3_coeffs_val_rreq : std_logic; - signal ch_3_coeffs_val_rack : std_logic; - signal ch_3_coeffs_val_int_wr : std_logic; - signal ch_4_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_4_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_4_coeffs_val_rreq : std_logic; - signal ch_4_coeffs_val_rack : std_logic; - signal ch_4_coeffs_val_int_wr : std_logic; - signal ch_5_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_5_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_5_coeffs_val_rreq : std_logic; - signal ch_5_coeffs_val_rack : std_logic; - signal ch_5_coeffs_val_int_wr : std_logic; - signal ch_6_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_6_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_6_coeffs_val_rreq : std_logic; - signal ch_6_coeffs_val_rack : std_logic; - signal ch_6_coeffs_val_int_wr : std_logic; - signal ch_7_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_7_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_7_coeffs_val_rreq : std_logic; - signal ch_7_coeffs_val_rack : std_logic; - signal ch_7_coeffs_val_int_wr : std_logic; - signal ch_8_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_8_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_8_coeffs_val_rreq : std_logic; - signal ch_8_coeffs_val_rack : std_logic; - signal ch_8_coeffs_val_int_wr : std_logic; - signal ch_9_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_9_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_9_coeffs_val_rreq : std_logic; - signal ch_9_coeffs_val_rack : std_logic; - signal ch_9_coeffs_val_int_wr : std_logic; - signal ch_10_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_10_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_10_coeffs_val_rreq : std_logic; - signal ch_10_coeffs_val_rack : std_logic; - signal ch_10_coeffs_val_int_wr : std_logic; - signal ch_11_coeffs_val_int_dato : std_logic_vector(31 downto 0); - signal ch_11_coeffs_val_ext_dat : std_logic_vector(31 downto 0); - signal ch_11_coeffs_val_rreq : std_logic; - signal ch_11_coeffs_val_rack : std_logic; - signal ch_11_coeffs_val_int_wr : std_logic; - signal ctl_eff_coeffs_reg : std_logic; - signal ctl_wreq : std_logic; - signal ctl_wack : std_logic; + signal ch_0_coeffs_rack : std_logic; + signal ch_0_coeffs_re : std_logic; + signal ch_1_coeffs_rack : std_logic; + signal ch_1_coeffs_re : std_logic; + signal ch_2_coeffs_rack : std_logic; + signal ch_2_coeffs_re : std_logic; + signal ch_3_coeffs_rack : std_logic; + signal ch_3_coeffs_re : std_logic; + signal ch_4_coeffs_rack : std_logic; + signal ch_4_coeffs_re : std_logic; + signal ch_5_coeffs_rack : std_logic; + signal ch_5_coeffs_re : std_logic; + signal ch_6_coeffs_rack : std_logic; + signal ch_6_coeffs_re : std_logic; + signal ch_7_coeffs_rack : std_logic; + signal ch_7_coeffs_re : std_logic; + signal ch_8_coeffs_rack : std_logic; + signal ch_8_coeffs_re : std_logic; + signal ch_9_coeffs_rack : std_logic; + signal ch_9_coeffs_re : std_logic; + signal ch_10_coeffs_rack : std_logic; + signal ch_10_coeffs_re : std_logic; + signal ch_11_coeffs_rack : std_logic; + signal ch_11_coeffs_re : std_logic; signal rd_ack_d0 : std_logic; signal rd_dat_d0 : std_logic_vector(31 downto 0); signal wr_req_d0 : std_logic; signal wr_adr_d0 : std_logic_vector(12 downto 2); signal wr_dat_d0 : std_logic_vector(31 downto 0); - signal wr_sel_d0 : std_logic_vector(3 downto 0); - signal ch_0_coeffs_wr : std_logic; - signal ch_0_coeffs_wreq : std_logic; - signal ch_0_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_1_coeffs_wr : std_logic; - signal ch_1_coeffs_wreq : std_logic; - signal ch_1_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_2_coeffs_wr : std_logic; - signal ch_2_coeffs_wreq : std_logic; - signal ch_2_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_3_coeffs_wr : std_logic; - signal ch_3_coeffs_wreq : std_logic; - signal ch_3_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_4_coeffs_wr : std_logic; - signal ch_4_coeffs_wreq : std_logic; - signal ch_4_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_5_coeffs_wr : std_logic; - signal ch_5_coeffs_wreq : std_logic; - signal ch_5_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_6_coeffs_wr : std_logic; - signal ch_6_coeffs_wreq : std_logic; - signal ch_6_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_7_coeffs_wr : std_logic; - signal ch_7_coeffs_wreq : std_logic; - signal ch_7_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_8_coeffs_wr : std_logic; - signal ch_8_coeffs_wreq : std_logic; - signal ch_8_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_9_coeffs_wr : std_logic; - signal ch_9_coeffs_wreq : std_logic; - signal ch_9_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_10_coeffs_wr : std_logic; - signal ch_10_coeffs_wreq : std_logic; - signal ch_10_coeffs_adr_int : std_logic_vector(5 downto 0); - signal ch_11_coeffs_wr : std_logic; - signal ch_11_coeffs_wreq : std_logic; - signal ch_11_coeffs_adr_int : std_logic_vector(5 downto 0); + signal ch_0_coeffs_wp : std_logic; + signal ch_0_coeffs_we : std_logic; + signal ch_1_coeffs_wp : std_logic; + signal ch_1_coeffs_we : std_logic; + signal ch_2_coeffs_wp : std_logic; + signal ch_2_coeffs_we : std_logic; + signal ch_3_coeffs_wp : std_logic; + signal ch_3_coeffs_we : std_logic; + signal ch_4_coeffs_wp : std_logic; + signal ch_4_coeffs_we : std_logic; + signal ch_5_coeffs_wp : std_logic; + signal ch_5_coeffs_we : std_logic; + signal ch_6_coeffs_wp : std_logic; + signal ch_6_coeffs_we : std_logic; + signal ch_7_coeffs_wp : std_logic; + signal ch_7_coeffs_we : std_logic; + signal ch_8_coeffs_wp : std_logic; + signal ch_8_coeffs_we : std_logic; + signal ch_9_coeffs_wp : std_logic; + signal ch_9_coeffs_we : std_logic; + signal ch_10_coeffs_wp : std_logic; + signal ch_10_coeffs_we : std_logic; + signal ch_11_coeffs_wp : std_logic; + signal ch_11_coeffs_we : std_logic; begin -- WB decode signals @@ -240,637 +215,428 @@ begin wr_req_d0 <= wr_req_int; wr_adr_d0 <= adr_int; wr_dat_d0 <= wb_i.dat; - wr_sel_d0 <= wb_i.sel; end if; end if; end process; - -- Memory ch_0_coeffs - process (adr_int, wr_adr_d0, ch_0_coeffs_wr) begin - if ch_0_coeffs_wr = '1' then - ch_0_coeffs_adr_int <= wr_adr_d0(7 downto 2); - else - ch_0_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_0_coeffs_wreq <= ch_0_coeffs_val_int_wr; - ch_0_coeffs_wr <= ch_0_coeffs_wreq; - ch_0_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_0_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_0_coeffs_val_int_dato, - rd_a_i => ch_0_coeffs_val_rreq, - wr_a_i => ch_0_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_0_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_0_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_0_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_0_coeffs_val_rd_i, - wr_b_i => '0' - ); - + -- Interface ch_0_coeffs process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_0_coeffs_val_rack <= '0'; + ch_0_coeffs_rack <= '0'; else - ch_0_coeffs_val_rack <= ch_0_coeffs_val_rreq; + ch_0_coeffs_rack <= ch_0_coeffs_re and not ch_0_coeffs_rack; end if; end if; end process; - - -- Memory ch_1_coeffs - process (adr_int, wr_adr_d0, ch_1_coeffs_wr) begin - if ch_1_coeffs_wr = '1' then - ch_1_coeffs_adr_int <= wr_adr_d0(7 downto 2); - else - ch_1_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_1_coeffs_wreq <= ch_1_coeffs_val_int_wr; - ch_1_coeffs_wr <= ch_1_coeffs_wreq; - ch_1_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_1_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_1_coeffs_val_int_dato, - rd_a_i => ch_1_coeffs_val_rreq, - wr_a_i => ch_1_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_1_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_1_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_1_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_1_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_0_coeffs_data_o <= wr_dat_d0; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_1_coeffs_val_rack <= '0'; + ch_0_coeffs_wp <= '0'; else - ch_1_coeffs_val_rack <= ch_1_coeffs_val_rreq; + ch_0_coeffs_wp <= (wr_req_d0 or ch_0_coeffs_wp) and rd_req_int; end if; end if; end process; - - -- Memory ch_2_coeffs - process (adr_int, wr_adr_d0, ch_2_coeffs_wr) begin - if ch_2_coeffs_wr = '1' then - ch_2_coeffs_adr_int <= wr_adr_d0(7 downto 2); + ch_0_coeffs_we <= (wr_req_d0 or ch_0_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_0_coeffs_re) begin + if ch_0_coeffs_re = '1' then + ch_0_coeffs_addr_o <= adr_int(7 downto 2); else - ch_2_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_2_coeffs_wreq <= ch_2_coeffs_val_int_wr; - ch_2_coeffs_wr <= ch_2_coeffs_wreq; - ch_2_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_2_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_2_coeffs_val_int_dato, - rd_a_i => ch_2_coeffs_val_rreq, - wr_a_i => ch_2_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_2_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_2_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_2_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_2_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_0_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; + + -- Interface ch_1_coeffs process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_2_coeffs_val_rack <= '0'; + ch_1_coeffs_rack <= '0'; else - ch_2_coeffs_val_rack <= ch_2_coeffs_val_rreq; + ch_1_coeffs_rack <= ch_1_coeffs_re and not ch_1_coeffs_rack; end if; end if; end process; - - -- Memory ch_3_coeffs - process (adr_int, wr_adr_d0, ch_3_coeffs_wr) begin - if ch_3_coeffs_wr = '1' then - ch_3_coeffs_adr_int <= wr_adr_d0(7 downto 2); - else - ch_3_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_3_coeffs_wreq <= ch_3_coeffs_val_int_wr; - ch_3_coeffs_wr <= ch_3_coeffs_wreq; - ch_3_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_3_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_3_coeffs_val_int_dato, - rd_a_i => ch_3_coeffs_val_rreq, - wr_a_i => ch_3_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_3_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_3_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_3_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_3_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_1_coeffs_data_o <= wr_dat_d0; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_3_coeffs_val_rack <= '0'; + ch_1_coeffs_wp <= '0'; else - ch_3_coeffs_val_rack <= ch_3_coeffs_val_rreq; + ch_1_coeffs_wp <= (wr_req_d0 or ch_1_coeffs_wp) and rd_req_int; end if; end if; end process; - - -- Memory ch_4_coeffs - process (adr_int, wr_adr_d0, ch_4_coeffs_wr) begin - if ch_4_coeffs_wr = '1' then - ch_4_coeffs_adr_int <= wr_adr_d0(7 downto 2); + ch_1_coeffs_we <= (wr_req_d0 or ch_1_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_1_coeffs_re) begin + if ch_1_coeffs_re = '1' then + ch_1_coeffs_addr_o <= adr_int(7 downto 2); else - ch_4_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_4_coeffs_wreq <= ch_4_coeffs_val_int_wr; - ch_4_coeffs_wr <= ch_4_coeffs_wreq; - ch_4_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_4_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_4_coeffs_val_int_dato, - rd_a_i => ch_4_coeffs_val_rreq, - wr_a_i => ch_4_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_4_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_4_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_4_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_4_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_1_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; + + -- Interface ch_2_coeffs process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_4_coeffs_val_rack <= '0'; + ch_2_coeffs_rack <= '0'; else - ch_4_coeffs_val_rack <= ch_4_coeffs_val_rreq; + ch_2_coeffs_rack <= ch_2_coeffs_re and not ch_2_coeffs_rack; end if; end if; end process; - - -- Memory ch_5_coeffs - process (adr_int, wr_adr_d0, ch_5_coeffs_wr) begin - if ch_5_coeffs_wr = '1' then - ch_5_coeffs_adr_int <= wr_adr_d0(7 downto 2); - else - ch_5_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_5_coeffs_wreq <= ch_5_coeffs_val_int_wr; - ch_5_coeffs_wr <= ch_5_coeffs_wreq; - ch_5_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_5_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_5_coeffs_val_int_dato, - rd_a_i => ch_5_coeffs_val_rreq, - wr_a_i => ch_5_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_5_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_5_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_5_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_5_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_2_coeffs_data_o <= wr_dat_d0; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_5_coeffs_val_rack <= '0'; + ch_2_coeffs_wp <= '0'; else - ch_5_coeffs_val_rack <= ch_5_coeffs_val_rreq; + ch_2_coeffs_wp <= (wr_req_d0 or ch_2_coeffs_wp) and rd_req_int; end if; end if; end process; - - -- Memory ch_6_coeffs - process (adr_int, wr_adr_d0, ch_6_coeffs_wr) begin - if ch_6_coeffs_wr = '1' then - ch_6_coeffs_adr_int <= wr_adr_d0(7 downto 2); + ch_2_coeffs_we <= (wr_req_d0 or ch_2_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_2_coeffs_re) begin + if ch_2_coeffs_re = '1' then + ch_2_coeffs_addr_o <= adr_int(7 downto 2); else - ch_6_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_6_coeffs_wreq <= ch_6_coeffs_val_int_wr; - ch_6_coeffs_wr <= ch_6_coeffs_wreq; - ch_6_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_6_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_6_coeffs_val_int_dato, - rd_a_i => ch_6_coeffs_val_rreq, - wr_a_i => ch_6_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_6_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_6_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_6_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_6_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_2_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; + + -- Interface ch_3_coeffs process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_6_coeffs_val_rack <= '0'; + ch_3_coeffs_rack <= '0'; else - ch_6_coeffs_val_rack <= ch_6_coeffs_val_rreq; + ch_3_coeffs_rack <= ch_3_coeffs_re and not ch_3_coeffs_rack; end if; end if; end process; - - -- Memory ch_7_coeffs - process (adr_int, wr_adr_d0, ch_7_coeffs_wr) begin - if ch_7_coeffs_wr = '1' then - ch_7_coeffs_adr_int <= wr_adr_d0(7 downto 2); - else - ch_7_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_7_coeffs_wreq <= ch_7_coeffs_val_int_wr; - ch_7_coeffs_wr <= ch_7_coeffs_wreq; - ch_7_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_7_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_7_coeffs_val_int_dato, - rd_a_i => ch_7_coeffs_val_rreq, - wr_a_i => ch_7_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_7_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_7_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_7_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_7_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_3_coeffs_data_o <= wr_dat_d0; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_7_coeffs_val_rack <= '0'; + ch_3_coeffs_wp <= '0'; else - ch_7_coeffs_val_rack <= ch_7_coeffs_val_rreq; + ch_3_coeffs_wp <= (wr_req_d0 or ch_3_coeffs_wp) and rd_req_int; end if; end if; end process; - - -- Memory ch_8_coeffs - process (adr_int, wr_adr_d0, ch_8_coeffs_wr) begin - if ch_8_coeffs_wr = '1' then - ch_8_coeffs_adr_int <= wr_adr_d0(7 downto 2); + ch_3_coeffs_we <= (wr_req_d0 or ch_3_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_3_coeffs_re) begin + if ch_3_coeffs_re = '1' then + ch_3_coeffs_addr_o <= adr_int(7 downto 2); else - ch_8_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_8_coeffs_wreq <= ch_8_coeffs_val_int_wr; - ch_8_coeffs_wr <= ch_8_coeffs_wreq; - ch_8_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_8_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_8_coeffs_val_int_dato, - rd_a_i => ch_8_coeffs_val_rreq, - wr_a_i => ch_8_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_8_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_8_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_8_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_8_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_3_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; + + -- Interface ch_4_coeffs process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_8_coeffs_val_rack <= '0'; + ch_4_coeffs_rack <= '0'; else - ch_8_coeffs_val_rack <= ch_8_coeffs_val_rreq; + ch_4_coeffs_rack <= ch_4_coeffs_re and not ch_4_coeffs_rack; end if; end if; end process; - - -- Memory ch_9_coeffs - process (adr_int, wr_adr_d0, ch_9_coeffs_wr) begin - if ch_9_coeffs_wr = '1' then - ch_9_coeffs_adr_int <= wr_adr_d0(7 downto 2); - else - ch_9_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_9_coeffs_wreq <= ch_9_coeffs_val_int_wr; - ch_9_coeffs_wr <= ch_9_coeffs_wreq; - ch_9_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_9_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_9_coeffs_val_int_dato, - rd_a_i => ch_9_coeffs_val_rreq, - wr_a_i => ch_9_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_9_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_9_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_9_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_9_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_4_coeffs_data_o <= wr_dat_d0; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_9_coeffs_val_rack <= '0'; + ch_4_coeffs_wp <= '0'; else - ch_9_coeffs_val_rack <= ch_9_coeffs_val_rreq; + ch_4_coeffs_wp <= (wr_req_d0 or ch_4_coeffs_wp) and rd_req_int; end if; end if; end process; + ch_4_coeffs_we <= (wr_req_d0 or ch_4_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_4_coeffs_re) begin + if ch_4_coeffs_re = '1' then + ch_4_coeffs_addr_o <= adr_int(7 downto 2); + else + ch_4_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; - -- Memory ch_10_coeffs - process (adr_int, wr_adr_d0, ch_10_coeffs_wr) begin - if ch_10_coeffs_wr = '1' then - ch_10_coeffs_adr_int <= wr_adr_d0(7 downto 2); + -- Interface ch_5_coeffs + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_coeffs_rack <= '0'; + else + ch_5_coeffs_rack <= ch_5_coeffs_re and not ch_5_coeffs_rack; + end if; + end if; + end process; + ch_5_coeffs_data_o <= wr_dat_d0; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_5_coeffs_wp <= '0'; + else + ch_5_coeffs_wp <= (wr_req_d0 or ch_5_coeffs_wp) and rd_req_int; + end if; + end if; + end process; + ch_5_coeffs_we <= (wr_req_d0 or ch_5_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_5_coeffs_re) begin + if ch_5_coeffs_re = '1' then + ch_5_coeffs_addr_o <= adr_int(7 downto 2); else - ch_10_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_10_coeffs_wreq <= ch_10_coeffs_val_int_wr; - ch_10_coeffs_wr <= ch_10_coeffs_wreq; - ch_10_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_10_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_10_coeffs_val_int_dato, - rd_a_i => ch_10_coeffs_val_rreq, - wr_a_i => ch_10_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_10_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_10_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_10_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_10_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_5_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; + + -- Interface ch_6_coeffs process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_10_coeffs_val_rack <= '0'; + ch_6_coeffs_rack <= '0'; else - ch_10_coeffs_val_rack <= ch_10_coeffs_val_rreq; + ch_6_coeffs_rack <= ch_6_coeffs_re and not ch_6_coeffs_rack; end if; end if; end process; + ch_6_coeffs_data_o <= wr_dat_d0; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_6_coeffs_wp <= '0'; + else + ch_6_coeffs_wp <= (wr_req_d0 or ch_6_coeffs_wp) and rd_req_int; + end if; + end if; + end process; + ch_6_coeffs_we <= (wr_req_d0 or ch_6_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_6_coeffs_re) begin + if ch_6_coeffs_re = '1' then + ch_6_coeffs_addr_o <= adr_int(7 downto 2); + else + ch_6_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; - -- Memory ch_11_coeffs - process (adr_int, wr_adr_d0, ch_11_coeffs_wr) begin - if ch_11_coeffs_wr = '1' then - ch_11_coeffs_adr_int <= wr_adr_d0(7 downto 2); + -- Interface ch_7_coeffs + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_coeffs_rack <= '0'; + else + ch_7_coeffs_rack <= ch_7_coeffs_re and not ch_7_coeffs_rack; + end if; + end if; + end process; + ch_7_coeffs_data_o <= wr_dat_d0; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_7_coeffs_wp <= '0'; + else + ch_7_coeffs_wp <= (wr_req_d0 or ch_7_coeffs_wp) and rd_req_int; + end if; + end if; + end process; + ch_7_coeffs_we <= (wr_req_d0 or ch_7_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_7_coeffs_re) begin + if ch_7_coeffs_re = '1' then + ch_7_coeffs_addr_o <= adr_int(7 downto 2); else - ch_11_coeffs_adr_int <= adr_int(7 downto 2); - end if; - end process; - ch_11_coeffs_wreq <= ch_11_coeffs_val_int_wr; - ch_11_coeffs_wr <= ch_11_coeffs_wreq; - ch_11_coeffs_val_raminst: cheby_dpssram - generic map ( - g_data_width => 32, - g_size => 64, - g_addr_width => 6, - g_dual_clock => '0', - g_use_bwsel => '1' - ) - port map ( - clk_a_i => clk_i, - clk_b_i => clk_i, - addr_a_i => ch_11_coeffs_adr_int, - bwsel_a_i => wr_sel_d0, - data_a_i => wr_dat_d0, - data_a_o => ch_11_coeffs_val_int_dato, - rd_a_i => ch_11_coeffs_val_rreq, - wr_a_i => ch_11_coeffs_val_int_wr, - addr_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_11_coeffs_adr_i, - bwsel_b_i => (others => '1'), - data_b_i => ch_11_coeffs_val_ext_dat, - data_b_o => wb_fofb_shaper_filt_regs_ifc_o.ch_11_coeffs_val_dat_o, - rd_b_i => wb_fofb_shaper_filt_regs_ifc_i.ch_11_coeffs_val_rd_i, - wr_b_i => '0' - ); - + ch_7_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; + + -- Interface ch_8_coeffs process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ch_11_coeffs_val_rack <= '0'; + ch_8_coeffs_rack <= '0'; else - ch_11_coeffs_val_rack <= ch_11_coeffs_val_rreq; + ch_8_coeffs_rack <= ch_8_coeffs_re and not ch_8_coeffs_rack; end if; end if; end process; + ch_8_coeffs_data_o <= wr_dat_d0; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_8_coeffs_wp <= '0'; + else + ch_8_coeffs_wp <= (wr_req_d0 or ch_8_coeffs_wp) and rd_req_int; + end if; + end if; + end process; + ch_8_coeffs_we <= (wr_req_d0 or ch_8_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_8_coeffs_re) begin + if ch_8_coeffs_re = '1' then + ch_8_coeffs_addr_o <= adr_int(7 downto 2); + else + ch_8_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; - -- Register max_filt_order + -- Interface ch_9_coeffs + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_coeffs_rack <= '0'; + else + ch_9_coeffs_rack <= ch_9_coeffs_re and not ch_9_coeffs_rack; + end if; + end if; + end process; + ch_9_coeffs_data_o <= wr_dat_d0; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_9_coeffs_wp <= '0'; + else + ch_9_coeffs_wp <= (wr_req_d0 or ch_9_coeffs_wp) and rd_req_int; + end if; + end if; + end process; + ch_9_coeffs_we <= (wr_req_d0 or ch_9_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_9_coeffs_re) begin + if ch_9_coeffs_re = '1' then + ch_9_coeffs_addr_o <= adr_int(7 downto 2); + else + ch_9_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; - -- Register coeffs_fp_repr + -- Interface ch_10_coeffs + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_coeffs_rack <= '0'; + else + ch_10_coeffs_rack <= ch_10_coeffs_re and not ch_10_coeffs_rack; + end if; + end if; + end process; + ch_10_coeffs_data_o <= wr_dat_d0; + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_10_coeffs_wp <= '0'; + else + ch_10_coeffs_wp <= (wr_req_d0 or ch_10_coeffs_wp) and rd_req_int; + end if; + end if; + end process; + ch_10_coeffs_we <= (wr_req_d0 or ch_10_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_10_coeffs_re) begin + if ch_10_coeffs_re = '1' then + ch_10_coeffs_addr_o <= adr_int(7 downto 2); + else + ch_10_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; - -- Register ctl - wb_fofb_shaper_filt_regs_ifc_o.ctl_eff_coeffs <= ctl_eff_coeffs_reg; + -- Interface ch_11_coeffs + process (clk_i) begin + if rising_edge(clk_i) then + if rst_n_i = '0' then + ch_11_coeffs_rack <= '0'; + else + ch_11_coeffs_rack <= ch_11_coeffs_re and not ch_11_coeffs_rack; + end if; + end if; + end process; + ch_11_coeffs_data_o <= wr_dat_d0; process (clk_i) begin if rising_edge(clk_i) then if rst_n_i = '0' then - ctl_eff_coeffs_reg <= '0'; - ctl_wack <= '0'; + ch_11_coeffs_wp <= '0'; else - if ctl_wreq = '1' then - ctl_eff_coeffs_reg <= wr_dat_d0(0); - else - ctl_eff_coeffs_reg <= '0'; - end if; - ctl_wack <= ctl_wreq; + ch_11_coeffs_wp <= (wr_req_d0 or ch_11_coeffs_wp) and rd_req_int; end if; end if; end process; + ch_11_coeffs_we <= (wr_req_d0 or ch_11_coeffs_wp) and not rd_req_int; + process (adr_int, wr_adr_d0, ch_11_coeffs_re) begin + if ch_11_coeffs_re = '1' then + ch_11_coeffs_addr_o <= adr_int(7 downto 2); + else + ch_11_coeffs_addr_o <= wr_adr_d0(7 downto 2); + end if; + end process; + + -- Register max_filt_order + + -- Register coeffs_fp_repr -- Process for write requests. - process (wr_adr_d0, wr_req_d0, ctl_wack) begin - ch_0_coeffs_val_int_wr <= '0'; - ch_1_coeffs_val_int_wr <= '0'; - ch_2_coeffs_val_int_wr <= '0'; - ch_3_coeffs_val_int_wr <= '0'; - ch_4_coeffs_val_int_wr <= '0'; - ch_5_coeffs_val_int_wr <= '0'; - ch_6_coeffs_val_int_wr <= '0'; - ch_7_coeffs_val_int_wr <= '0'; - ch_8_coeffs_val_int_wr <= '0'; - ch_9_coeffs_val_int_wr <= '0'; - ch_10_coeffs_val_int_wr <= '0'; - ch_11_coeffs_val_int_wr <= '0'; - ctl_wreq <= '0'; + process (wr_adr_d0, ch_0_coeffs_we, ch_1_coeffs_we, ch_2_coeffs_we, + ch_3_coeffs_we, ch_4_coeffs_we, ch_5_coeffs_we, ch_6_coeffs_we, + ch_7_coeffs_we, ch_8_coeffs_we, ch_9_coeffs_we, ch_10_coeffs_we, + ch_11_coeffs_we, wr_req_d0) begin + ch_0_coeffs_wr_o <= '0'; + ch_1_coeffs_wr_o <= '0'; + ch_2_coeffs_wr_o <= '0'; + ch_3_coeffs_wr_o <= '0'; + ch_4_coeffs_wr_o <= '0'; + ch_5_coeffs_wr_o <= '0'; + ch_6_coeffs_wr_o <= '0'; + ch_7_coeffs_wr_o <= '0'; + ch_8_coeffs_wr_o <= '0'; + ch_9_coeffs_wr_o <= '0'; + ch_10_coeffs_wr_o <= '0'; + ch_11_coeffs_wr_o <= '0'; case wr_adr_d0(12 downto 8) is when "00000" => -- Memory ch_0_coeffs - ch_0_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_0_coeffs_wr_o <= ch_0_coeffs_we; + wr_ack_int <= ch_0_coeffs_we; when "00001" => -- Memory ch_1_coeffs - ch_1_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_1_coeffs_wr_o <= ch_1_coeffs_we; + wr_ack_int <= ch_1_coeffs_we; when "00010" => -- Memory ch_2_coeffs - ch_2_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_2_coeffs_wr_o <= ch_2_coeffs_we; + wr_ack_int <= ch_2_coeffs_we; when "00011" => -- Memory ch_3_coeffs - ch_3_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_3_coeffs_wr_o <= ch_3_coeffs_we; + wr_ack_int <= ch_3_coeffs_we; when "00100" => -- Memory ch_4_coeffs - ch_4_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_4_coeffs_wr_o <= ch_4_coeffs_we; + wr_ack_int <= ch_4_coeffs_we; when "00101" => -- Memory ch_5_coeffs - ch_5_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_5_coeffs_wr_o <= ch_5_coeffs_we; + wr_ack_int <= ch_5_coeffs_we; when "00110" => -- Memory ch_6_coeffs - ch_6_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_6_coeffs_wr_o <= ch_6_coeffs_we; + wr_ack_int <= ch_6_coeffs_we; when "00111" => -- Memory ch_7_coeffs - ch_7_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_7_coeffs_wr_o <= ch_7_coeffs_we; + wr_ack_int <= ch_7_coeffs_we; when "01000" => -- Memory ch_8_coeffs - ch_8_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_8_coeffs_wr_o <= ch_8_coeffs_we; + wr_ack_int <= ch_8_coeffs_we; when "01001" => -- Memory ch_9_coeffs - ch_9_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_9_coeffs_wr_o <= ch_9_coeffs_we; + wr_ack_int <= ch_9_coeffs_we; when "01010" => -- Memory ch_10_coeffs - ch_10_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_10_coeffs_wr_o <= ch_10_coeffs_we; + wr_ack_int <= ch_10_coeffs_we; when "01011" => -- Memory ch_11_coeffs - ch_11_coeffs_val_int_wr <= wr_req_d0; - wr_ack_int <= wr_req_d0; + ch_11_coeffs_wr_o <= ch_11_coeffs_we; + wr_ack_int <= ch_11_coeffs_we; when "10000" => case wr_adr_d0(7 downto 2) is when "000000" => @@ -879,10 +645,6 @@ begin when "000001" => -- Reg coeffs_fp_repr wr_ack_int <= wr_req_d0; - when "000010" => - -- Reg ctl - ctl_wreq <= wr_req_d0; - wr_ack_int <= ctl_wack; when others => wr_ack_int <= wr_req_d0; end case; @@ -892,113 +654,103 @@ begin end process; -- Process for read requests. - process (adr_int, ch_0_coeffs_val_int_dato, rd_req_int, ch_0_coeffs_val_rack, - ch_1_coeffs_val_int_dato, ch_1_coeffs_val_rack, - ch_2_coeffs_val_int_dato, ch_2_coeffs_val_rack, - ch_3_coeffs_val_int_dato, ch_3_coeffs_val_rack, - ch_4_coeffs_val_int_dato, ch_4_coeffs_val_rack, - ch_5_coeffs_val_int_dato, ch_5_coeffs_val_rack, - ch_6_coeffs_val_int_dato, ch_6_coeffs_val_rack, - ch_7_coeffs_val_int_dato, ch_7_coeffs_val_rack, - ch_8_coeffs_val_int_dato, ch_8_coeffs_val_rack, - ch_9_coeffs_val_int_dato, ch_9_coeffs_val_rack, - ch_10_coeffs_val_int_dato, ch_10_coeffs_val_rack, - ch_11_coeffs_val_int_dato, ch_11_coeffs_val_rack, - wb_fofb_shaper_filt_regs_ifc_i.max_filt_order, - wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_int_width, - wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_frac_width) begin + process (adr_int, ch_0_coeffs_data_i, ch_0_coeffs_rack, rd_req_int, + ch_1_coeffs_data_i, ch_1_coeffs_rack, ch_2_coeffs_data_i, + ch_2_coeffs_rack, ch_3_coeffs_data_i, ch_3_coeffs_rack, + ch_4_coeffs_data_i, ch_4_coeffs_rack, ch_5_coeffs_data_i, + ch_5_coeffs_rack, ch_6_coeffs_data_i, ch_6_coeffs_rack, + ch_7_coeffs_data_i, ch_7_coeffs_rack, ch_8_coeffs_data_i, + ch_8_coeffs_rack, ch_9_coeffs_data_i, ch_9_coeffs_rack, + ch_10_coeffs_data_i, ch_10_coeffs_rack, ch_11_coeffs_data_i, + ch_11_coeffs_rack, max_filt_order_i, coeffs_fp_repr_int_width_i, + coeffs_fp_repr_frac_width_i) begin -- By default ack read requests rd_dat_d0 <= (others => 'X'); - ch_0_coeffs_val_rreq <= '0'; - ch_1_coeffs_val_rreq <= '0'; - ch_2_coeffs_val_rreq <= '0'; - ch_3_coeffs_val_rreq <= '0'; - ch_4_coeffs_val_rreq <= '0'; - ch_5_coeffs_val_rreq <= '0'; - ch_6_coeffs_val_rreq <= '0'; - ch_7_coeffs_val_rreq <= '0'; - ch_8_coeffs_val_rreq <= '0'; - ch_9_coeffs_val_rreq <= '0'; - ch_10_coeffs_val_rreq <= '0'; - ch_11_coeffs_val_rreq <= '0'; + ch_0_coeffs_re <= '0'; + ch_1_coeffs_re <= '0'; + ch_2_coeffs_re <= '0'; + ch_3_coeffs_re <= '0'; + ch_4_coeffs_re <= '0'; + ch_5_coeffs_re <= '0'; + ch_6_coeffs_re <= '0'; + ch_7_coeffs_re <= '0'; + ch_8_coeffs_re <= '0'; + ch_9_coeffs_re <= '0'; + ch_10_coeffs_re <= '0'; + ch_11_coeffs_re <= '0'; case adr_int(12 downto 8) is when "00000" => -- Memory ch_0_coeffs - rd_dat_d0 <= ch_0_coeffs_val_int_dato; - ch_0_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_0_coeffs_val_rack; + rd_dat_d0 <= ch_0_coeffs_data_i; + rd_ack_d0 <= ch_0_coeffs_rack; + ch_0_coeffs_re <= rd_req_int; when "00001" => -- Memory ch_1_coeffs - rd_dat_d0 <= ch_1_coeffs_val_int_dato; - ch_1_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_1_coeffs_val_rack; + rd_dat_d0 <= ch_1_coeffs_data_i; + rd_ack_d0 <= ch_1_coeffs_rack; + ch_1_coeffs_re <= rd_req_int; when "00010" => -- Memory ch_2_coeffs - rd_dat_d0 <= ch_2_coeffs_val_int_dato; - ch_2_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_2_coeffs_val_rack; + rd_dat_d0 <= ch_2_coeffs_data_i; + rd_ack_d0 <= ch_2_coeffs_rack; + ch_2_coeffs_re <= rd_req_int; when "00011" => -- Memory ch_3_coeffs - rd_dat_d0 <= ch_3_coeffs_val_int_dato; - ch_3_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_3_coeffs_val_rack; + rd_dat_d0 <= ch_3_coeffs_data_i; + rd_ack_d0 <= ch_3_coeffs_rack; + ch_3_coeffs_re <= rd_req_int; when "00100" => -- Memory ch_4_coeffs - rd_dat_d0 <= ch_4_coeffs_val_int_dato; - ch_4_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_4_coeffs_val_rack; + rd_dat_d0 <= ch_4_coeffs_data_i; + rd_ack_d0 <= ch_4_coeffs_rack; + ch_4_coeffs_re <= rd_req_int; when "00101" => -- Memory ch_5_coeffs - rd_dat_d0 <= ch_5_coeffs_val_int_dato; - ch_5_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_5_coeffs_val_rack; + rd_dat_d0 <= ch_5_coeffs_data_i; + rd_ack_d0 <= ch_5_coeffs_rack; + ch_5_coeffs_re <= rd_req_int; when "00110" => -- Memory ch_6_coeffs - rd_dat_d0 <= ch_6_coeffs_val_int_dato; - ch_6_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_6_coeffs_val_rack; + rd_dat_d0 <= ch_6_coeffs_data_i; + rd_ack_d0 <= ch_6_coeffs_rack; + ch_6_coeffs_re <= rd_req_int; when "00111" => -- Memory ch_7_coeffs - rd_dat_d0 <= ch_7_coeffs_val_int_dato; - ch_7_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_7_coeffs_val_rack; + rd_dat_d0 <= ch_7_coeffs_data_i; + rd_ack_d0 <= ch_7_coeffs_rack; + ch_7_coeffs_re <= rd_req_int; when "01000" => -- Memory ch_8_coeffs - rd_dat_d0 <= ch_8_coeffs_val_int_dato; - ch_8_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_8_coeffs_val_rack; + rd_dat_d0 <= ch_8_coeffs_data_i; + rd_ack_d0 <= ch_8_coeffs_rack; + ch_8_coeffs_re <= rd_req_int; when "01001" => -- Memory ch_9_coeffs - rd_dat_d0 <= ch_9_coeffs_val_int_dato; - ch_9_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_9_coeffs_val_rack; + rd_dat_d0 <= ch_9_coeffs_data_i; + rd_ack_d0 <= ch_9_coeffs_rack; + ch_9_coeffs_re <= rd_req_int; when "01010" => -- Memory ch_10_coeffs - rd_dat_d0 <= ch_10_coeffs_val_int_dato; - ch_10_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_10_coeffs_val_rack; + rd_dat_d0 <= ch_10_coeffs_data_i; + rd_ack_d0 <= ch_10_coeffs_rack; + ch_10_coeffs_re <= rd_req_int; when "01011" => -- Memory ch_11_coeffs - rd_dat_d0 <= ch_11_coeffs_val_int_dato; - ch_11_coeffs_val_rreq <= rd_req_int; - rd_ack_d0 <= ch_11_coeffs_val_rack; + rd_dat_d0 <= ch_11_coeffs_data_i; + rd_ack_d0 <= ch_11_coeffs_rack; + ch_11_coeffs_re <= rd_req_int; when "10000" => case adr_int(7 downto 2) is when "000000" => -- Reg max_filt_order rd_ack_d0 <= rd_req_int; - rd_dat_d0 <= wb_fofb_shaper_filt_regs_ifc_i.max_filt_order; + rd_dat_d0 <= max_filt_order_i; when "000001" => -- Reg coeffs_fp_repr rd_ack_d0 <= rd_req_int; - rd_dat_d0(4 downto 0) <= wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_int_width; - rd_dat_d0(9 downto 5) <= wb_fofb_shaper_filt_regs_ifc_i.coeffs_fp_repr_frac_width; + rd_dat_d0(4 downto 0) <= coeffs_fp_repr_int_width_i; + rd_dat_d0(9 downto 5) <= coeffs_fp_repr_frac_width_i; rd_dat_d0(31 downto 10) <= (others => '0'); - when "000010" => - -- Reg ctl - rd_ack_d0 <= rd_req_int; - rd_dat_d0(0) <= '0'; - rd_dat_d0(31 downto 1) <= (others => '0'); when others => rd_ack_d0 <= rd_req_int; end case; diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index b3449dc0..6334ce7d 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -28,7 +28,6 @@ LIBRARY work; USE work.ifc_common_pkg.ALL; USE work.fofb_ctrl_pkg.ALL; USE work.fofb_shaper_filt_pkg.ALL; -USE work.wb_fofb_shaper_filt_regs_pkg.ALL; USE work.wishbone_pkg.ALL; ENTITY xwb_fofb_shaper_filt IS @@ -76,8 +75,19 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS TYPE t_fofb_shaper_filt_coeffs IS ARRAY (NATURAL RANGE <>) OF t_iir_filt_coeffs; - TYPE t_wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat IS - ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 downto 0); + TYPE t_wb_fofb_shaper_filt_regs_coeffs_i_ifc IS RECORD + data : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; + TYPE t_wb_fofb_shaper_filt_regs_coeffs_o_ifc IS RECORD + addr : STD_LOGIC_VECTOR(7 DOWNTO 2); + data : STD_LOGIC_VECTOR(31 DOWNTO 0); + wr : STD_LOGIC; + END RECORD; + + TYPE t_wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr IS + ARRAY (NATURAL RANGE <>) OF t_wb_fofb_shaper_filt_regs_coeffs_i_ifc; + TYPE t_wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr IS + ARRAY (NATURAL RANGE <>) OF t_wb_fofb_shaper_filt_regs_coeffs_o_ifc; -- Number of bits in Wishbone register interface -- +2 to account for BYTE addressing @@ -88,6 +98,13 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; CONSTANT c_NUM_OF_COEFFS_PER_FILT : NATURAL := 5*c_NUM_OF_BIQUADS_PER_FILT; + CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_I_IFC_0s : + t_wb_fofb_shaper_filt_regs_coeffs_i_ifc := (data => (OTHERS => '0')); + CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s : + t_wb_fofb_shaper_filt_regs_coeffs_o_ifc := (addr => (OTHERS => '0'), + data => (OTHERS => '0'), + wr => '0'); + -- The signed fixed-point representation of coefficients is aligned to the -- left in Wishbone registers PURE FUNCTION f_parse_wb_coeff(wb_coeff : STD_LOGIC_VECTOR) @@ -111,15 +128,13 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS SIGNAL wb_slave_in_d1 : t_wishbone_slave_in_array(0 DOWNTO 0); SIGNAL wb_slave_out_d1 : t_wishbone_slave_out_array(0 DOWNTO 0); - SIGNAL wb_fofb_shaper_filt_regs_ifc_master_in : - t_wb_fofb_shaper_filt_regs_ifc_master_in; - SIGNAL wb_fofb_shaper_filt_regs_ifc_master_out : - t_wb_fofb_shaper_filt_regs_ifc_master_out; - SIGNAL wb_fofb_shaper_filt_regs_ifc_coeffs_adr : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat : - t_wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(c_MAX_CHANNELS-1 DOWNTO 0); + SIGNAL wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr : + t_wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(c_MAX_CHANNELS-1 DOWNTO 0) := + (OTHERS => c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_I_IFC_0s); + SIGNAL wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr : + t_wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(c_MAX_CHANNELS-1 DOWNTO 0) := + (OTHERS => c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s); - SIGNAL state : NATURAL RANGE 0 TO 2 := 0; SIGNAL coeffs : t_fofb_shaper_filt_coeffs(g_CHANNELS-1 DOWNTO 0)( c_NUM_OF_BIQUADS_PER_FILT-1 DOWNTO 0)( b0(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), @@ -127,6 +142,9 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS b2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), a1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), a2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH)); + + SIGNAL biquad_idx : NATURAL RANGE 0 to c_NUM_OF_BIQUADS_PER_FILT-1 := 0; + SIGNAL coeff_idx : NATURAL RANGE 0 to c_NUM_OF_COEFFS_PER_FILT-1 := 0; BEGIN ASSERT c_MAX_FILT_ORDER <= 20 REPORT "ABI supports up to 20th order filters" @@ -139,85 +157,70 @@ BEGIN "to be at least 1." SEVERITY ERROR; + coeff_idx <= to_integer(UNSIGNED( + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(0).addr)); + biquad_idx <= coeff_idx/5; + PROCESS(clk_i) IS - VARIABLE v_biquad_idx : NATURAL RANGE 0 to c_NUM_OF_BIQUADS_PER_FILT-1 := 0; - VARIABLE v_coeff_idx : NATURAL RANGE 0 to c_NUM_OF_COEFFS_PER_FILT-1 := 0; BEGIN - IF rising_edge(clk_i) THEN - IF rst_n_i = '0' THEN - state <= 0; - v_coeff_idx := 0; - ELSE - CASE state IS - -- Waits for strobe signal - WHEN 0 => - IF wb_fofb_shaper_filt_regs_ifc_master_out.ctl_eff_coeffs THEN - state <= 1; - END IF; - v_coeff_idx := 0; - - -- Waits for coefficients RAMs' output update - WHEN 1 => - state <= 2; - - -- Effectivates (i.e. updates) coefficients - -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads. Each of these - -- takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). Each iir_filt - -- has a dedicated RAM holding its coefficients. These RAMs are - -- populated in the following manner: - -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: - -- coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} - -- coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} - -- coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} - -- coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} - -- coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} - -- RAMs are accessed in parallel. - WHEN 2 => - v_biquad_idx := v_coeff_idx/5; - FOR ch IN 0 TO g_CHANNELS-1 - LOOP - CASE v_coeff_idx REM 5 IS - WHEN 0 => - coeffs(ch)(v_biquad_idx).b0 <= f_parse_wb_coeff( - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); - - WHEN 1 => - coeffs(ch)(v_biquad_idx).b1 <= f_parse_wb_coeff( - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); - - - WHEN 2 => - coeffs(ch)(v_biquad_idx).b2 <= f_parse_wb_coeff( - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); - - WHEN 3 => - coeffs(ch)(v_biquad_idx).a1 <= f_parse_wb_coeff( - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); - - WHEN 4 => - coeffs(ch)(v_biquad_idx).a2 <= f_parse_wb_coeff( - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(ch)); - - WHEN OTHERS => - END CASE; - END LOOP; - - IF v_coeff_idx = c_NUM_OF_COEFFS_PER_FILT-1 THEN - state <= 0; - ELSE - v_coeff_idx := v_coeff_idx + 1; - state <= 1; - END IF; - END CASE; - - -- Addresses coefficients RAMs - -- The state machine above computes the address and waits a cycle for - -- output to update - wb_fofb_shaper_filt_regs_ifc_coeffs_adr <= - STD_LOGIC_VECTOR(to_unsigned(v_coeff_idx, - wb_fofb_shaper_filt_regs_ifc_coeffs_adr'LENGTH)); + -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads and each of these + -- has 5 associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). + -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing + -- the c_NUM_OF_COEFFS_PER_FILT = 5*c_NUM_OF_BIQUADS_PER_FILT + -- coefficients of each iir_filt. The address map is: + -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} + -- coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} + -- coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} + -- coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} + -- coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + FOR ch IN 0 TO g_CHANNELS-1 + LOOP + CASE coeff_idx REM 5 IS + WHEN 0 => + wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(ch).data <= + (to_slv(coeffs(ch)(biquad_idx).b0), OTHERS => '0'); + WHEN 1 => + wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(ch).data <= + (to_slv(coeffs(ch)(biquad_idx).b1), OTHERS => '0'); + WHEN 2 => + wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(ch).data <= + (to_slv(coeffs(ch)(biquad_idx).b2), OTHERS => '0'); + WHEN 3 => + wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(ch).data <= + (to_slv(coeffs(ch)(biquad_idx).a1), OTHERS => '0'); + WHEN 4 => + wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(ch).data <= + (to_slv(coeffs(ch)(biquad_idx).a2), OTHERS => '0'); + WHEN OTHERS => + END CASE; + + IF rising_edge(clk_i) THEN + IF rst_n_i = '0' THEN + ELSE + IF wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).wr = '1' THEN + CASE coeff_idx REM 5 IS + WHEN 0 => + coeffs(ch)(biquad_idx).b0 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).data); + WHEN 1 => + coeffs(ch)(biquad_idx).b1 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).data); + WHEN 2 => + coeffs(ch)(biquad_idx).b2 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).data); + WHEN 3 => + coeffs(ch)(biquad_idx).a1 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).data); + WHEN 4 => + coeffs(ch)(biquad_idx).a2 <= f_parse_wb_coeff( + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).data); + WHEN OTHERS => + END CASE; + END IF; + END IF; END IF; - END IF; + END LOOP; END PROCESS; gen_iir_filts : FOR idx IN 0 TO g_CHANNELS-1 @@ -254,12 +257,61 @@ BEGIN cmp_wb_fofb_shaper_filt_regs : ENTITY work.wb_fofb_shaper_filt_regs PORT MAP ( - clk_i => clk_i, - rst_n_i => rst_n_i, - wb_i => wb_slv_adp_out, - wb_o => wb_slv_adp_in, - wb_fofb_shaper_filt_regs_ifc_i => wb_fofb_shaper_filt_regs_ifc_master_in, - wb_fofb_shaper_filt_regs_ifc_o => wb_fofb_shaper_filt_regs_ifc_master_out + rst_n_i => rst_n_i, + clk_i => clk_i, + wb_i => wb_slv_adp_out, + wb_o => wb_slv_adp_in, + ch_0_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(0).addr, + ch_0_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(0).data, + ch_0_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(0).data, + ch_0_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(0).wr, + ch_1_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(1).addr, + ch_1_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(1).data, + ch_1_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(1).data, + ch_1_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(1).wr, + ch_2_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(2).addr, + ch_2_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(2).data, + ch_2_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(2).data, + ch_2_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(2).wr, + ch_3_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(3).addr, + ch_3_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(3).data, + ch_3_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(3).data, + ch_3_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(3).wr, + ch_4_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(4).addr, + ch_4_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(4).data, + ch_4_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(4).data, + ch_4_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(4).wr, + ch_5_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(5).addr, + ch_5_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(5).data, + ch_5_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(5).data, + ch_5_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(5).wr, + ch_6_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(6).addr, + ch_6_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(6).data, + ch_6_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(6).data, + ch_6_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(6).wr, + ch_7_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(7).addr, + ch_7_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(7).data, + ch_7_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(7).data, + ch_7_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(7).wr, + ch_8_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(8).addr, + ch_8_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(8).data, + ch_8_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(8).data, + ch_8_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(8).wr, + ch_9_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(9).addr, + ch_9_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(9).data, + ch_9_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(9).data, + ch_9_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(9).wr, + ch_10_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(10).addr, + ch_10_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(10).data, + ch_10_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(10).data, + ch_10_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(10).wr, + ch_11_coeffs_addr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).addr, + ch_11_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(11).data, + ch_11_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).data, + ch_11_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).wr, + max_filt_order_i => STD_LOGIC_VECTOR(to_unsigned(c_MAX_FILT_ORDER, 32)), + coeffs_fp_repr_int_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_INT_WIDTH, 5)), + coeffs_fp_repr_frac_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_FRAC_WIDTH, 5)) ); -- Extra Wishbone registering stage for ease timing @@ -327,75 +379,4 @@ BEGIN ELSE GENERATE resized_addr <= wb_slave_in(0).adr; END GENERATE; - - wb_fofb_shaper_filt_regs_ifc_master_in.ch_0_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_0_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_1_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_1_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_2_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_2_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_3_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_3_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_4_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_4_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_5_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_5_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_6_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_6_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_7_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_7_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_8_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_8_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_9_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_9_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_10_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_10_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_11_coeffs_adr_i <= - wb_fofb_shaper_filt_regs_ifc_coeffs_adr; - wb_fofb_shaper_filt_regs_ifc_master_in.ch_11_coeffs_val_rd_i <= '0'; - wb_fofb_shaper_filt_regs_ifc_master_in.max_filt_order <= - STD_LOGIC_VECTOR(to_unsigned(c_MAX_FILT_ORDER, - wb_fofb_shaper_filt_regs_ifc_master_in.max_filt_order'LENGTH)); - wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_int_width <= - STD_LOGIC_VECTOR(to_unsigned(c_COEFF_INT_WIDTH, - wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_int_width'LENGTH)); - wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_frac_width <= - STD_LOGIC_VECTOR(to_unsigned(c_COEFF_FRAC_WIDTH, - wb_fofb_shaper_filt_regs_ifc_master_in.coeffs_fp_repr_frac_width'LENGTH)); - - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(0) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_0_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(1) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_1_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(2) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_2_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(3) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_3_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(4) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_4_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(5) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_5_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(6) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_6_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(7) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_7_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(8) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_8_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(9) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_9_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(10) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_10_coeffs_val_dat_o; - wb_fofb_shaper_filt_regs_ifc_coeffs_val_dat(11) <= - wb_fofb_shaper_filt_regs_ifc_master_out.ch_11_coeffs_val_dat_o; END ARCHITECTURE behave; diff --git a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd index cbfe4a05..927c2f02 100644 --- a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd +++ b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd @@ -1,9 +1,9 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Fri Sep 22 15:10:27 2023 by guilherme.ricioli +-- Generated on Tue Apr 09 10:23:32 2024 by guilherme.ricioli package wb_fofb_shaper_filt_regs_consts_pkg is - constant c_WB_FOFB_SHAPER_FILT_REGS_SIZE : Natural := 4108; + constant c_WB_FOFB_SHAPER_FILT_REGS_SIZE : Natural := 4104; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_ADDR : Natural := 16#0#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_SIZE : Natural := 4096; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_ADDR : Natural := 16#0#; @@ -70,6 +70,4 @@ package wb_fofb_shaper_filt_regs_consts_pkg is constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_ADDR : Natural := 16#1004#; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET : Natural := 0; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET : Natural := 5; - constant c_WB_FOFB_SHAPER_FILT_REGS_CTL_ADDR : Natural := 16#1008#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CTL_EFF_COEFFS_OFFSET : Natural := 0; end package wb_fofb_shaper_filt_regs_consts_pkg; diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index 529e8cc4..6d151236 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -71,7 +71,7 @@ BEGIN FILE fin : TEXT; VARIABLE lin : LINE; VARIABLE v_wb_addr : NATURAL := 0; - VARIABLE v_wb_dat : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + VARIABLE v_wb_coeff, v_wb_dat : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); VARIABLE v_coeff : REAL; VARIABLE v_x_or_y : INTEGER; BEGIN @@ -126,7 +126,6 @@ BEGIN & NATURAL'image(c_COEFF_FRAC_WIDTH) & ")" SEVERITY ERROR; - -- Load filter coefficients file_open(fin, g_TEST_COEFFS_FILENAME, read_mode); FOR ch_idx IN 0 TO g_CHANNELS-1 LOOP @@ -139,30 +138,33 @@ BEGIN read(lin, v_coeff); -- The signed fixed-point representation of coefficients is aligned to -- the left in Wishbone registers - v_wb_dat := ( + v_wb_coeff := ( 31 DOWNTO 32-(c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH) => to_slv(to_sfixed(v_coeff, c_COEFF_INT_WIDTH-1, -c_COEFF_FRAC_WIDTH)), OTHERS => '0'); + v_wb_dat := v_wb_coeff; + + -- Load filter coefficients write32_pl(clk, wb_slave_i, wb_slave_o, v_wb_addr, v_wb_dat); + -- Read back filter coefficients + read32_pl(clk, wb_slave_i, wb_slave_o, v_wb_addr, v_wb_dat); + + ASSERT v_wb_dat = v_wb_coeff + REPORT + "UNEXPECTED FILTER COEFFICIENT " + & NATURAL'image(v_wb_addr) & ": " + & to_hstring(v_wb_dat) + & " (EXPECTED: " + & to_hstring(v_wb_coeff) & ")" + SEVERITY ERROR; + v_wb_addr := v_wb_addr + c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE; END LOOP; END LOOP; file_close(fin); - -- Effectivate (update) filter coefficients - v_wb_dat := (c_WB_FOFB_SHAPER_FILT_REGS_CTL_EFF_COEFFS_OFFSET => '1', - OTHERS => '0'); - write32_pl(clk, wb_slave_i, wb_slave_o, c_WB_FOFB_SHAPER_FILT_REGS_CTL_ADDR, - v_wb_dat); - - -- Wait for coefficients to be effectivated - -- Coefficients RAMs are accessed in parallel and each of the - -- c_NUM_OF_COEFFS_PER_FILT coefficients takes 2 cycles for being - -- effectivated. The +1 is accounting for the command detection cycle. - f_wait_cycles(clk, 2*c_NUM_OF_COEFFS_PER_FILT+1); - file_open(fin, g_TEST_X_Y_FILENAME, read_mode); WHILE NOT endfile(fin) LOOP From fd15c51b44030622eaeecd6f6ec9e0309c41af39 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 12 Apr 2024 15:14:50 -0300 Subject: [PATCH 10/26] cheby: align biquads' base addresses to a power of 2 In order to reduce the logic needed to decode coefficients' addresses, align biquads' base addresses to a power of 2. NOTE: This breaks the ABI. --- hdl/modules/fofb_ctrl_pkg.vhd | 4 +- .../cheby/doc/wb_fofb_shaper_filt_regs.html | 106 +++++++++--------- .../cheby/wb_fofb_shaper_filt_regs.cheby | 15 ++- .../cheby/wb_fofb_shaper_filt_regs.h | 44 ++++---- .../cheby/wb_fofb_shaper_filt_regs.vhd | 96 ++++++++-------- .../fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 37 +++--- .../wb_fofb_shaper_filt_regs_consts_pkg.vhd | 78 ++++++------- .../xwb_fofb_shaper_filt_tb.vhd | 75 ++++++++----- 8 files changed, 245 insertions(+), 210 deletions(-) diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index 45127647..d2c0cf45 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -774,7 +774,7 @@ package fofb_ctrl_pkg is constant c_xwb_fofb_shaper_filter_regs_sdb : t_sdb_device := ( abi_class => x"0000", -- undocumented device abi_ver_major => x"00", - abi_ver_minor => x"02", + abi_ver_minor => x"03", wbd_endian => c_sdb_endian_big, wbd_width => x"4", -- 32-bit port granularity (0100) sdb_component => ( @@ -784,7 +784,7 @@ package fofb_ctrl_pkg is vendor_id => x"1000000000001215", -- LNLS device_id => x"f65559b2", -- Last 8 chars of "FOFB_SHAPER_REGS" md5sum version => x"00000001", - date => x"20240411", + date => x"20240412", name => "FOFB_SHAPER_REGS "))); end fofb_ctrl_pkg; diff --git a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html index ad18e508..392d43e2 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html +++ b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html @@ -53,21 +53,21 @@

1. Memory map summary

C prefix -0x0000-0x0fff +0x0000-0x1fff BLOCK ch ch ch -0x0000-0x00ff +0x0000-0x01ff BLOCK ch.0 ch_0 ch.0 -0x0000-0x00ff +0x0000-0x01ff MEMORY ch.0.coeffs ch_0_coeffs @@ -81,245 +81,245 @@

1. Memory map summary

ch.0.coeffs.val -0x0100-0x01ff +0x0200-0x03ff BLOCK ch.1 ch_1 ch.1 -0x0100-0x01ff +0x0200-0x03ff MEMORY ch.1.coeffs ch_1_coeffs ch.1.coeffs - +0x0100 + +0x0200 REG ch.1.coeffs.val ch_1_coeffs_val ch.1.coeffs.val -0x0200-0x02ff +0x0400-0x05ff BLOCK ch.2 ch_2 ch.2 -0x0200-0x02ff +0x0400-0x05ff MEMORY ch.2.coeffs ch_2_coeffs ch.2.coeffs - +0x0200 + +0x0400 REG ch.2.coeffs.val ch_2_coeffs_val ch.2.coeffs.val -0x0300-0x03ff +0x0600-0x07ff BLOCK ch.3 ch_3 ch.3 -0x0300-0x03ff +0x0600-0x07ff MEMORY ch.3.coeffs ch_3_coeffs ch.3.coeffs - +0x0300 + +0x0600 REG ch.3.coeffs.val ch_3_coeffs_val ch.3.coeffs.val -0x0400-0x04ff +0x0800-0x09ff BLOCK ch.4 ch_4 ch.4 -0x0400-0x04ff +0x0800-0x09ff MEMORY ch.4.coeffs ch_4_coeffs ch.4.coeffs - +0x0400 + +0x0800 REG ch.4.coeffs.val ch_4_coeffs_val ch.4.coeffs.val -0x0500-0x05ff +0x0a00-0x0bff BLOCK ch.5 ch_5 ch.5 -0x0500-0x05ff +0x0a00-0x0bff MEMORY ch.5.coeffs ch_5_coeffs ch.5.coeffs - +0x0500 + +0x0a00 REG ch.5.coeffs.val ch_5_coeffs_val ch.5.coeffs.val -0x0600-0x06ff +0x0c00-0x0dff BLOCK ch.6 ch_6 ch.6 -0x0600-0x06ff +0x0c00-0x0dff MEMORY ch.6.coeffs ch_6_coeffs ch.6.coeffs - +0x0600 + +0x0c00 REG ch.6.coeffs.val ch_6_coeffs_val ch.6.coeffs.val -0x0700-0x07ff +0x0e00-0x0fff BLOCK ch.7 ch_7 ch.7 -0x0700-0x07ff +0x0e00-0x0fff MEMORY ch.7.coeffs ch_7_coeffs ch.7.coeffs - +0x0700 + +0x0e00 REG ch.7.coeffs.val ch_7_coeffs_val ch.7.coeffs.val -0x0800-0x08ff +0x1000-0x11ff BLOCK ch.8 ch_8 ch.8 -0x0800-0x08ff +0x1000-0x11ff MEMORY ch.8.coeffs ch_8_coeffs ch.8.coeffs - +0x0800 + +0x1000 REG ch.8.coeffs.val ch_8_coeffs_val ch.8.coeffs.val -0x0900-0x09ff +0x1200-0x13ff BLOCK ch.9 ch_9 ch.9 -0x0900-0x09ff +0x1200-0x13ff MEMORY ch.9.coeffs ch_9_coeffs ch.9.coeffs - +0x0900 + +0x1200 REG ch.9.coeffs.val ch_9_coeffs_val ch.9.coeffs.val -0x0a00-0x0aff +0x1400-0x15ff BLOCK ch.10 ch_10 ch.10 -0x0a00-0x0aff +0x1400-0x15ff MEMORY ch.10.coeffs ch_10_coeffs ch.10.coeffs - +0x0a00 + +0x1400 REG ch.10.coeffs.val ch_10_coeffs_val ch.10.coeffs.val -0x0b00-0x0bff +0x1600-0x17ff BLOCK ch.11 ch_11 ch.11 -0x0b00-0x0bff +0x1600-0x17ff MEMORY ch.11.coeffs ch_11_coeffs ch.11.coeffs - +0x0b00 + +0x1600 REG ch.11.coeffs.val ch_11_coeffs_val ch.11.coeffs.val -0x1000 +0x2000 REG max_filt_order max_filt_order max_filt_order -0x1004 +0x2004 REG coeffs_fp_repr coeffs_fp_repr @@ -404,7 +404,7 @@

2.1. ch.0.coeffs.val

2.2. ch.1.coeffs.val

- +
HW prefix:ch_1_coeffs_val
HW address:0x100
HW address:0x200
C prefix:ch.1.coeffs.val
C block offset:0x0
@@ -476,7 +476,7 @@

2.2. ch.1.coeffs.val

2.3. ch.2.coeffs.val

- +
HW prefix:ch_2_coeffs_val
HW address:0x200
HW address:0x400
C prefix:ch.2.coeffs.val
C block offset:0x0
@@ -548,7 +548,7 @@

2.3. ch.2.coeffs.val

2.4. ch.3.coeffs.val

- +
HW prefix:ch_3_coeffs_val
HW address:0x300
HW address:0x600
C prefix:ch.3.coeffs.val
C block offset:0x0
@@ -620,7 +620,7 @@

2.4. ch.3.coeffs.val

2.5. ch.4.coeffs.val

- +
HW prefix:ch_4_coeffs_val
HW address:0x400
HW address:0x800
C prefix:ch.4.coeffs.val
C block offset:0x0
@@ -692,7 +692,7 @@

2.5. ch.4.coeffs.val

2.6. ch.5.coeffs.val

- +
HW prefix:ch_5_coeffs_val
HW address:0x500
HW address:0xa00
C prefix:ch.5.coeffs.val
C block offset:0x0
@@ -764,7 +764,7 @@

2.6. ch.5.coeffs.val

2.7. ch.6.coeffs.val

- +
HW prefix:ch_6_coeffs_val
HW address:0x600
HW address:0xc00
C prefix:ch.6.coeffs.val
C block offset:0x0
@@ -836,7 +836,7 @@

2.7. ch.6.coeffs.val

2.8. ch.7.coeffs.val

- +
HW prefix:ch_7_coeffs_val
HW address:0x700
HW address:0xe00
C prefix:ch.7.coeffs.val
C block offset:0x0
@@ -908,7 +908,7 @@

2.8. ch.7.coeffs.val

2.9. ch.8.coeffs.val

- +
HW prefix:ch_8_coeffs_val
HW address:0x800
HW address:0x1000
C prefix:ch.8.coeffs.val
C block offset:0x0
@@ -980,7 +980,7 @@

2.9. ch.8.coeffs.val

2.10. ch.9.coeffs.val

- +
HW prefix:ch_9_coeffs_val
HW address:0x900
HW address:0x1200
C prefix:ch.9.coeffs.val
C block offset:0x0
@@ -1052,7 +1052,7 @@

2.10. ch.9.coeffs.val

2.11. ch.10.coeffs.val

- +
HW prefix:ch_10_coeffs_val
HW address:0xa00
HW address:0x1400
C prefix:ch.10.coeffs.val
C block offset:0x0
@@ -1124,7 +1124,7 @@

2.11. ch.10.coeffs.val

2.12. ch.11.coeffs.val

- +
HW prefix:ch_11_coeffs_val
HW address:0xb00
HW address:0x1600
C prefix:ch.11.coeffs.val
C block offset:0x0
@@ -1196,9 +1196,9 @@

2.12. ch.11.coeffs.val

2.13. max_filt_order

- + - +
HW prefix:max_filt_order
HW address:0x1000
HW address:0x2000
C prefix:max_filt_order
C block offset:0x1000
C block offset:0x2000

Maximum filter order supported by the gateware.
@@ -1267,9 +1267,9 @@

2.13. max_filt_order

2.14. coeffs_fp_repr

- + - +
HW prefix:coeffs_fp_repr
HW address:0x1004
HW address:0x2004
C prefix:coeffs_fp_repr
C block offset:0x1004
C block offset:0x2004

Fixed-point signed representation of coefficients.
The coefficients should be aligned to the left. The fixed-point
position is then given by 32 - 'int_width' (i.e. one should divide
this register's content by 2**{32 - 'int_width'} to get the
represented decimal number.
diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby index b584cd1c..0f533240 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby @@ -11,7 +11,7 @@ memory-map: children: - memory: name: coeffs - memsize: 200 + memsize: 320 interface: sram description: | Coefficients for the ceil('max_filt_order'/2) IIR internal @@ -20,11 +20,14 @@ memory-map: Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: - coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} - coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} - coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} - coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} - coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + coeffs[0 + 8*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 8*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 8*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 8*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 8*{biquad_idx}] = a2 of biquad {biquad_idx} + coeffs[5 + 8*{biquad_idx}] = unused + coeffs[6 + 8*{biquad_idx}] = unused + coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the coefficients corresponding to the first 'max_filt_order' filters diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h index 6984809c..f879ec4f 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h @@ -1,10 +1,10 @@ #ifndef __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__ #define __CHEBY__WB_FOFB_SHAPER_FILT_REGS__H__ -#define WB_FOFB_SHAPER_FILT_REGS_SIZE 4104 /* 0x1008 */ +#define WB_FOFB_SHAPER_FILT_REGS_SIZE 8200 /* 0x2008 */ /* None */ #define WB_FOFB_SHAPER_FILT_REGS_CH 0x0UL -#define WB_FOFB_SHAPER_FILT_REGS_CH_SIZE 256 /* 0x100 */ +#define WB_FOFB_SHAPER_FILT_REGS_CH_SIZE 512 /* 0x200 */ /* Coefficients for the ceil('max_filt_order'/2) IIR internal biquads. @@ -12,11 +12,14 @@ biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: - coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} - coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} - coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} - coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} - coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + coeffs[0 + 8*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 8*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 8*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 8*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 8*{biquad_idx}] = a2 of biquad {biquad_idx} + coeffs[5 + 8*{biquad_idx}] = unused + coeffs[6 + 8*{biquad_idx}] = unused + coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the coefficients corresponding to the first 'max_filt_order' filters @@ -32,7 +35,7 @@ representation. It should be aligned to the left. /* Maximum filter order supported by the gateware. */ -#define WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER 0x1000UL +#define WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER 0x2000UL /* Fixed-point signed representation of coefficients. The coefficients should be aligned to the left. The fixed-point @@ -40,7 +43,7 @@ position is then given by 32 - 'int_width' (i.e. one should divide this register's content by 2**{32 - 'int_width'} to get the represented decimal number. */ -#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR 0x1004UL +#define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR 0x2004UL #define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_MASK 0x1fUL #define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_SHIFT 0 #define WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_MASK 0x3e0UL @@ -56,11 +59,14 @@ biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: - coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} - coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} - coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} - coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} - coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + coeffs[0 + 8*{biquad_idx}] = b0 of biquad {biquad_idx} + coeffs[1 + 8*{biquad_idx}] = b1 of biquad {biquad_idx} + coeffs[2 + 8*{biquad_idx}] = b2 of biquad {biquad_idx} + coeffs[3 + 8*{biquad_idx}] = a1 of biquad {biquad_idx} + coeffs[4 + 8*{biquad_idx}] = a2 of biquad {biquad_idx} + coeffs[5 + 8*{biquad_idx}] = unused + coeffs[6 + 8*{biquad_idx}] = unused + coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the coefficients corresponding to the first 'max_filt_order' filters @@ -71,20 +77,20 @@ are meaningful for the gateware. representation. It should be aligned to the left. */ uint32_t val; - } coeffs[50]; + } coeffs[80]; /* padding to: 0 words */ - uint32_t __padding_0[14]; + uint32_t __padding_0[48]; } ch[12]; /* padding to: 0 words */ - uint32_t __padding_0[256]; + uint32_t __padding_0[512]; - /* [0x1000]: REG (ro) Maximum filter order supported by the gateware. + /* [0x2000]: REG (ro) Maximum filter order supported by the gateware. */ uint32_t max_filt_order; - /* [0x1004]: REG (ro) Fixed-point signed representation of coefficients. + /* [0x2004]: REG (ro) Fixed-point signed representation of coefficients. The coefficients should be aligned to the left. The fixed-point position is then given by 32 - 'int_width' (i.e. one should divide this register's content by 2**{32 - 'int_width'} to get the diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd index 621218aa..d39e5943 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd @@ -1,6 +1,6 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Tue Apr 09 10:23:32 2024 by guilherme.ricioli +-- Generated on Fri Apr 12 13:09:19 2024 by guilherme.ricioli library ieee; @@ -16,73 +16,73 @@ entity wb_fofb_shaper_filt_regs is wb_o : out t_wishbone_slave_out; -- SRAM bus ch_0_coeffs - ch_0_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_0_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_0_coeffs_data_i : in std_logic_vector(31 downto 0); ch_0_coeffs_data_o : out std_logic_vector(31 downto 0); ch_0_coeffs_wr_o : out std_logic; -- SRAM bus ch_1_coeffs - ch_1_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_1_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_1_coeffs_data_i : in std_logic_vector(31 downto 0); ch_1_coeffs_data_o : out std_logic_vector(31 downto 0); ch_1_coeffs_wr_o : out std_logic; -- SRAM bus ch_2_coeffs - ch_2_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_2_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_2_coeffs_data_i : in std_logic_vector(31 downto 0); ch_2_coeffs_data_o : out std_logic_vector(31 downto 0); ch_2_coeffs_wr_o : out std_logic; -- SRAM bus ch_3_coeffs - ch_3_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_3_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_3_coeffs_data_i : in std_logic_vector(31 downto 0); ch_3_coeffs_data_o : out std_logic_vector(31 downto 0); ch_3_coeffs_wr_o : out std_logic; -- SRAM bus ch_4_coeffs - ch_4_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_4_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_4_coeffs_data_i : in std_logic_vector(31 downto 0); ch_4_coeffs_data_o : out std_logic_vector(31 downto 0); ch_4_coeffs_wr_o : out std_logic; -- SRAM bus ch_5_coeffs - ch_5_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_5_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_5_coeffs_data_i : in std_logic_vector(31 downto 0); ch_5_coeffs_data_o : out std_logic_vector(31 downto 0); ch_5_coeffs_wr_o : out std_logic; -- SRAM bus ch_6_coeffs - ch_6_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_6_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_6_coeffs_data_i : in std_logic_vector(31 downto 0); ch_6_coeffs_data_o : out std_logic_vector(31 downto 0); ch_6_coeffs_wr_o : out std_logic; -- SRAM bus ch_7_coeffs - ch_7_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_7_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_7_coeffs_data_i : in std_logic_vector(31 downto 0); ch_7_coeffs_data_o : out std_logic_vector(31 downto 0); ch_7_coeffs_wr_o : out std_logic; -- SRAM bus ch_8_coeffs - ch_8_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_8_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_8_coeffs_data_i : in std_logic_vector(31 downto 0); ch_8_coeffs_data_o : out std_logic_vector(31 downto 0); ch_8_coeffs_wr_o : out std_logic; -- SRAM bus ch_9_coeffs - ch_9_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_9_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_9_coeffs_data_i : in std_logic_vector(31 downto 0); ch_9_coeffs_data_o : out std_logic_vector(31 downto 0); ch_9_coeffs_wr_o : out std_logic; -- SRAM bus ch_10_coeffs - ch_10_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_10_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_10_coeffs_data_i : in std_logic_vector(31 downto 0); ch_10_coeffs_data_o : out std_logic_vector(31 downto 0); ch_10_coeffs_wr_o : out std_logic; -- SRAM bus ch_11_coeffs - ch_11_coeffs_addr_o : out std_logic_vector(7 downto 2); + ch_11_coeffs_addr_o : out std_logic_vector(8 downto 2); ch_11_coeffs_data_i : in std_logic_vector(31 downto 0); ch_11_coeffs_data_o : out std_logic_vector(31 downto 0); ch_11_coeffs_wr_o : out std_logic; @@ -107,7 +107,7 @@ entity wb_fofb_shaper_filt_regs is end wb_fofb_shaper_filt_regs; architecture syn of wb_fofb_shaper_filt_regs is - signal adr_int : std_logic_vector(12 downto 2); + signal adr_int : std_logic_vector(13 downto 2); signal rd_req_int : std_logic; signal wr_req_int : std_logic; signal rd_ack_int : std_logic; @@ -143,7 +143,7 @@ architecture syn of wb_fofb_shaper_filt_regs is signal rd_ack_d0 : std_logic; signal rd_dat_d0 : std_logic_vector(31 downto 0); signal wr_req_d0 : std_logic; - signal wr_adr_d0 : std_logic_vector(12 downto 2); + signal wr_adr_d0 : std_logic_vector(13 downto 2); signal wr_dat_d0 : std_logic_vector(31 downto 0); signal ch_0_coeffs_wp : std_logic; signal ch_0_coeffs_we : std_logic; @@ -172,7 +172,7 @@ architecture syn of wb_fofb_shaper_filt_regs is begin -- WB decode signals - adr_int <= wb_i.adr(12 downto 2); + adr_int <= wb_i.adr(13 downto 2); wb_en <= wb_i.cyc and wb_i.stb; process (clk_i) begin @@ -242,9 +242,9 @@ begin ch_0_coeffs_we <= (wr_req_d0 or ch_0_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_0_coeffs_re) begin if ch_0_coeffs_re = '1' then - ch_0_coeffs_addr_o <= adr_int(7 downto 2); + ch_0_coeffs_addr_o <= adr_int(8 downto 2); else - ch_0_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_0_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -271,9 +271,9 @@ begin ch_1_coeffs_we <= (wr_req_d0 or ch_1_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_1_coeffs_re) begin if ch_1_coeffs_re = '1' then - ch_1_coeffs_addr_o <= adr_int(7 downto 2); + ch_1_coeffs_addr_o <= adr_int(8 downto 2); else - ch_1_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_1_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -300,9 +300,9 @@ begin ch_2_coeffs_we <= (wr_req_d0 or ch_2_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_2_coeffs_re) begin if ch_2_coeffs_re = '1' then - ch_2_coeffs_addr_o <= adr_int(7 downto 2); + ch_2_coeffs_addr_o <= adr_int(8 downto 2); else - ch_2_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_2_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -329,9 +329,9 @@ begin ch_3_coeffs_we <= (wr_req_d0 or ch_3_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_3_coeffs_re) begin if ch_3_coeffs_re = '1' then - ch_3_coeffs_addr_o <= adr_int(7 downto 2); + ch_3_coeffs_addr_o <= adr_int(8 downto 2); else - ch_3_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_3_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -358,9 +358,9 @@ begin ch_4_coeffs_we <= (wr_req_d0 or ch_4_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_4_coeffs_re) begin if ch_4_coeffs_re = '1' then - ch_4_coeffs_addr_o <= adr_int(7 downto 2); + ch_4_coeffs_addr_o <= adr_int(8 downto 2); else - ch_4_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_4_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -387,9 +387,9 @@ begin ch_5_coeffs_we <= (wr_req_d0 or ch_5_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_5_coeffs_re) begin if ch_5_coeffs_re = '1' then - ch_5_coeffs_addr_o <= adr_int(7 downto 2); + ch_5_coeffs_addr_o <= adr_int(8 downto 2); else - ch_5_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_5_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -416,9 +416,9 @@ begin ch_6_coeffs_we <= (wr_req_d0 or ch_6_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_6_coeffs_re) begin if ch_6_coeffs_re = '1' then - ch_6_coeffs_addr_o <= adr_int(7 downto 2); + ch_6_coeffs_addr_o <= adr_int(8 downto 2); else - ch_6_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_6_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -445,9 +445,9 @@ begin ch_7_coeffs_we <= (wr_req_d0 or ch_7_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_7_coeffs_re) begin if ch_7_coeffs_re = '1' then - ch_7_coeffs_addr_o <= adr_int(7 downto 2); + ch_7_coeffs_addr_o <= adr_int(8 downto 2); else - ch_7_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_7_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -474,9 +474,9 @@ begin ch_8_coeffs_we <= (wr_req_d0 or ch_8_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_8_coeffs_re) begin if ch_8_coeffs_re = '1' then - ch_8_coeffs_addr_o <= adr_int(7 downto 2); + ch_8_coeffs_addr_o <= adr_int(8 downto 2); else - ch_8_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_8_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -503,9 +503,9 @@ begin ch_9_coeffs_we <= (wr_req_d0 or ch_9_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_9_coeffs_re) begin if ch_9_coeffs_re = '1' then - ch_9_coeffs_addr_o <= adr_int(7 downto 2); + ch_9_coeffs_addr_o <= adr_int(8 downto 2); else - ch_9_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_9_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -532,9 +532,9 @@ begin ch_10_coeffs_we <= (wr_req_d0 or ch_10_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_10_coeffs_re) begin if ch_10_coeffs_re = '1' then - ch_10_coeffs_addr_o <= adr_int(7 downto 2); + ch_10_coeffs_addr_o <= adr_int(8 downto 2); else - ch_10_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_10_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -561,9 +561,9 @@ begin ch_11_coeffs_we <= (wr_req_d0 or ch_11_coeffs_wp) and not rd_req_int; process (adr_int, wr_adr_d0, ch_11_coeffs_re) begin if ch_11_coeffs_re = '1' then - ch_11_coeffs_addr_o <= adr_int(7 downto 2); + ch_11_coeffs_addr_o <= adr_int(8 downto 2); else - ch_11_coeffs_addr_o <= wr_adr_d0(7 downto 2); + ch_11_coeffs_addr_o <= wr_adr_d0(8 downto 2); end if; end process; @@ -588,7 +588,7 @@ begin ch_9_coeffs_wr_o <= '0'; ch_10_coeffs_wr_o <= '0'; ch_11_coeffs_wr_o <= '0'; - case wr_adr_d0(12 downto 8) is + case wr_adr_d0(13 downto 9) is when "00000" => -- Memory ch_0_coeffs ch_0_coeffs_wr_o <= ch_0_coeffs_we; @@ -638,11 +638,11 @@ begin ch_11_coeffs_wr_o <= ch_11_coeffs_we; wr_ack_int <= ch_11_coeffs_we; when "10000" => - case wr_adr_d0(7 downto 2) is - when "000000" => + case wr_adr_d0(8 downto 2) is + when "0000000" => -- Reg max_filt_order wr_ack_int <= wr_req_d0; - when "000001" => + when "0000001" => -- Reg coeffs_fp_repr wr_ack_int <= wr_req_d0; when others => @@ -678,7 +678,7 @@ begin ch_9_coeffs_re <= '0'; ch_10_coeffs_re <= '0'; ch_11_coeffs_re <= '0'; - case adr_int(12 downto 8) is + case adr_int(13 downto 9) is when "00000" => -- Memory ch_0_coeffs rd_dat_d0 <= ch_0_coeffs_data_i; @@ -740,12 +740,12 @@ begin rd_ack_d0 <= ch_11_coeffs_rack; ch_11_coeffs_re <= rd_req_int; when "10000" => - case adr_int(7 downto 2) is - when "000000" => + case adr_int(8 downto 2) is + when "0000000" => -- Reg max_filt_order rd_ack_d0 <= rd_req_int; rd_dat_d0 <= max_filt_order_i; - when "000001" => + when "0000001" => -- Reg coeffs_fp_repr rd_ack_d0 <= rd_req_int; rd_dat_d0(4 downto 0) <= coeffs_fp_repr_int_width_i; diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index 6334ce7d..0238d610 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -79,7 +79,7 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS data : STD_LOGIC_VECTOR(31 DOWNTO 0); END RECORD; TYPE t_wb_fofb_shaper_filt_regs_coeffs_o_ifc IS RECORD - addr : STD_LOGIC_VECTOR(7 DOWNTO 2); + addr : STD_LOGIC_VECTOR(8 DOWNTO 2); data : STD_LOGIC_VECTOR(31 DOWNTO 0); wr : STD_LOGIC; END RECORD; @@ -96,7 +96,6 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS CONSTANT c_MAX_CHANNELS : NATURAL := 12; CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; - CONSTANT c_NUM_OF_COEFFS_PER_FILT : NATURAL := 5*c_NUM_OF_BIQUADS_PER_FILT; CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_I_IFC_0s : t_wb_fofb_shaper_filt_regs_coeffs_i_ifc := (data => (OTHERS => '0')); @@ -144,7 +143,7 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS a2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH)); SIGNAL biquad_idx : NATURAL RANGE 0 to c_NUM_OF_BIQUADS_PER_FILT-1 := 0; - SIGNAL coeff_idx : NATURAL RANGE 0 to c_NUM_OF_COEFFS_PER_FILT-1 := 0; + SIGNAL coeff_idx : NATURAL RANGE 0 to 4 := 0; BEGIN ASSERT c_MAX_FILT_ORDER <= 20 REPORT "ABI supports up to 20th order filters" @@ -157,26 +156,34 @@ BEGIN "to be at least 1." SEVERITY ERROR; + -- NOTE: All wb_fofb_shaper_filt_regs RAM interfaces addresses are + -- internally connected to same signals. So, pick just one of + -- them to index the coefficients. + biquad_idx <= to_integer(UNSIGNED( + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(0).addr(8 DOWNTO 5))); coeff_idx <= to_integer(UNSIGNED( - wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(0).addr)); - biquad_idx <= coeff_idx/5; + wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(0).addr(4 DOWNTO 2))); PROCESS(clk_i) IS BEGIN -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads and each of these -- has 5 associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing - -- the c_NUM_OF_COEFFS_PER_FILT = 5*c_NUM_OF_BIQUADS_PER_FILT - -- coefficients of each iir_filt. The address map is: - -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: - -- coeffs[0 + 5*{biquad_idx}] = b0 of biquad {biquad_idx} - -- coeffs[1 + 5*{biquad_idx}] = b1 of biquad {biquad_idx} - -- coeffs[2 + 5*{biquad_idx}] = b2 of biquad {biquad_idx} - -- coeffs[3 + 5*{biquad_idx}] = a1 of biquad {biquad_idx} - -- coeffs[4 + 5*{biquad_idx}] = a2 of biquad {biquad_idx} + -- the 5*c_NUM_OF_BIQUADS_PER_FILT coefficients of each iir_filt. + -- + -- The address map is: + -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} + -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} + -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} + -- RAM address 3 + 8*{biquad_idx} = a1 of biquad {biquad_idx} + -- RAM address 4 + 8*{biquad_idx} = a2 of biquad {biquad_idx} + -- RAM address 5 + 8*{biquad_idx} = unused + -- RAM address 6 + 8*{biquad_idx} = unused + -- RAM address 7 + 8*{biquad_idx} = unused FOR ch IN 0 TO g_CHANNELS-1 LOOP - CASE coeff_idx REM 5 IS + CASE coeff_idx IS WHEN 0 => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(ch).data <= (to_slv(coeffs(ch)(biquad_idx).b0), OTHERS => '0'); @@ -199,7 +206,7 @@ BEGIN IF rst_n_i = '0' THEN ELSE IF wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).wr = '1' THEN - CASE coeff_idx REM 5 IS + CASE coeff_idx IS WHEN 0 => coeffs(ch)(biquad_idx).b0 <= f_parse_wb_coeff( wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(ch).data); diff --git a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd index 927c2f02..ce1e79ea 100644 --- a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd +++ b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd @@ -1,73 +1,73 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Tue Apr 09 10:23:32 2024 by guilherme.ricioli +-- Generated on Fri Apr 12 13:09:19 2024 by guilherme.ricioli package wb_fofb_shaper_filt_regs_consts_pkg is - constant c_WB_FOFB_SHAPER_FILT_REGS_SIZE : Natural := 4104; + constant c_WB_FOFB_SHAPER_FILT_REGS_SIZE : Natural := 8200; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_SIZE : Natural := 4096; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_SIZE : Natural := 8192; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE : Natural := 256; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE : Natural := 512; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_ADDR : Natural := 16#0#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_ADDR : Natural := 16#100#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_COEFFS_ADDR : Natural := 16#100#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_ADDR : Natural := 16#200#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_COEFFS_ADDR : Natural := 16#200#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_1_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_ADDR : Natural := 16#200#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_COEFFS_ADDR : Natural := 16#200#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_ADDR : Natural := 16#400#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_COEFFS_ADDR : Natural := 16#400#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_2_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_ADDR : Natural := 16#300#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_COEFFS_ADDR : Natural := 16#300#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_ADDR : Natural := 16#600#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_COEFFS_ADDR : Natural := 16#600#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_3_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_ADDR : Natural := 16#400#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_COEFFS_ADDR : Natural := 16#400#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_ADDR : Natural := 16#800#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_COEFFS_ADDR : Natural := 16#800#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_4_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_ADDR : Natural := 16#500#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_COEFFS_ADDR : Natural := 16#500#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_ADDR : Natural := 16#a00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_COEFFS_ADDR : Natural := 16#a00#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_5_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_ADDR : Natural := 16#600#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_COEFFS_ADDR : Natural := 16#600#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_ADDR : Natural := 16#c00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_COEFFS_ADDR : Natural := 16#c00#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_6_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_ADDR : Natural := 16#700#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_COEFFS_ADDR : Natural := 16#700#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_ADDR : Natural := 16#e00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_COEFFS_ADDR : Natural := 16#e00#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_7_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_ADDR : Natural := 16#800#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_COEFFS_ADDR : Natural := 16#800#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_ADDR : Natural := 16#1000#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_COEFFS_ADDR : Natural := 16#1000#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_8_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_ADDR : Natural := 16#900#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_COEFFS_ADDR : Natural := 16#900#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_ADDR : Natural := 16#1200#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_COEFFS_ADDR : Natural := 16#1200#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_9_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_ADDR : Natural := 16#a00#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_COEFFS_ADDR : Natural := 16#a00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_ADDR : Natural := 16#1400#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_COEFFS_ADDR : Natural := 16#1400#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_10_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_ADDR : Natural := 16#b00#; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_SIZE : Natural := 256; - constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_ADDR : Natural := 16#b00#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_ADDR : Natural := 16#1600#; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_SIZE : Natural := 512; + constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_ADDR : Natural := 16#1600#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR : Natural := 16#1000#; - constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_ADDR : Natural := 16#1004#; + constant c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR : Natural := 16#2000#; + constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_ADDR : Natural := 16#2004#; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET : Natural := 0; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET : Natural := 5; end package wb_fofb_shaper_filt_regs_consts_pkg; diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index 6d151236..de76e3a0 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -52,7 +52,6 @@ END ENTITY xwb_fofb_shaper_filt_tb; ARCHITECTURE test OF xwb_fofb_shaper_filt_tb IS CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; - CONSTANT c_NUM_OF_COEFFS_PER_FILT : NATURAL := 5*c_NUM_OF_BIQUADS_PER_FILT; CONSTANT c_SYS_CLOCK_FREQ : NATURAL := 100_000_000; SIGNAL clk : STD_LOGIC := '0'; @@ -126,6 +125,21 @@ BEGIN & NATURAL'image(c_COEFF_FRAC_WIDTH) & ")" SEVERITY ERROR; + -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads and each of these + -- has 5 associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). + -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing + -- the 5*c_NUM_OF_BIQUADS_PER_FILT coefficients of each iir_filt. + -- + -- The address map is: + -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} + -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} + -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} + -- RAM address 3 + 8*{biquad_idx} = a1 of biquad {biquad_idx} + -- RAM address 4 + 8*{biquad_idx} = a2 of biquad {biquad_idx} + -- RAM address 5 + 8*{biquad_idx} = unused + -- RAM address 6 + 8*{biquad_idx} = unused + -- RAM address 7 + 8*{biquad_idx} = unused file_open(fin, g_TEST_COEFFS_FILENAME, read_mode); FOR ch_idx IN 0 TO g_CHANNELS-1 LOOP @@ -133,34 +147,39 @@ BEGIN ch_idx*c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE; readline(fin, lin); - FOR coeff_idx IN 0 TO c_NUM_OF_COEFFS_PER_FILT-1 + FOR biquad_idx IN 0 TO c_NUM_OF_BIQUADS_PER_FILT-1 LOOP - read(lin, v_coeff); - -- The signed fixed-point representation of coefficients is aligned to - -- the left in Wishbone registers - v_wb_coeff := ( - 31 DOWNTO 32-(c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH) => - to_slv(to_sfixed(v_coeff, c_COEFF_INT_WIDTH-1, - -c_COEFF_FRAC_WIDTH)), - OTHERS => '0'); - v_wb_dat := v_wb_coeff; - - -- Load filter coefficients - write32_pl(clk, wb_slave_i, wb_slave_o, v_wb_addr, v_wb_dat); - - -- Read back filter coefficients - read32_pl(clk, wb_slave_i, wb_slave_o, v_wb_addr, v_wb_dat); - - ASSERT v_wb_dat = v_wb_coeff - REPORT - "UNEXPECTED FILTER COEFFICIENT " - & NATURAL'image(v_wb_addr) & ": " - & to_hstring(v_wb_dat) - & " (EXPECTED: " - & to_hstring(v_wb_coeff) & ")" - SEVERITY ERROR; - - v_wb_addr := v_wb_addr + c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE; + FOR coeff_idx IN 0 TO 4 + LOOP + read(lin, v_coeff); + -- The signed fixed-point representation of coefficients is aligned to + -- the left in Wishbone registers + v_wb_coeff := ( + 31 DOWNTO 32-(c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH) => + to_slv(to_sfixed(v_coeff, c_COEFF_INT_WIDTH-1, + -c_COEFF_FRAC_WIDTH)), + OTHERS => '0'); + v_wb_dat := v_wb_coeff; + + -- Load filter coefficients + write32_pl(clk, wb_slave_i, wb_slave_o, v_wb_addr, v_wb_dat); + + -- Read back filter coefficients + read32_pl(clk, wb_slave_i, wb_slave_o, v_wb_addr, v_wb_dat); + + ASSERT v_wb_dat = v_wb_coeff + REPORT + "UNEXPECTED FILTER COEFFICIENT " + & NATURAL'image(v_wb_addr) & ": " + & to_hstring(v_wb_dat) + & " (EXPECTED: " + & to_hstring(v_wb_coeff) & ")" + SEVERITY ERROR; + + v_wb_addr := v_wb_addr + c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE; + END LOOP; + -- Unused addresses + v_wb_addr := v_wb_addr + 3*c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE; END LOOP; END LOOP; file_close(fin); From 231287e25054e4389c65ae97ac4b07e0b9f1ecbb Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Mon, 15 Apr 2024 14:24:01 -0300 Subject: [PATCH 11/26] fofb_shaper_filt_pkg.vhd: reduce maximum filter order Even with the optimizations from the latest commits, synthesis can't close timing. By now, the two options we found that solve this issue are: 1. Reduce the number of supported channels from 12 to 8. 2. Reduce the maximum filter order from 10 to 8. We picked option 2: Although current operation doesn't require more than 8 channels, we want to keep those 4 extras as a backup for any malfuction. Also, we currently don't have a real demand for {9,10}th order filters. The testbench files changed accordingly. --- .../fofb_shaper_filt/fofb_shaper_filt_pkg.vhd | 2 +- .../fofb_shaper_filt_coeffs.dat | 24 +- .../fofb_shaper_filt_x_y.dat | 400 +++++++++--------- .../xwb_fofb_shaper_filt_tb.vhd | 4 +- 4 files changed, 215 insertions(+), 215 deletions(-) diff --git a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd index 6e56693c..863c38f2 100644 --- a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd +++ b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd @@ -27,7 +27,7 @@ USE work.wishbone_pkg.ALL; PACKAGE fofb_shaper_filt_pkg IS -- The maximum filter order supported - CONSTANT c_MAX_FILT_ORDER : NATURAL := 10; + CONSTANT c_MAX_FILT_ORDER : NATURAL := 8; -- The signed fixed-point representation of filters' coefficients CONSTANT c_COEFF_INT_WIDTH : NATURAL := 2; diff --git a/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat index aa4deb88..2a02f909 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat +++ b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat @@ -1,12 +1,12 @@ -2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 7.29453817e-01 -2.89644590e-03 5.79289180e-03 2.89644590e-03 -7.11236625e-17 6.19395866e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 5.76378106e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 1.71572875e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 3.75524806e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.11022302e-16 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-2378 -2378 -2378 + -6635 -6635 -6635 -6635 -6635 -6635 -6635 -6635 -6635 -6635 -6635 -6635 2540 2540 2540 2540 2540 2540 2540 2540 2540 2540 2540 2540 + -1945 -1945 -1945 -1945 -1945 -1945 -1945 -1945 -1945 -1945 -1945 -1945 16140 16140 16140 16140 16140 16140 16140 16140 16140 16140 16140 16140 + 23679 23679 23679 23679 23679 23679 23679 23679 23679 23679 23679 23679 22954 22954 22954 22954 22954 22954 22954 22954 22954 22954 22954 22954 diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index de76e3a0..a393c6f7 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -46,7 +46,7 @@ ENTITY xwb_fofb_shaper_filt_tb IS -- Extra bits for biquads' internal arithmetic g_ARITH_EXTRA_BITS : NATURAL := 0; -- Extra bits for between-biquads cascade interfaces - g_IFCS_EXTRA_BITS : NATURAL := 4 + g_IFCS_EXTRA_BITS : NATURAL := 5 ); END ENTITY xwb_fofb_shaper_filt_tb; @@ -208,7 +208,7 @@ BEGIN LOOP read(lin, v_x_or_y); IF ABS(REAL(to_integer(filt_sp_arr(ch_idx)))/REAL(v_x_or_y) - 1.0) > - 0.01 THEN + 0.05 THEN REPORT "TOO LARGE ERROR (> 1%): " & INTEGER'image(to_integer(filt_sp_arr(ch_idx))) From 2c6d099a1ca884c2535dd97f5915663f92ac57de Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 18 Apr 2024 15:27:17 -0300 Subject: [PATCH 12/26] cheby: clearify the signed representation we use Which is 2's complement. --- .../fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html | 4 ++-- .../fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby | 4 ++-- hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h | 4 ++-- .../fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html index 392d43e2..f44d4206 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html +++ b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html @@ -1272,7 +1272,7 @@

2.14. coeffs_fp_repr

C block offset:0x2004

-Fixed-point signed representation of coefficients.
The coefficients should be aligned to the left. The fixed-point
position is then given by 32 - 'int_width' (i.e. one should divide
this register's content by 2**{32 - 'int_width'} to get the
represented decimal number.
+Fixed-point signed (2's complement) representation of coefficients.
The coefficients should be aligned to the left. The fixed-point
position is then given by 32 - 'int_width' (i.e. one should divide
this register's content by 2**{32 - 'int_width'} to get the
represented decimal number.

@@ -1352,7 +1352,7 @@

2.14. coeffs_fp_repr

  • int_width -[ro]: Integer width (accounting for the signal bit). +[ro]: Integer width.
  • frac_width diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby index 0f533240..54502139 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby @@ -51,7 +51,7 @@ memory-map: width: 32 access: ro description: | - Fixed-point signed representation of coefficients. + Fixed-point signed (2's complement) representation of coefficients. The coefficients should be aligned to the left. The fixed-point position is then given by 32 - 'int_width' (i.e. one should divide this register's content by 2**{32 - 'int_width'} to get the @@ -61,7 +61,7 @@ memory-map: name: int_width range: 4-0 description: | - Integer width (accounting for the signal bit). + Integer width. - field: name: frac_width range: 9-5 diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h index f879ec4f..8ceee227 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h @@ -37,7 +37,7 @@ representation. It should be aligned to the left. */ #define WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER 0x2000UL -/* Fixed-point signed representation of coefficients. +/* Fixed-point signed (2's complement) representation of coefficients. The coefficients should be aligned to the left. The fixed-point position is then given by 32 - 'int_width' (i.e. one should divide this register's content by 2**{32 - 'int_width'} to get the @@ -90,7 +90,7 @@ representation. It should be aligned to the left. */ uint32_t max_filt_order; - /* [0x2004]: REG (ro) Fixed-point signed representation of coefficients. + /* [0x2004]: REG (ro) Fixed-point signed (2's complement) representation of coefficients. The coefficients should be aligned to the left. The fixed-point position is then given by 32 - 'int_width' (i.e. one should divide this register's content by 2**{32 - 'int_width'} to get the diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd index d39e5943..58177e08 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd @@ -91,13 +91,13 @@ entity wb_fofb_shaper_filt_regs is max_filt_order_i : in std_logic_vector(31 downto 0); - -- Fixed-point signed representation of coefficients. + -- Fixed-point signed (2's complement) representation of coefficients. -- The coefficients should be aligned to the left. The fixed-point -- position is then given by 32 - 'int_width' (i.e. one should divide -- this register's content by 2**{32 - 'int_width'} to get the -- represented decimal number. - -- Integer width (accounting for the signal bit). + -- Integer width. coeffs_fp_repr_int_width_i : in std_logic_vector(4 downto 0); -- Fractionary width. From 403fbea2d93b5cb62faf4f3d0d97247d7430be41 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 18 Apr 2024 16:38:34 -0300 Subject: [PATCH 13/26] fofb_shaper_filt: use number of biquads to define order Instead of defining the maximum order, use a generic to define the number of internal biquads (the order is twice this value). This simplifies things since we can use it directly (i.e. no intermediate computation) for defining internal dimensions, number of iterations etc. NOTE: The ABI was broken. The register 'max_filt_order' was changed to 'num_biquads'. --- hdl/ip_cores/infra-cores | 2 +- hdl/modules/fofb_ctrl_pkg.vhd | 4 +-- .../cheby/doc/wb_fofb_shaper_filt_regs.html | 28 +++++++++---------- .../cheby/wb_fofb_shaper_filt_regs.cheby | 11 ++++---- .../cheby/wb_fofb_shaper_filt_regs.h | 22 +++++++-------- .../cheby/wb_fofb_shaper_filt_regs.vhd | 16 +++++------ .../fofb_shaper_filt/fofb_shaper_filt_pkg.vhd | 4 +-- .../fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 24 ++++++++-------- .../wb_fofb_shaper_filt_regs_consts_pkg.vhd | 4 +-- .../xwb_fofb_shaper_filt_tb.vhd | 21 +++++++------- 10 files changed, 65 insertions(+), 71 deletions(-) diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index a11f5cbb..030fc0fd 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit a11f5cbb7848939f7dd67cbee0601728450cd1d9 +Subproject commit 030fc0fdb7583a47495fcaff47a3853855d41b0a diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index d2c0cf45..cd51b441 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -774,7 +774,7 @@ package fofb_ctrl_pkg is constant c_xwb_fofb_shaper_filter_regs_sdb : t_sdb_device := ( abi_class => x"0000", -- undocumented device abi_ver_major => x"00", - abi_ver_minor => x"03", + abi_ver_minor => x"04", wbd_endian => c_sdb_endian_big, wbd_width => x"4", -- 32-bit port granularity (0100) sdb_component => ( @@ -784,7 +784,7 @@ package fofb_ctrl_pkg is vendor_id => x"1000000000001215", -- LNLS device_id => x"f65559b2", -- Last 8 chars of "FOFB_SHAPER_REGS" md5sum version => x"00000001", - date => x"20240412", + date => x"20240418", name => "FOFB_SHAPER_REGS "))); end fofb_ctrl_pkg; diff --git a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html index f44d4206..939b1fa0 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html +++ b/hdl/modules/fofb_shaper_filt/cheby/doc/wb_fofb_shaper_filt_regs.html @@ -314,9 +314,9 @@

    1. Memory map summary

- - - + + + @@ -1192,16 +1192,16 @@

2.12. ch.11.coeffs.val

representation. It should be aligned to the left. - -

2.13. max_filt_order

+ +

2.13. num_biquads

0x2000 REGmax_filt_ordermax_filt_ordermax_filt_ordernum_biquadsnum_biquadsnum_biquads
0x2004
- + - +
HW prefix:max_filt_order
HW prefix:num_biquads
HW address:0x2000
C prefix:max_filt_order
C prefix:num_biquads
C block offset:0x2000

-Maximum filter order supported by the gateware.
+The number of internal biquads each IIR filter has.

@@ -1215,7 +1215,7 @@

2.13. max_filt_order

- + @@ -1228,7 +1228,7 @@

2.13. max_filt_order

- + @@ -1241,7 +1241,7 @@

2.13. max_filt_order

- + @@ -1254,13 +1254,13 @@

2.13. max_filt_order

- +
24
max_filt_order[31:24]num_biquads[31:24]
23 16
max_filt_order[23:16]num_biquads[23:16]
15 8
max_filt_order[15:8]num_biquads[15:8]
7 0
max_filt_order[7:0]num_biquads[7:0]
  • -max_filt_order -[ro]: Maximum filter order supported by the gateware. +num_biquads +[ro]: The number of internal biquads each IIR filter has.
diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby index 54502139..00bc7ffc 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.cheby @@ -14,8 +14,7 @@ memory-map: memsize: 320 interface: sram description: | - Coefficients for the ceil('max_filt_order'/2) IIR internal - biquads. + Coefficients for the 'num_biquads' IIR internal biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: @@ -30,8 +29,8 @@ memory-map: coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the - coefficients corresponding to the first 'max_filt_order' filters - are meaningful for the gateware. + coefficients corresponding to the first 'num_biquads' biquads are + meaningful for the gateware. children: - reg: name: val @@ -41,11 +40,11 @@ memory-map: Coefficient value using 'coeffs_fp_repr' fixed-point representation. It should be aligned to the left. - reg: - name: max_filt_order + name: num_biquads width: 32 access: ro description: | - Maximum filter order supported by the gateware. + The number of internal biquads each IIR filter has. - reg: name: coeffs_fp_repr width: 32 diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h index 8ceee227..bf6b664c 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.h @@ -6,8 +6,7 @@ #define WB_FOFB_SHAPER_FILT_REGS_CH 0x0UL #define WB_FOFB_SHAPER_FILT_REGS_CH_SIZE 512 /* 0x200 */ -/* Coefficients for the ceil('max_filt_order'/2) IIR internal -biquads. +/* Coefficients for the 'num_biquads' IIR internal biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: @@ -22,8 +21,8 @@ The 'coeffs' array should be populated in the following manner: coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the -coefficients corresponding to the first 'max_filt_order' filters -are meaningful for the gateware. +coefficients corresponding to the first 'num_biquads' biquads are +meaningful for the gateware. */ #define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS 0x0UL #define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS_SIZE 4 /* 0x4 */ @@ -33,9 +32,9 @@ representation. It should be aligned to the left. */ #define WB_FOFB_SHAPER_FILT_REGS_CH_COEFFS_VAL 0x0UL -/* Maximum filter order supported by the gateware. +/* The number of internal biquads each IIR filter has. */ -#define WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER 0x2000UL +#define WB_FOFB_SHAPER_FILT_REGS_NUM_BIQUADS 0x2000UL /* Fixed-point signed (2's complement) representation of coefficients. The coefficients should be aligned to the left. The fixed-point @@ -53,8 +52,7 @@ represented decimal number. struct wb_fofb_shaper_filt_regs { /* [0x0]: REPEAT (no description) */ struct ch { - /* [0x0]: MEMORY Coefficients for the ceil('max_filt_order'/2) IIR internal -biquads. + /* [0x0]: MEMORY Coefficients for the 'num_biquads' IIR internal biquads. Each biquad takes 5 coefficients: b0, b1, b2, a1 and a2 (a0 = 1). The 'coeffs' array should be populated in the following manner: @@ -69,8 +67,8 @@ The 'coeffs' array should be populated in the following manner: coeffs[7 + 8*{biquad_idx}] = unused NOTE: This ABI supports up to 20th order filters, but only the -coefficients corresponding to the first 'max_filt_order' filters -are meaningful for the gateware. +coefficients corresponding to the first 'num_biquads' biquads are +meaningful for the gateware. */ struct coeffs { /* [0x0]: REG (rw) Coefficient value using 'coeffs_fp_repr' fixed-point @@ -86,9 +84,9 @@ representation. It should be aligned to the left. /* padding to: 0 words */ uint32_t __padding_0[512]; - /* [0x2000]: REG (ro) Maximum filter order supported by the gateware. + /* [0x2000]: REG (ro) The number of internal biquads each IIR filter has. */ - uint32_t max_filt_order; + uint32_t num_biquads; /* [0x2004]: REG (ro) Fixed-point signed (2's complement) representation of coefficients. The coefficients should be aligned to the left. The fixed-point diff --git a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd index 58177e08..2c7b24ca 100644 --- a/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd +++ b/hdl/modules/fofb_shaper_filt/cheby/wb_fofb_shaper_filt_regs.vhd @@ -1,6 +1,6 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Fri Apr 12 13:09:19 2024 by guilherme.ricioli +-- Generated on Thu Apr 18 16:32:06 2024 by guilherme.ricioli library ieee; @@ -87,9 +87,9 @@ entity wb_fofb_shaper_filt_regs is ch_11_coeffs_data_o : out std_logic_vector(31 downto 0); ch_11_coeffs_wr_o : out std_logic; - -- Maximum filter order supported by the gateware. + -- The number of internal biquads each IIR filter has. - max_filt_order_i : in std_logic_vector(31 downto 0); + num_biquads_i : in std_logic_vector(31 downto 0); -- Fixed-point signed (2's complement) representation of coefficients. -- The coefficients should be aligned to the left. The fixed-point @@ -567,7 +567,7 @@ begin end if; end process; - -- Register max_filt_order + -- Register num_biquads -- Register coeffs_fp_repr @@ -640,7 +640,7 @@ begin when "10000" => case wr_adr_d0(8 downto 2) is when "0000000" => - -- Reg max_filt_order + -- Reg num_biquads wr_ack_int <= wr_req_d0; when "0000001" => -- Reg coeffs_fp_repr @@ -662,7 +662,7 @@ begin ch_7_coeffs_data_i, ch_7_coeffs_rack, ch_8_coeffs_data_i, ch_8_coeffs_rack, ch_9_coeffs_data_i, ch_9_coeffs_rack, ch_10_coeffs_data_i, ch_10_coeffs_rack, ch_11_coeffs_data_i, - ch_11_coeffs_rack, max_filt_order_i, coeffs_fp_repr_int_width_i, + ch_11_coeffs_rack, num_biquads_i, coeffs_fp_repr_int_width_i, coeffs_fp_repr_frac_width_i) begin -- By default ack read requests rd_dat_d0 <= (others => 'X'); @@ -742,9 +742,9 @@ begin when "10000" => case adr_int(8 downto 2) is when "0000000" => - -- Reg max_filt_order + -- Reg num_biquads rd_ack_d0 <= rd_req_int; - rd_dat_d0 <= max_filt_order_i; + rd_dat_d0 <= num_biquads_i; when "0000001" => -- Reg coeffs_fp_repr rd_ack_d0 <= rd_req_int; diff --git a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd index 863c38f2..4537a824 100644 --- a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd +++ b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd @@ -26,8 +26,8 @@ LIBRARY work; USE work.wishbone_pkg.ALL; PACKAGE fofb_shaper_filt_pkg IS - -- The maximum filter order supported - CONSTANT c_MAX_FILT_ORDER : NATURAL := 8; + -- The number of internal biquads each IIR filter has + CONSTANT c_NUM_BIQUADS : NATURAL := 4; -- The signed fixed-point representation of filters' coefficients CONSTANT c_COEFF_INT_WIDTH : NATURAL := 2; diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index 0238d610..fd0ca714 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -95,8 +95,6 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS CONSTANT c_MAX_CHANNELS : NATURAL := 12; - CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; - CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_I_IFC_0s : t_wb_fofb_shaper_filt_regs_coeffs_i_ifc := (data => (OTHERS => '0')); CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s : @@ -135,18 +133,18 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS (OTHERS => c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s); SIGNAL coeffs : t_fofb_shaper_filt_coeffs(g_CHANNELS-1 DOWNTO 0)( - c_NUM_OF_BIQUADS_PER_FILT-1 DOWNTO 0)( + c_NUM_BIQUADS-1 DOWNTO 0)( b0(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), b1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), b2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), a1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), a2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH)); - SIGNAL biquad_idx : NATURAL RANGE 0 to c_NUM_OF_BIQUADS_PER_FILT-1 := 0; + SIGNAL biquad_idx : NATURAL RANGE 0 to c_NUM_BIQUADS-1 := 0; SIGNAL coeff_idx : NATURAL RANGE 0 to 4 := 0; BEGIN - ASSERT c_MAX_FILT_ORDER <= 20 - REPORT "ABI supports up to 20th order filters" + ASSERT c_NUM_BIQUADS <= 10 + REPORT "ABI supports up to 20th order filters (i.e. 10 biquads)" SEVERITY ERROR; ASSERT c_COEFF_INT_WIDTH > 1 and c_COEFF_FRAC_WIDTH > 1 and @@ -166,13 +164,13 @@ BEGIN PROCESS(clk_i) IS BEGIN - -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads and each of these - -- has 5 associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). - -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing - -- the 5*c_NUM_OF_BIQUADS_PER_FILT coefficients of each iir_filt. + -- Each iir_filt has c_NUM_BIQUADS biquads and each of these has 5 + -- associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). + -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing the + -- 5*c_NUM_BIQUADS coefficients of each iir_filt. -- -- The address map is: - -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- For biquad_idx in 0 to c_NUM_BIQUADS-1: -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} @@ -234,7 +232,7 @@ BEGIN GENERATE cmp_iir_filt : iir_filt GENERIC MAP ( - g_MAX_FILT_ORDER => c_MAX_FILT_ORDER, + g_NUM_BIQUADS => c_NUM_BIQUADS, g_X_INT_WIDTH => c_SP_WIDTH, g_X_FRAC_WIDTH => 1, -- see note below g_COEFF_INT_WIDTH => c_COEFF_INT_WIDTH, @@ -316,7 +314,7 @@ BEGIN ch_11_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(11).data, ch_11_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).data, ch_11_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).wr, - max_filt_order_i => STD_LOGIC_VECTOR(to_unsigned(c_MAX_FILT_ORDER, 32)), + num_biquads_i => STD_LOGIC_VECTOR(to_unsigned(c_NUM_BIQUADS, 32)), coeffs_fp_repr_int_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_INT_WIDTH, 5)), coeffs_fp_repr_frac_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_FRAC_WIDTH, 5)) ); diff --git a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd index ce1e79ea..723125af 100644 --- a/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd +++ b/hdl/sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd @@ -1,6 +1,6 @@ -- Do not edit. Generated by cheby 1.6.dev0 using these options: -- -i wb_fofb_shaper_filt_regs.cheby --hdl vhdl --gen-hdl wb_fofb_shaper_filt_regs.vhd --doc html --gen-doc doc/wb_fofb_shaper_filt_regs.html --gen-c wb_fofb_shaper_filt_regs.h --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_shaper_filt_regs_consts_pkg.vhd --- Generated on Fri Apr 12 13:09:19 2024 by guilherme.ricioli +-- Generated on Thu Apr 18 16:32:06 2024 by guilherme.ricioli package wb_fofb_shaper_filt_regs_consts_pkg is constant c_WB_FOFB_SHAPER_FILT_REGS_SIZE : Natural := 8200; @@ -66,7 +66,7 @@ package wb_fofb_shaper_filt_regs_consts_pkg is constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_ADDR : Natural := 16#1600#; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_SIZE : Natural := 4; constant c_WB_FOFB_SHAPER_FILT_REGS_CH_11_COEFFS_VAL_ADDR : Natural := 16#0#; - constant c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR : Natural := 16#2000#; + constant c_WB_FOFB_SHAPER_FILT_REGS_NUM_BIQUADS_ADDR : Natural := 16#2000#; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_ADDR : Natural := 16#2004#; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET : Natural := 0; constant c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET : Natural := 5; diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index a393c6f7..d9f9dcf6 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -51,7 +51,6 @@ ENTITY xwb_fofb_shaper_filt_tb IS END ENTITY xwb_fofb_shaper_filt_tb; ARCHITECTURE test OF xwb_fofb_shaper_filt_tb IS - CONSTANT c_NUM_OF_BIQUADS_PER_FILT : NATURAL := (c_MAX_FILT_ORDER + 1)/2; CONSTANT c_SYS_CLOCK_FREQ : NATURAL := 100_000_000; SIGNAL clk : STD_LOGIC := '0'; @@ -84,14 +83,14 @@ BEGIN -- Reads maximum filter order read32_pl(clk, wb_slave_i, wb_slave_o, - c_WB_FOFB_SHAPER_FILT_REGS_MAX_FILT_ORDER_ADDR, v_wb_dat); + c_WB_FOFB_SHAPER_FILT_REGS_NUM_BIQUADS_ADDR, v_wb_dat); - ASSERT to_integer(UNSIGNED(v_wb_dat)) = c_MAX_FILT_ORDER + ASSERT to_integer(UNSIGNED(v_wb_dat)) = c_NUM_BIQUADS REPORT - "UNEXPECTED MAXIMUM FILTER ORDER: " + "UNEXPECTED NUMBER OF BIQUADS: " & NATURAL'image(to_integer(UNSIGNED(v_wb_dat))) & " (EXPECTED: " - & NATURAL'image(c_MAX_FILT_ORDER) & ")" + & NATURAL'image(c_NUM_BIQUADS) & ")" SEVERITY ERROR; -- Read coefficients' fixed-point representation @@ -125,13 +124,13 @@ BEGIN & NATURAL'image(c_COEFF_FRAC_WIDTH) & ")" SEVERITY ERROR; - -- Each iir_filt has c_NUM_OF_BIQUADS_PER_FILT biquads and each of these - -- has 5 associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). - -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing - -- the 5*c_NUM_OF_BIQUADS_PER_FILT coefficients of each iir_filt. + -- Each iir_filt has c_NUM_BIQUADS biquads and each of these has 5 + -- associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). + -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing the + -- 5*c_NUM_BIQUADS coefficients of each iir_filt. -- -- The address map is: - -- For biquad_idx in 0 to c_NUM_OF_BIQUADS_PER_FILT-1: + -- For biquad_idx in 0 to c_NUM_BIQUADS-1: -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} @@ -147,7 +146,7 @@ BEGIN ch_idx*c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE; readline(fin, lin); - FOR biquad_idx IN 0 TO c_NUM_OF_BIQUADS_PER_FILT-1 + FOR biquad_idx IN 0 TO c_NUM_BIQUADS-1 LOOP FOR coeff_idx IN 0 TO 4 LOOP From b0d2d67f7e30ca06d1bb0579015e3ff8d7995d46 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Thu, 18 Apr 2024 17:14:11 -0300 Subject: [PATCH 14/26] fofb_shaper_filt: change severity from ERROR to FAILURE Critial assertions should have its severity set to FAILURE so synthesis/simulation breaks if it fails. The argument '--assert-level=error' to ghdl isn't needed anymore. --- hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 4 ++-- hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py | 2 +- .../xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd | 10 +++++----- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index fd0ca714..0b4348a5 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -145,14 +145,14 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS BEGIN ASSERT c_NUM_BIQUADS <= 10 REPORT "ABI supports up to 20th order filters (i.e. 10 biquads)" - SEVERITY ERROR; + SEVERITY FAILURE; ASSERT c_COEFF_INT_WIDTH > 1 and c_COEFF_FRAC_WIDTH > 1 and c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH <= 32 REPORT "ABI supports at most 32-bits coefficients (c_COEFF_INT_WIDTH + " & "c_COEFF_FRAC_WIDTH). Also, the SFIXED type requires each of these" & "to be at least 1." - SEVERITY ERROR; + SEVERITY FAILURE; -- NOTE: All wb_fofb_shaper_filt_regs RAM interfaces addresses are -- internally connected to same signals. So, pick just one of diff --git a/hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py b/hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py index ae0285c6..badf97ff 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py +++ b/hdl/testbench/xwb_fofb_shaper_filt/ghdl/Manifest.py @@ -8,4 +8,4 @@ top_module = "xwb_fofb_shaper_filt_tb" modules = {"local" : ["../"]} -sim_post_cmd = "ghdl -r --std=08 %s --wave=%s.ghw --assert-level=error" % (top_module, top_module) +sim_post_cmd = "ghdl -r --std=08 %s --wave=%s.ghw" % (top_module, top_module) diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index d9f9dcf6..819117e6 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -91,7 +91,7 @@ BEGIN & NATURAL'image(to_integer(UNSIGNED(v_wb_dat))) & " (EXPECTED: " & NATURAL'image(c_NUM_BIQUADS) & ")" - SEVERITY ERROR; + SEVERITY FAILURE; -- Read coefficients' fixed-point representation read32_pl(clk, wb_slave_i, wb_slave_o, @@ -108,7 +108,7 @@ BEGIN c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET)))) & " (EXPECTED: " & NATURAL'image(c_COEFF_INT_WIDTH) & ")" - SEVERITY ERROR; + SEVERITY FAILURE; -- TODO: +4 hardcoded ASSERT to_integer(UNSIGNED(v_wb_dat( @@ -122,7 +122,7 @@ BEGIN c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET)))) & " (EXPECTED: " & NATURAL'image(c_COEFF_FRAC_WIDTH) & ")" - SEVERITY ERROR; + SEVERITY FAILURE; -- Each iir_filt has c_NUM_BIQUADS biquads and each of these has 5 -- associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). @@ -173,7 +173,7 @@ BEGIN & to_hstring(v_wb_dat) & " (EXPECTED: " & to_hstring(v_wb_coeff) & ")" - SEVERITY ERROR; + SEVERITY FAILURE; v_wb_addr := v_wb_addr + c_WB_FOFB_SHAPER_FILT_REGS_CH_0_COEFFS_SIZE; END LOOP; @@ -213,7 +213,7 @@ BEGIN & INTEGER'image(to_integer(filt_sp_arr(ch_idx))) & " (EXPECTED: " & INTEGER'image(v_x_or_y) & ")" - SEVERITY ERROR; + SEVERITY FAILURE; END IF; END LOOP; END LOOP; From 8341d78bc5107fa2251b11c2e378a6a7ab5f4d95 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 19 Apr 2024 12:49:44 -0300 Subject: [PATCH 15/26] fofb_shaper_filt: move constants to the top level We used to define constants in packages for constraining dimensions of array types, which was required by VHDL standards older than 2008's. We use VHDL 2008 now, so array types can be unconstrainedly defined and these constants can be moved to the top level file. --- hdl/modules/fofb_ctrl_pkg.vhd | 3 + hdl/modules/fofb_shaper_filt/Manifest.py | 3 +- .../fofb_shaper_filt/fofb_shaper_filt_pkg.vhd | 35 ------------ .../fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 55 ++++++++++--------- .../xwb_fofb_shaper_filt_tb.vhd | 44 +++++++++------ .../afc_ref_fofb_ctrl_gen.vhd | 6 ++ 6 files changed, 68 insertions(+), 78 deletions(-) delete mode 100644 hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index cd51b441..fe5512d2 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -643,6 +643,9 @@ package fofb_ctrl_pkg is component xwb_fofb_shaper_filt is generic ( g_CHANNELS : natural; + g_NUM_BIQUADS : natural; + g_COEFF_INT_WIDTH : natural; + g_COEFF_FRAC_WIDTH : natural; g_ARITH_EXTRA_BITS : natural; g_IFCS_EXTRA_BITS : natural; g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; diff --git a/hdl/modules/fofb_shaper_filt/Manifest.py b/hdl/modules/fofb_shaper_filt/Manifest.py index f7b436ce..15a2118d 100644 --- a/hdl/modules/fofb_shaper_filt/Manifest.py +++ b/hdl/modules/fofb_shaper_filt/Manifest.py @@ -1,5 +1,4 @@ files = [ "cheby/wb_fofb_shaper_filt_regs.vhd", - "xwb_fofb_shaper_filt.vhd", - "fofb_shaper_filt_pkg.vhd" + "xwb_fofb_shaper_filt.vhd" ] diff --git a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd b/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd deleted file mode 100644 index 4537a824..00000000 --- a/hdl/modules/fofb_shaper_filt/fofb_shaper_filt_pkg.vhd +++ /dev/null @@ -1,35 +0,0 @@ --------------------------------------------------------------------------------- --- Title : FOFB shaper filters package --- Project : fofb-ctrl-gw --------------------------------------------------------------------------------- --- File : fofb_shaper_filt_pkg.vhd --- Author : Guilherme Ricioli --- Company : CNPEM, LNLS - GIE --- Platform : Generic --- Standard : VHDL'08 --------------------------------------------------------------------------------- --- Description: Package for FOFB shaper filters stuff. --------------------------------------------------------------------------------- --- Copyright (c) 2023 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 --------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2023-09-28 1.0 guilherme.ricioli Created --------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.fixed_pkg.ALL; - -LIBRARY work; -USE work.wishbone_pkg.ALL; - -PACKAGE fofb_shaper_filt_pkg IS - -- The number of internal biquads each IIR filter has - CONSTANT c_NUM_BIQUADS : NATURAL := 4; - - -- The signed fixed-point representation of filters' coefficients - CONSTANT c_COEFF_INT_WIDTH : NATURAL := 2; - CONSTANT c_COEFF_FRAC_WIDTH : NATURAL := 16; -END PACKAGE fofb_shaper_filt_pkg; diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index 0b4348a5..aaddd20e 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -27,7 +27,6 @@ USE ieee.numeric_std.ALL; LIBRARY work; USE work.ifc_common_pkg.ALL; USE work.fofb_ctrl_pkg.ALL; -USE work.fofb_shaper_filt_pkg.ALL; USE work.wishbone_pkg.ALL; ENTITY xwb_fofb_shaper_filt IS @@ -35,6 +34,12 @@ ENTITY xwb_fofb_shaper_filt IS -- Number of channels g_CHANNELS : NATURAL; + -- Number of internal biquads + -- The order is given by 2*g_NUM_BIQUADS + g_NUM_BIQUADS : NATURAL; + -- Signed fixed-point representation of biquads' coefficients + g_COEFF_INT_WIDTH : NATURAL; + g_COEFF_FRAC_WIDTH : NATURAL; -- Extra bits for biquads' internal arithmetic g_ARITH_EXTRA_BITS : NATURAL; -- Extra bits for between-biquads cascade interfaces @@ -108,8 +113,8 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS RETURN SFIXED IS BEGIN RETURN to_sfixed(wb_coeff(31 DOWNTO - 32-(c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH)), c_COEFF_INT_WIDTH-1, - -c_COEFF_FRAC_WIDTH); + 32-(g_COEFF_INT_WIDTH + g_COEFF_FRAC_WIDTH)), g_COEFF_INT_WIDTH-1, + -g_COEFF_FRAC_WIDTH); END f_parse_wb_coeff; SIGNAL iir_filts_x, iir_filts_y : t_iir_filts_x_or_y(g_CHANNELS-1 DOWNTO 0)( @@ -133,24 +138,24 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS (OTHERS => c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s); SIGNAL coeffs : t_fofb_shaper_filt_coeffs(g_CHANNELS-1 DOWNTO 0)( - c_NUM_BIQUADS-1 DOWNTO 0)( - b0(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), - b1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), - b2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), - a1(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH), - a2(c_COEFF_INT_WIDTH-1 DOWNTO -c_COEFF_FRAC_WIDTH)); - - SIGNAL biquad_idx : NATURAL RANGE 0 to c_NUM_BIQUADS-1 := 0; + g_NUM_BIQUADS-1 DOWNTO 0)( + b0(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), + b1(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), + b2(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), + a1(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), + a2(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH)); + + SIGNAL biquad_idx : NATURAL RANGE 0 to g_NUM_BIQUADS-1 := 0; SIGNAL coeff_idx : NATURAL RANGE 0 to 4 := 0; BEGIN - ASSERT c_NUM_BIQUADS <= 10 + ASSERT g_NUM_BIQUADS <= 10 REPORT "ABI supports up to 20th order filters (i.e. 10 biquads)" SEVERITY FAILURE; - ASSERT c_COEFF_INT_WIDTH > 1 and c_COEFF_FRAC_WIDTH > 1 and - c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH <= 32 - REPORT "ABI supports at most 32-bits coefficients (c_COEFF_INT_WIDTH + " & - "c_COEFF_FRAC_WIDTH). Also, the SFIXED type requires each of these" & + ASSERT g_COEFF_INT_WIDTH > 1 and g_COEFF_FRAC_WIDTH > 1 and + g_COEFF_INT_WIDTH + g_COEFF_FRAC_WIDTH <= 32 + REPORT "ABI supports at most 32-bits coefficients (g_COEFF_INT_WIDTH + " & + "g_COEFF_FRAC_WIDTH). Also, the SFIXED type requires each of these" & "to be at least 1." SEVERITY FAILURE; @@ -164,13 +169,13 @@ BEGIN PROCESS(clk_i) IS BEGIN - -- Each iir_filt has c_NUM_BIQUADS biquads and each of these has 5 + -- Each iir_filt has g_NUM_BIQUADS biquads and each of these has 5 -- associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing the - -- 5*c_NUM_BIQUADS coefficients of each iir_filt. + -- 5*g_NUM_BIQUADS coefficients of each iir_filt. -- -- The address map is: - -- For biquad_idx in 0 to c_NUM_BIQUADS-1: + -- For biquad_idx in 0 to g_NUM_BIQUADS-1: -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} @@ -232,11 +237,11 @@ BEGIN GENERATE cmp_iir_filt : iir_filt GENERIC MAP ( - g_NUM_BIQUADS => c_NUM_BIQUADS, + g_NUM_BIQUADS => g_NUM_BIQUADS, g_X_INT_WIDTH => c_SP_WIDTH, g_X_FRAC_WIDTH => 1, -- see note below - g_COEFF_INT_WIDTH => c_COEFF_INT_WIDTH, - g_COEFF_FRAC_WIDTH => c_COEFF_FRAC_WIDTH, + g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, g_Y_INT_WIDTH => c_SP_WIDTH, g_Y_FRAC_WIDTH => 1, -- see note below g_ARITH_EXTRA_BITS => g_ARITH_EXTRA_BITS, @@ -314,9 +319,9 @@ BEGIN ch_11_coeffs_data_i => wb_fofb_shaper_filt_regs_coeffs_i_ifc_arr(11).data, ch_11_coeffs_data_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).data, ch_11_coeffs_wr_o => wb_fofb_shaper_filt_regs_coeffs_o_ifc_arr(11).wr, - num_biquads_i => STD_LOGIC_VECTOR(to_unsigned(c_NUM_BIQUADS, 32)), - coeffs_fp_repr_int_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_INT_WIDTH, 5)), - coeffs_fp_repr_frac_width_i => STD_LOGIC_VECTOR(to_unsigned(c_COEFF_FRAC_WIDTH, 5)) + num_biquads_i => STD_LOGIC_VECTOR(to_unsigned(g_NUM_BIQUADS, 32)), + coeffs_fp_repr_int_width_i => STD_LOGIC_VECTOR(to_unsigned(g_COEFF_INT_WIDTH, 5)), + coeffs_fp_repr_frac_width_i => STD_LOGIC_VECTOR(to_unsigned(g_COEFF_FRAC_WIDTH, 5)) ); -- Extra Wishbone registering stage for ease timing diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index 819117e6..3f0fb33d 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -27,7 +27,6 @@ USE std.textio.ALL; LIBRARY work; USE work.fofb_ctrl_pkg.ALL; -USE work.fofb_shaper_filt_pkg.ALL; USE work.fofb_tb_pkg.ALL; USE work.sim_wishbone.ALL; USE work.wishbone_pkg.ALL; @@ -43,6 +42,12 @@ ENTITY xwb_fofb_shaper_filt_tb IS -- File containing the values for x and the expected values for y g_TEST_X_Y_FILENAME : STRING := "../fofb_shaper_filt_x_y.dat"; + -- Number of internal biquads + -- The order is given by 2*g_NUM_BIQUADS + g_NUM_BIQUADS : NATURAL := 4; + -- Signed fixed-point representation of biquads' coefficients + g_COEFF_INT_WIDTH : NATURAL := 2; + g_COEFF_FRAC_WIDTH : NATURAL := 16; -- Extra bits for biquads' internal arithmetic g_ARITH_EXTRA_BITS : NATURAL := 0; -- Extra bits for between-biquads cascade interfaces @@ -85,12 +90,12 @@ BEGIN read32_pl(clk, wb_slave_i, wb_slave_o, c_WB_FOFB_SHAPER_FILT_REGS_NUM_BIQUADS_ADDR, v_wb_dat); - ASSERT to_integer(UNSIGNED(v_wb_dat)) = c_NUM_BIQUADS + ASSERT to_integer(UNSIGNED(v_wb_dat)) = g_NUM_BIQUADS REPORT "UNEXPECTED NUMBER OF BIQUADS: " & NATURAL'image(to_integer(UNSIGNED(v_wb_dat))) & " (EXPECTED: " - & NATURAL'image(c_NUM_BIQUADS) & ")" + & NATURAL'image(g_NUM_BIQUADS) & ")" SEVERITY FAILURE; -- Read coefficients' fixed-point representation @@ -100,37 +105,37 @@ BEGIN ASSERT to_integer(UNSIGNED(v_wb_dat( c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET-1 DOWNTO c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET))) = - c_COEFF_INT_WIDTH + g_COEFF_INT_WIDTH REPORT "UNEXPECTED COEFFICIENTS' INTEGER WIDTH: " & NATURAL'image(to_integer(UNSIGNED(v_wb_dat( c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET-1 DOWNTO c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_INT_WIDTH_OFFSET)))) & " (EXPECTED: " - & NATURAL'image(c_COEFF_INT_WIDTH) & ")" + & NATURAL'image(g_COEFF_INT_WIDTH) & ")" SEVERITY FAILURE; -- TODO: +4 hardcoded ASSERT to_integer(UNSIGNED(v_wb_dat( c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET+4 DOWNTO c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET))) = - c_COEFF_FRAC_WIDTH + g_COEFF_FRAC_WIDTH REPORT "UNEXPECTED COEFFICIENTS' FRACTIONARY WIDTH: " & NATURAL'image(to_integer(UNSIGNED(v_wb_dat( c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET+4 DOWNTO c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_FP_REPR_FRAC_WIDTH_OFFSET)))) & " (EXPECTED: " - & NATURAL'image(c_COEFF_FRAC_WIDTH) & ")" + & NATURAL'image(g_COEFF_FRAC_WIDTH) & ")" SEVERITY FAILURE; - -- Each iir_filt has c_NUM_BIQUADS biquads and each of these has 5 + -- Each iir_filt has g_NUM_BIQUADS biquads and each of these has 5 -- associated coefficients (b0, b1, b2, a1 and a2 (a0 = 1)). -- wb_fofb_shaper_filt_regs uses dedicated RAM interfaces for accessing the - -- 5*c_NUM_BIQUADS coefficients of each iir_filt. + -- 5*g_NUM_BIQUADS coefficients of each iir_filt. -- -- The address map is: - -- For biquad_idx in 0 to c_NUM_BIQUADS-1: + -- For biquad_idx in 0 to g_NUM_BIQUADS-1: -- RAM address 0 + 8*{biquad_idx} = b0 of biquad {biquad_idx} -- RAM address 1 + 8*{biquad_idx} = b1 of biquad {biquad_idx} -- RAM address 2 + 8*{biquad_idx} = b2 of biquad {biquad_idx} @@ -146,18 +151,22 @@ BEGIN ch_idx*c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE; readline(fin, lin); - FOR biquad_idx IN 0 TO c_NUM_BIQUADS-1 + FOR biquad_idx IN 0 TO g_NUM_BIQUADS-1 LOOP FOR coeff_idx IN 0 TO 4 LOOP read(lin, v_coeff); -- The signed fixed-point representation of coefficients is aligned to -- the left in Wishbone registers - v_wb_coeff := ( - 31 DOWNTO 32-(c_COEFF_INT_WIDTH + c_COEFF_FRAC_WIDTH) => - to_slv(to_sfixed(v_coeff, c_COEFF_INT_WIDTH-1, - -c_COEFF_FRAC_WIDTH)), - OTHERS => '0'); + v_wb_coeff := x"00000000"; + v_wb_coeff(31 DOWNTO 32-(g_COEFF_INT_WIDTH + g_COEFF_FRAC_WIDTH)) := + to_slv(to_sfixed(v_coeff, g_COEFF_INT_WIDTH-1, + -g_COEFF_FRAC_WIDTH)); + -- v_wb_coeff := ( + -- 31 DOWNTO 32-(g_COEFF_INT_WIDTH + g_COEFF_FRAC_WIDTH) => + -- to_slv(to_sfixed(v_coeff, g_COEFF_INT_WIDTH-1, + -- -g_COEFF_FRAC_WIDTH)), + -- OTHERS => '0'); v_wb_dat := v_wb_coeff; -- Load filter coefficients @@ -228,6 +237,9 @@ BEGIN UUT : xwb_fofb_shaper_filt GENERIC MAP ( g_CHANNELS => g_CHANNELS, + g_NUM_BIQUADS => g_NUM_BIQUADS, + g_COEFF_INT_WIDTH => g_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => g_COEFF_FRAC_WIDTH, g_ARITH_EXTRA_BITS => g_ARITH_EXTRA_BITS, g_IFCS_EXTRA_BITS => g_IFCS_EXTRA_BITS, g_INTERFACE_MODE => PIPELINED, diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 166b3ddb..86b735ca 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -502,6 +502,9 @@ architecture top of afc_ref_fofb_ctrl_gen is ----------------------------------------------------------------------------- -- FOFB shaper filters signals ----------------------------------------------------------------------------- + constant c_FOFB_SHAPER_FILT_NUM_BIQUADS : natural := 4; + constant c_FOFB_SHAPER_FILT_COEFF_INT_WIDTH : natural := 2; + constant c_FOFB_SHAPER_FILT_COEFF_FRAC_WIDTH : natural := 16; constant c_FOFB_SHAPER_FILT_ARITH_EXTRA_BITS : natural := 0; constant c_FOFB_SHAPER_FILT_IFCS_EXTRA_BITS : natural := 4; @@ -1911,6 +1914,9 @@ begin cmp_xwb_fofb_shaper_filt : xwb_fofb_shaper_filt generic map ( g_CHANNELS => c_FOFB_CHANNELS, + g_NUM_BIQUADS => c_FOFB_SHAPER_FILT_NUM_BIQUADS, + g_COEFF_INT_WIDTH => c_FOFB_SHAPER_FILT_COEFF_INT_WIDTH, + g_COEFF_FRAC_WIDTH => c_FOFB_SHAPER_FILT_COEFF_FRAC_WIDTH, g_ARITH_EXTRA_BITS => c_FOFB_SHAPER_FILT_ARITH_EXTRA_BITS, g_IFCS_EXTRA_BITS => c_FOFB_SHAPER_FILT_IFCS_EXTRA_BITS, g_INTERFACE_MODE => PIPELINED, From d5361a41df8a28c72b630cf4f8e7a82128d299ca Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 19 Apr 2024 15:57:42 -0300 Subject: [PATCH 16/26] xwb_fofb_shaper_filt/nvc: add support to NVC simulator We're evaluating NVC [1] simulator. [1] https://github.com/nickg/nvc --- hdl/testbench/xwb_fofb_shaper_filt/nvc/.gitignore | 4 ++++ hdl/testbench/xwb_fofb_shaper_filt/nvc/Manifest.py | 13 +++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/nvc/.gitignore create mode 100644 hdl/testbench/xwb_fofb_shaper_filt/nvc/Manifest.py diff --git a/hdl/testbench/xwb_fofb_shaper_filt/nvc/.gitignore b/hdl/testbench/xwb_fofb_shaper_filt/nvc/.gitignore new file mode 100644 index 00000000..b4b8831b --- /dev/null +++ b/hdl/testbench/xwb_fofb_shaper_filt/nvc/.gitignore @@ -0,0 +1,4 @@ +xwb_fofb_shaper_filt_tb +xwb_fofb_shaper_filt_tb.fst +*.o +*.cf diff --git a/hdl/testbench/xwb_fofb_shaper_filt/nvc/Manifest.py b/hdl/testbench/xwb_fofb_shaper_filt/nvc/Manifest.py new file mode 100644 index 00000000..148a5a23 --- /dev/null +++ b/hdl/testbench/xwb_fofb_shaper_filt/nvc/Manifest.py @@ -0,0 +1,13 @@ +action = "simulation" +sim_tool = "nvc" +top_module = "xwb_fofb_shaper_filt_tb" +target = "xilinx" +syn_device = "xc7a200t" + +modules = {"local" : ["../"]} + +nvc_opt = "--std=2008" +nvc_analysis_opt = "--relaxed" +nvc_elab_opt = "--no-collapse" + +sim_post_cmd = "nvc -r --dump-arrays %s --wave=%s.fst --format=fst"%(top_module, top_module) From 64c5bf1b409a9f4749f265178d04ac0607b54991 Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 19 Apr 2024 16:22:58 -0300 Subject: [PATCH 17/26] fofb_ctrl_pkg.vhd: first stable release of FOFB_SHAPER_REGS' ABI --- hdl/modules/fofb_ctrl_pkg.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hdl/modules/fofb_ctrl_pkg.vhd b/hdl/modules/fofb_ctrl_pkg.vhd index fe5512d2..66ef6156 100644 --- a/hdl/modules/fofb_ctrl_pkg.vhd +++ b/hdl/modules/fofb_ctrl_pkg.vhd @@ -776,8 +776,8 @@ package fofb_ctrl_pkg is -- FOFB shaper filters constant c_xwb_fofb_shaper_filter_regs_sdb : t_sdb_device := ( abi_class => x"0000", -- undocumented device - abi_ver_major => x"00", - abi_ver_minor => x"04", + abi_ver_major => x"01", + abi_ver_minor => x"00", wbd_endian => c_sdb_endian_big, wbd_width => x"4", -- 32-bit port granularity (0100) sdb_component => ( @@ -787,7 +787,7 @@ package fofb_ctrl_pkg is vendor_id => x"1000000000001215", -- LNLS device_id => x"f65559b2", -- Last 8 chars of "FOFB_SHAPER_REGS" md5sum version => x"00000001", - date => x"20240418", + date => x"20240419", name => "FOFB_SHAPER_REGS "))); end fofb_ctrl_pkg; From 0abfd31580c4a954a9d64471e84b7e10488e1ed6 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Thu, 18 Apr 2024 10:39:50 -0300 Subject: [PATCH 18/26] Fix RTM-LAMP ADC clock constraints - clk_fast_spi is a TCl variable, so when using set_clock_groups it should be expanded with a '$'; - clk_fast_spi and clk_adcdac_ref are asynchronous between each other, remove the 'set_max_delay' commands between them; - clk_fast_spi and rtmlamp_adc_octo_sck or rtmlamp_adc_quad_sck are asynchronous between each other, remove the 'set_max_delay' commands between them; --- hdl/syn/afcv4_ref_design/afcv4_ref_fofb_ctrl.xdc | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/hdl/syn/afcv4_ref_design/afcv4_ref_fofb_ctrl.xdc b/hdl/syn/afcv4_ref_design/afcv4_ref_fofb_ctrl.xdc index a21d56e3..e8e1808e 100644 --- a/hdl/syn/afcv4_ref_design/afcv4_ref_fofb_ctrl.xdc +++ b/hdl/syn/afcv4_ref_design/afcv4_ref_fofb_ctrl.xdc @@ -71,8 +71,9 @@ set rtmlamp_adc_quad_sdoc_delay -0.144 set rtmlamp_adc_uncertainty_delay 0.020 -set_clock_groups -asynchronous -group rtmlamp_adc_octo_sck_ret -group clk_fast_spi -set_clock_groups -asynchronous -group rtmlamp_adc_quad_sck_ret -group clk_fast_spi +set_clock_groups -asynchronous -group rtmlamp_adc_octo_sck_ret +set_clock_groups -asynchronous -group rtmlamp_adc_quad_sck_ret +set_clock_groups -asynchronous -group $clk_fast_spi set_input_delay -clock rtmlamp_adc_octo_sck_ret -max [expr {$rtmlamp_adc_octo_sdoa_delay + $rtmlamp_adc_uncertainty_delay}] [get_ports rtmlamp_adc_octo_sdoa_p_i]; set_input_delay -clock rtmlamp_adc_octo_sck_ret -min [expr {$rtmlamp_adc_octo_sdoa_delay - $rtmlamp_adc_uncertainty_delay}] [get_ports rtmlamp_adc_octo_sdoa_p_i]; @@ -108,21 +109,15 @@ set_max_delay -datapath_only -from [get_clocks $clk_fast_spi] -to # Give it 1x destination clock. set_max_delay -datapath_only -from [get_clocks clk_aux] -to [get_clocks $clk_dac_master] $clk_dac_master_period set_max_delay -datapath_only -from [get_clocks $clk_adcdac_ref] -to [get_clocks $clk_dac_master] $clk_dac_master_period -# CDC for done/ready flags -set_max_delay -datapath_only -from [get_clocks $clk_adcdac_ref] -to [get_clocks $clk_fast_spi] $clk_fast_spi_period # CDC between FS clocks and Clk Aux (trigger clock) # These are using pulse_synchronizer2 which is a full feedback sync. # Give it 1x destination clock. set_max_delay -datapath_only -from [get_clocks $clk_dac_master] -to [get_clocks clk_aux] $clk_aux_period set_max_delay -datapath_only -from [get_clocks $clk_dac_master] -to [get_clocks $clk_adcdac_ref] $clk_adcdac_ref_period -# CDC for done/ready flags -set_max_delay -datapath_only -from [get_clocks $clk_fast_spi] -to [get_clocks $clk_adcdac_ref] $clk_adcdac_ref_period # Cosntraint all ADC inputs as a max delay of clk_fast_spi_period, so theier difference # are not too large -set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sck_ret_p_i] \ - -to [get_clocks $clk_fast_spi] $clk_fast_spi_period set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdoa_p_i] \ -to [get_clocks $clk_fast_spi] $clk_fast_spi_period set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdob_p_i] \ @@ -132,8 +127,6 @@ set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdo set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdod_p_i] \ -to [get_clocks $clk_fast_spi] $clk_fast_spi_period -set_max_delay -datapath_only -from [get_ports rtmlamp_adc_quad_sck_ret_p_i] \ - -to [get_clocks $clk_fast_spi] $clk_fast_spi_period set_max_delay -datapath_only -from [get_ports rtmlamp_adc_quad_sdoa_p_i] \ -to [get_clocks $clk_fast_spi] $clk_fast_spi_period set_max_delay -datapath_only -from [get_ports rtmlamp_adc_quad_sdoc_p_i] \ From 510c48315c928175c0bdf8a0e1da8c72842ca8a2 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Mon, 22 Apr 2024 16:14:11 -0300 Subject: [PATCH 19/26] Use an additional pipeline stage on the FOFB ACC gain multiplication Makes timing closure easier. --- hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 86b735ca..97a2e61f 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -92,7 +92,7 @@ generic ( -- Dot product accumulator pipeline stages g_FOFB_DOT_PROD_ACC_PIPELINE_STAGES : natural := 2; -- Gain multiplication pipeline stages - g_FOFB_ACC_GAIN_MUL_PIPELINE_STAGES : natural := 2 + g_FOFB_ACC_GAIN_MUL_PIPELINE_STAGES : natural := 3 ); port ( --------------------------------------------------------------------------- From 1d1cc893449683e9ae9dfaef12494f050fb6d02a Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 23 Apr 2024 07:58:29 -0300 Subject: [PATCH 20/26] Register the gain input before multiplying This should lead to a more efficient DSP inference, possibly fixing some time closures problems. Also register the inputs of dot_prod. --- .../fofb_processing/fofb_processing_channel.vhd | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/hdl/modules/fofb_processing/fofb_processing_channel.vhd b/hdl/modules/fofb_processing/fofb_processing_channel.vhd index f55a322a..bb76843a 100644 --- a/hdl/modules/fofb_processing/fofb_processing_channel.vhd +++ b/hdl/modules/fofb_processing/fofb_processing_channel.vhd @@ -197,10 +197,6 @@ begin - g_COEFF_FRAC_WIDTH - 1)); - -- Cast gain_i to fixed point, assume the integer and fractionary parts to be - -- g_GAIN_INT_WIDTH and g_GAIN_FRAC_WIDTH respectively - gain <= sfixed(gain_i); - -- Set-point output is the accumulator value casted to signed sp_o <= signed(to_slv(acc)); @@ -217,7 +213,7 @@ begin g_B_INT_WIDTH => g_BPM_POS_INT_WIDTH, g_B_FRAC_WIDTH => g_BPM_POS_FRAC_WIDTH, g_ACC_EXTRA_WIDTH => g_DOT_PROD_ACC_EXTRA_WIDTH, - g_REG_INPUTS => false, + g_REG_INPUTS => true, g_MULT_PIPELINE_STAGES => g_DOT_PROD_MUL_PIPELINE_STAGES, g_ACC_PIPELINE_STAGES => g_DOT_PROD_ACC_PIPELINE_STAGES ) @@ -249,6 +245,11 @@ begin sp_filtered <= (others => '0'); sp_filtered_samples <= 0; else + + -- Cast gain_i to fixed point, assume the integer and fractionary parts to be + -- g_GAIN_INT_WIDTH and g_GAIN_FRAC_WIDTH respectively + gain <= sfixed(gain_i); + -- Delay 1 clock cycle to wait for the RAM data dot_prod_valid <= bpm_pos_err_valid_i; bpm_pos_err_fp <= sfixed(bpm_pos_err_i); From 755e43e75d4448d3a0dc0b145f0538eb07d85156 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Mon, 22 Apr 2024 07:47:55 -0300 Subject: [PATCH 21/26] Update DCC and infra-cores submodules, optimize timing further Update CommsCtrlFPGA and infra-cores submodules to include the updated xci IP cores for Vivado 2022.2, add the ExtraTimingOpt flag to make timing closure possible. --- hdl/ip_cores/CommsCtrlFPGA | 2 +- hdl/ip_cores/infra-cores | 2 +- hdl/syn/afcv4_ref_design/Manifest.py | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hdl/ip_cores/CommsCtrlFPGA b/hdl/ip_cores/CommsCtrlFPGA index 56bf6e65..73f76db4 160000 --- a/hdl/ip_cores/CommsCtrlFPGA +++ b/hdl/ip_cores/CommsCtrlFPGA @@ -1 +1 @@ -Subproject commit 56bf6e653ff04b7620f8d2737f0fa950f4b666db +Subproject commit 73f76db43af853e0b1bf976499a761fb29d07f1e diff --git a/hdl/ip_cores/infra-cores b/hdl/ip_cores/infra-cores index 030fc0fd..71d42147 160000 --- a/hdl/ip_cores/infra-cores +++ b/hdl/ip_cores/infra-cores @@ -1 +1 @@ -Subproject commit 030fc0fdb7583a47495fcaff47a3853855d41b0a +Subproject commit 71d421471a945fb57cca8a39c737cd7c82da4738 diff --git a/hdl/syn/afcv4_ref_design/Manifest.py b/hdl/syn/afcv4_ref_design/Manifest.py index 433a8a73..33d65090 100644 --- a/hdl/syn/afcv4_ref_design/Manifest.py +++ b/hdl/syn/afcv4_ref_design/Manifest.py @@ -23,6 +23,7 @@ ["steps.phys_opt_design.args.directive", "Explore"], ["steps.phys_opt_design.args.more options", "-verbose"], ["steps.phys_opt_design.is_enabled", "1"], + ["steps.place_design.args.directive", "ExtraTimingOpt"], ["steps.post_route_phys_opt_design.args.directive", "Explore"], ["steps.post_route_phys_opt_design.args.more options", "-verbose"], ["steps.post_route_phys_opt_design.is_enabled", "1"], From bb6eaf34ca8b8e1dbf225ece55a246bc97e4f128 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 7 May 2024 16:44:02 -0300 Subject: [PATCH 22/26] Remove support for AFCv3 boards These synthesis targets are not updated since a long time, we don't use them anymore. Remove them. --- hdl/syn/afcv3_ref_design/Manifest.py | 68 --- hdl/syn/afcv3_ref_design/afc.pins | 391 -------------- .../afcv3_ref_design/afcv3_fmc_4sfp+_caen.xdc | 100 ---- hdl/syn/afcv3_ref_design/afcv3_pins.xlsx | Bin 57661 -> 0 bytes .../afcv3_ref_design/afcv3_ref_fofb_ctrl.xdc | 179 ------- .../afcv3_ref_design/afcv3_rtm_lamp_ohwr.xdc | 82 --- .../afcv3_ref_design/build_bitstream_local.sh | 11 - .../build_bitstream_remote.sh | 11 - .../afcv3_ref_design/build_synthesis_sdb.sh | 17 - hdl/syn/afcv3_ref_design/commands.tcl | 2 - hdl/syn/afcv3_ref_design/fmc-4sfp+-caen.pins | 72 --- hdl/syn/afcv3_ref_design/rtm-lamp-ohwr.pins | 78 --- hdl/syn/afcv3_ref_design/xdcgen.py | 250 --------- hdl/syn/afcv3_rtm_sfp_design/Manifest.py | 64 --- hdl/syn/afcv3_rtm_sfp_design/afc.pins | 363 ------------- .../afc_rtm_8sfp+_ohwr.xdc | 61 --- hdl/syn/afcv3_rtm_sfp_design/afcv3_pins.xlsx | Bin 57661 -> 0 bytes .../afcv3_rtm_sfp_fofb_ctrl.xdc | 31 -- .../build_bitstream_local.sh | 11 - .../build_bitstream_remote.sh | 11 - .../build_synthesis_sdb.sh | 17 - hdl/syn/afcv3_rtm_sfp_design/commands.tcl | 2 - .../afcv3_rtm_sfp_design/rtm-8sfp+-ohwr.pins | 85 ---- hdl/syn/afcv3_rtm_sfp_design/xdcgen.py | 250 --------- hdl/syn/generate-all-bits.sh | 10 - hdl/top/afcv3_ref_design/Manifest.py | 9 - .../afcv3_ref_design/afcv3_ref_fofb_ctrl.vhd | 478 ------------------ hdl/top/afcv3_rtm_sfp_design/Manifest.py | 9 - .../afcv3_rtm_sfp_fofb_ctrl.vhd | 443 ---------------- 29 files changed, 3105 deletions(-) delete mode 100644 hdl/syn/afcv3_ref_design/Manifest.py delete mode 100644 hdl/syn/afcv3_ref_design/afc.pins delete mode 100644 hdl/syn/afcv3_ref_design/afcv3_fmc_4sfp+_caen.xdc delete mode 100755 hdl/syn/afcv3_ref_design/afcv3_pins.xlsx delete mode 100644 hdl/syn/afcv3_ref_design/afcv3_ref_fofb_ctrl.xdc delete mode 100644 hdl/syn/afcv3_ref_design/afcv3_rtm_lamp_ohwr.xdc delete mode 100755 hdl/syn/afcv3_ref_design/build_bitstream_local.sh delete mode 100755 hdl/syn/afcv3_ref_design/build_bitstream_remote.sh delete mode 100755 hdl/syn/afcv3_ref_design/build_synthesis_sdb.sh delete mode 100644 hdl/syn/afcv3_ref_design/commands.tcl delete mode 100644 hdl/syn/afcv3_ref_design/fmc-4sfp+-caen.pins delete mode 100644 hdl/syn/afcv3_ref_design/rtm-lamp-ohwr.pins delete mode 100755 hdl/syn/afcv3_ref_design/xdcgen.py delete mode 100644 hdl/syn/afcv3_rtm_sfp_design/Manifest.py delete mode 100644 hdl/syn/afcv3_rtm_sfp_design/afc.pins delete mode 100644 hdl/syn/afcv3_rtm_sfp_design/afc_rtm_8sfp+_ohwr.xdc delete mode 100755 hdl/syn/afcv3_rtm_sfp_design/afcv3_pins.xlsx delete mode 100644 hdl/syn/afcv3_rtm_sfp_design/afcv3_rtm_sfp_fofb_ctrl.xdc delete mode 100755 hdl/syn/afcv3_rtm_sfp_design/build_bitstream_local.sh delete mode 100755 hdl/syn/afcv3_rtm_sfp_design/build_bitstream_remote.sh delete mode 100755 hdl/syn/afcv3_rtm_sfp_design/build_synthesis_sdb.sh delete mode 100644 hdl/syn/afcv3_rtm_sfp_design/commands.tcl delete mode 100644 hdl/syn/afcv3_rtm_sfp_design/rtm-8sfp+-ohwr.pins delete mode 100755 hdl/syn/afcv3_rtm_sfp_design/xdcgen.py delete mode 100755 hdl/syn/generate-all-bits.sh delete mode 100644 hdl/top/afcv3_ref_design/Manifest.py delete mode 100644 hdl/top/afcv3_ref_design/afcv3_ref_fofb_ctrl.vhd delete mode 100644 hdl/top/afcv3_rtm_sfp_design/Manifest.py delete mode 100644 hdl/top/afcv3_rtm_sfp_design/afcv3_rtm_sfp_fofb_ctrl.vhd diff --git a/hdl/syn/afcv3_ref_design/Manifest.py b/hdl/syn/afcv3_ref_design/Manifest.py deleted file mode 100644 index 7ecb757f..00000000 --- a/hdl/syn/afcv3_ref_design/Manifest.py +++ /dev/null @@ -1,68 +0,0 @@ -target = "xilinx" -action = "synthesis" - -language = "vhdl" - -# Allow the user to override fetchto using: -# hdlmake -p "fetchto='xxx'" -if locals().get('fetchto', None) is None: - fetchto = "../../ip_cores" - -syn_device = "xc7a200t" -syn_grade = "-2" -syn_package = "ffg1156" -syn_top = "afcv3_ref_fofb_ctrl" -syn_project = "afcv3_ref_fofb_ctrl" -syn_tool = "vivado" -syn_properties = [ - ["steps.synth_design.args.more options", "-verbose"], - ["steps.synth_design.args.retiming", "1"], - ["steps.synth_design.args.assert", "1"], - ["steps.opt_design.args.verbose", "1"], - ["steps.opt_design.is_enabled", "1"], - ["steps.phys_opt_design.args.directive", "Explore"], - ["steps.phys_opt_design.args.more options", "-verbose"], - ["steps.phys_opt_design.is_enabled", "1"], - ["steps.post_route_phys_opt_design.args.directive", "Explore"], - ["steps.post_route_phys_opt_design.args.more options", "-verbose"], - ["steps.post_route_phys_opt_design.is_enabled", "1"], - ["steps.write_bitstream.args.verbose", "1"] -] - -board = "afcv3" - -# For appending the afc_ref_design.xdc to synthesis -afc_base_xdc = ['acq'] - -files = [] - -import os -import sys -if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files.append("synthesis_descriptor_pkg.vhd") -else: - sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") - -# TCL commands file -files.append("commands.tcl") - -# Pass more XDC to afc-gw so it will merge it last with -# other .xdc. We need this as we depend on variables defined -# on afc_base xdc files. -xdc_files =[ - "afcv3_fmc_4sfp+_caen.xdc", - "afcv3_rtm_lamp_ohwr.xdc", - "../afc_common/afc_fmc_4sfp_gts.xdc", - "../afc_common/afc_p2p_gts.xdc", - "afcv3_ref_fofb_ctrl.xdc", -] - -additional_xdc = [] -for f in xdc_files: - additional_xdc.append(os.path.abspath(f)) - -modules = { - "local" : [ - "../../top/afcv3_ref_design", - ] -} diff --git a/hdl/syn/afcv3_ref_design/afc.pins b/hdl/syn/afcv3_ref_design/afc.pins deleted file mode 100644 index 2d004dab..00000000 --- a/hdl/syn/afcv3_ref_design/afc.pins +++ /dev/null @@ -1,391 +0,0 @@ -# -# Carrier FMC pins description file -# -# Syntax: -# carrier carrier_name number_of_fmc_slots -# pin FMC_Slot signal_name FPGA_pin - -carrier afc-v3 2 - -pin 0 la_p28 T8 -pin 0 la_n26 T2 -pin 0 la_p32 R1 -pin 0 la_n32 P1 -pin 0 la_p33 U2 -pin 0 la_n33 U1 -pin 0 ha_n12 G34 -pin 0 ha_p13 K25 -pin 0 ha_p12 H33 -pin 0 la_n13 G9 -pin 0 la_p13 G10 -pin 0 la_n09 J3 -pin 0 la_p14 H9 -pin 0 la_n14 H8 -pin 0 la_p15 K11 -pin 0 la_n15 J11 -pin 0 la_p09 J4 -# Conflicts with RTM -# pin 0 clk0m2c_p H16 -# pin 0 clk0m2c_n G16 -pin 0 la_p30 N1 -pin 0 la_n30 M1 -pin 0 la_p31 U7 -pin 0 la_n31 U6 -pin 0 la_p27 R3 -pin 0 la_n27 R2 -pin 0 la_n28 T7 -pin 0 la_p06 L5 -pin 0 la_p10 H2 -pin 0 la_n10 G2 -pin 0 la_n06 K5 -pin 0 la_n16 L9 -pin 0 la_p16 L10 -pin 0 la_p26 T3 -pin 0 la_p17 T5 -pin 0 la_n17 T4 -pin 0 la_p24 M11 -pin 0 la_n24 M10 -pin 0 la_p25 N8 -pin 0 la_n25 N7 -pin 0 la_p21 M7 -pin 0 la_n21 M6 -pin 0 la_p22 M5 -pin 0 la_n22 M4 -pin 0 la_n23 N2 -pin 0 la_n19 U4 -pin 0 la_n18 P3 -pin 0 la_p23 N3 -pin 0 la_n20 P10 -pin 0 la_p19 U5 -pin 0 la_p18 P4 -pin 0 la_p20 R10 -pin 0 la_p29 P9 -pin 0 la_n29 P8 -pin 0 ha_p17 J28 -pin 0 ha_p10 H32 -pin 0 ha_p11 M25 -pin 0 ha_n10 G32 -pin 0 ha_n11 L25 -pin 0 ha_p15 G29 -pin 0 ha_p14 M24 -pin 0 ha_n15 G30 -pin 0 ha_n14 L24 -pin 0 ha_n18 G27 -pin 0 ha_p18 H27 -pin 0 ha_n19 G26 -pin 0 ha_p21 G24 -pin 0 ha_p22 J24 -pin 0 ha_n21 G25 -pin 0 ha_p23 K23 -pin 0 ha_n22 H24 -pin 0 ha_n23 J23 -pin 0 la_p00 K7 -pin 0 la_n00 K6 -pin 0 la_p01 J6 -pin 0 la_p02 G7 -pin 0 la_n01 J5 -pin 0 la_n02 G6 -pin 0 la_n03 G1 -pin 0 la_p03 H1 -pin 0 la_n04 J1 -pin 0 la_p04 K1 -pin 0 la_n05 H3 -pin 0 la_p05 H4 -pin 0 la_n08 F2 -pin 0 la_p08 F3 -pin 0 la_n07 K2 -pin 0 la_p07 K3 -pin 0 la_n12 K8 -pin 0 la_p12 L8 -pin 0 la_p11 M2 -pin 0 la_n11 L2 -pin 0 ha_p01 L28 -pin 0 ha_n00 H29 -pin 0 ha_p00 J29 -pin 0 ha_n05 H34 -pin 0 ha_p05 J33 -pin 0 ha_n04 L34 -pin 0 ha_p04 L33 -pin 0 ha_n09 J31 -pin 0 ha_p09 K31 -pin 0 ha_n03 J30 -pin 0 ha_p03 K30 -pin 0 ha_p08 L29 -pin 0 ha_p02 K33 -pin 0 ha_p07 L32 -pin 0 ha_n02 J34 -pin 0 ha_p06 L27 -pin 0 ha_n07 K32 -pin 0 ha_n06 K27 -# Conflicts with RTM -# -# # RX116_3_N MGTPRXN3_116 E17 -# # RX116_3_P MGTPRXP3_116 F17 -# pin 0 dp3_m2c_n E17 -# pin 0 dp3_m2c_p F17 -# # RX116_2_N MGTPRXN2_116 C16 -# # RX116_2_P MGTPRXP2_116 D16 -# pin 0 dp2_m2c_n C16 -# pin 0 dp2_m2c_p D16 -# # RX116_1_N MGTPRXN1_116 E15 -# # RX116_1_P MGTPRXP1_116 F15 -# pin 0 dp1_m2c_n E15 -# pin 0 dp1_m2c_p F15 -# # RX116_0_N MGTPRXN0_116 E13 -# # RX116_0_P MGTPRXP0_116 F13 -# pin 0 dp0_m2c_n E13 -# pin 0 dp0_m2c_p F13 -# # TX116_3_N MGTPTXN3_116 A17 -# # TX116_3_P MGTPTXP3_116 B17 -# pin 0 dp3_c2m_n A17 -# pin 0 dp3_c2m_p B17 -# # TX116_2_N MGTPTXN2_116 A15 -# # TX116_2_P MGTPTXP2_116 B15 -# pin 0 dp2_c2m_n A15 -# pin 0 dp2_c2m_p B15 -# # TX116_1_N MGTPTXN1_116 C14 -# # TX116_1_P MGTPTXP1_116 D14 -# pin 0 dp1_c2m_n C14 -# pin 0 dp1_c2m_p D14 -# # TX116_0_N MGTPTXN0_116 A13 -# # TX116_0_P MGTPTXP0_116 B13 -# pin 0 dp0_c2m_n A13 -# pin 0 dp0_c2m_p B13 - -pin 1 la_p17 AB31 -pin 1 la_n17 AB32 -pin 1 la_p24 Y32 -pin 1 la_n24 Y33 -pin 1 la_p25 AA29 -pin 1 la_n25 AB29 -pin 1 la_p21 AA32 -pin 1 la_n21 AA33 -pin 1 la_p22 AA24 -pin 1 la_n22 AA25 -pin 1 la_n23 Y25 -pin 1 la_n19 AB27 -pin 1 la_n18 W31 -pin 1 la_p23 W25 -pin 1 la_n20 AB25 -pin 1 la_p19 AB26 -pin 1 la_p18 W30 -pin 1 la_p20 AB24 -pin 1 la_p29 AC33 -pin 1 la_n29 AC34 -pin 1 la_p30 W33 -pin 1 la_n30 W34 -pin 1 ha_p17 AJ28 -pin 1 ha_p10 AP25 -pin 1 ha_p11 AK33 -pin 1 ha_n10 AP26 -pin 1 ha_n11 AL33 -pin 1 ha_p15 AJ29 -pin 1 ha_p14 AN34 -pin 1 ha_n15 AK30 -pin 1 ha_n14 AP34 -pin 1 ha_n18 AP33 -pin 1 ha_p18 AN33 -pin 1 ha_n19 AK31 -pin 1 ha_p21 AP29 -pin 1 ha_p22 AL34 -pin 1 ha_n21 AP30 -pin 1 ha_p23 AJ33 -pin 1 ha_n22 AM34 -pin 1 ha_n23 AJ34 -pin 1 la_p00 AE28 -pin 1 la_n00 AF28 -pin 1 la_p01 AF29 -pin 1 la_p02 AG31 -pin 1 la_n01 AF30 -pin 1 la_n02 AH31 -pin 1 la_n03 AH24 -pin 1 la_p03 AG24 -pin 1 la_n04 AC27 -pin 1 la_p04 AC26 -pin 1 la_n05 AH34 -pin 1 la_p05 AH33 -pin 1 la_n08 AE25 -pin 1 la_p08 AD25 -pin 1 la_n07 AH27 -pin 1 la_p07 AG27 -pin 1 la_n12 AF27 -pin 1 la_p12 AE27 -pin 1 la_p11 AD30 -pin 1 la_n11 AE30 -pin 1 ha_p01 AL28 -pin 1 ha_n00 AM30 -pin 1 ha_p00 AL30 -pin 1 ha_n05 AM25 -pin 1 ha_p05 AL25 -pin 1 ha_n04 AK25 -pin 1 ha_p04 AJ25 -pin 1 ha_n09 AK26 -pin 1 ha_p09 AJ26 -pin 1 ha_n03 AN26 -pin 1 ha_p03 AM26 -pin 1 ha_p08 AM27 -pin 1 ha_p02 AN31 -pin 1 ha_p07 AM31 -pin 1 ha_n02 AP31 -pin 1 ha_p06 AL32 -pin 1 ha_n07 AN32 -pin 1 ha_n06 AM32 -pin 1 la_p28 W28 -pin 1 la_n26 AC32 -pin 1 la_p32 AA34 -pin 1 la_n32 AB34 -pin 1 la_p33 V33 -pin 1 la_n33 V34 -pin 1 ha_n12 AN29 -pin 1 ha_p13 AN28 -pin 1 ha_p12 AM29 -pin 1 la_n13 AG34 -pin 1 la_p13 AF34 -pin 1 la_n09 AG25 -pin 1 la_p14 AE33 -pin 1 la_n14 AF33 -pin 1 la_p15 AD28 -pin 1 la_n15 AD29 -pin 1 la_p09 AF25 -# Conflicts with RTM -# -# pin 1 clk0m2c_p AG20 -# pin 1 clk0m2c_n AH20 -pin 1 la_p31 V31 -pin 1 la_n31 V32 -pin 1 la_p27 AA27 -pin 1 la_n27 AA28 -pin 1 la_n28 W29 -pin 1 la_p06 AE23 -pin 1 la_p10 AG32 -pin 1 la_n10 AH32 -pin 1 la_n06 AF23 -pin 1 la_n16 AD34 -pin 1 la_p16 AD33 -pin 1 la_p26 AC31 -# Conflicts with RTM -# -# # RX213_3_P MGTPRXP3_213 AJ21 -# # RX213_3_N MGTPRXN3_213 AK21 -# pin 1 dp3_m2c_p AJ21 -# pin 1 dp3_m2c_n AK21 -# # RX213_2_P MGTPRXP2_213 AL20 -# # RX213_2_N MGTPRXN2_213 AM20 -# pin 1 dp2_m2c_p AL20 -# pin 1 dp2_m2c_n AM20 -# # RX213_1_P MGTPRXP1_213 AJ19 -# # RX213_1_N MGTPRXN1_213 AK19 -# pin 1 dp1_m2c_p AJ19 -# pin 1 dp1_m2c_n AK19 -# # RX213_0_P MGTPRXP0_213 AL18 -# # RX213_0_N MGTPRXN0_213 AM18 -# pin 1 dp0_m2c_p AL18 -# pin 1 dp0_m2c_n AM18 -# # TX213_3_P MGTPTXP3_213 AN23 -# # TX213_3_N MGTPTXN3_213 AP23 -# pin 1 dp3_c2m_p AN23 -# pin 1 dp3_c2m_n AP23 -# # TX213_2_P MGTPTXP2_213 AL22 -# # TX213_2_N MGTPTXN2_213 AM22 -# pin 1 dp2_c2m_p AL22 -# pin 1 dp2_c2m_n AM22 -# # TX213_1_PMGTPTXP1_213 AN21 -# # TX213_1_NMGTPTXN1_213 AP21 -# pin 1 dp1_c2m_p AN21 -# pin 1 dp1_c2m_n AP21 -# # TX213_0_P MGTPTXP0_213 AN19 -# # TX213_0_N MGTPTXN0_213 AP19 -# pin 1 dp0_c2m_p AN19 -# pin 1 dp0_c2m_n AP19 - -# RTM connections - -# Not connected to FPGA -# pin 0 j1_b3 -# pin 0 j1_a3 -pin 0 j1_c9 U11 -pin 0 j1_c8 AA8 -pin 0 j1_c7 W6 -pin 0 j1_c6 L23 -pin 0 j1_a7 AC11 - -pin 0 j1_a8 AN7 -pin 0 j1_f5 K12 -pin 0 j1_e5 L12 -pin 0 j1_f8 AD24 -pin 0 j1_e8 AC24 - -pin 0 j1_f10 AE26 -pin 0 j1_e10 AD26 -pin 0 j1_f9 AE31 -pin 0 j1_e9 AD31 -pin 0 j1_f7 T10 -pin 0 j1_e7 U10 -pin 0 j1_f6 T9 -pin 0 j1_e6 U9 - -pin 0 j1_c5 M26 -pin 0 j1_c6 L23 - -# Not connected to FPGA -# pin 0 j1_d6 XXX -# pin 0 j1_d7 XXX -# pin 0 j1_d8 XXX -# pin 0 j1_d9 XXX - -pin 0 j1_a9 AN6 -pin 0 j1_c10 R8 - -# Not connected to FPGA -# pin 0 j1_d3 -# pin 0 j1_c3 - -pin 0 j2_b9 AH20 -pin 0 j2_a9 AG20 -pin 0 j2_b5 G16 -pin 0 j2_a5 H16 - -pin 0 j2_a1 L4 -pin 0 j2_a2 AE32 - -pin 0 j2_d10 AM18 -pin 0 j2_c10 AL18 -pin 0 j2_d9 AK19 -pin 0 j2_c9 AJ19 -pin 0 j2_d8 AM20 -pin 0 j2_c8 AL20 -pin 0 j2_d7 AK21 -pin 0 j2_c7 AJ21 -pin 0 j2_d6 E17 -pin 0 j2_c6 F17 -pin 0 j2_d5 E13 -pin 0 j2_c5 F13 -pin 0 j2_d4 E15 -pin 0 j2_c4 F15 -pin 0 j2_d3 C16 -pin 0 j2_c3 D16 - -pin 0 j2_f10 AP19 -pin 0 j2_e10 AN19 -pin 0 j2_f9 AP21 -pin 0 j2_e9 AN21 -pin 0 j2_f8 AM22 -pin 0 j2_e8 AL22 -pin 0 j2_f7 AP23 -pin 0 j2_e7 AN23 -pin 0 j2_f6 A17 -pin 0 j2_e6 B17 -pin 0 j2_f5 A13 -pin 0 j2_e5 B13 -pin 0 j2_f4 C14 -pin 0 j2_e4 D14 -pin 0 j2_f3 A15 -pin 0 j2_e3 B15 - -pin 0 j2_c2 Y26 -pin 0 j2_c1 AC28 - -pin 0 j2_e2 AF10 -pin 0 j2_e1 T32 - -#eof diff --git a/hdl/syn/afcv3_ref_design/afcv3_fmc_4sfp+_caen.xdc b/hdl/syn/afcv3_ref_design/afcv3_fmc_4sfp+_caen.xdc deleted file mode 100644 index bd605d68..00000000 --- a/hdl/syn/afcv3_ref_design/afcv3_fmc_4sfp+_caen.xdc +++ /dev/null @@ -1,100 +0,0 @@ - - - - - - - - -# - -# This section has been generated automatically by xdcgen.py. Do not hand-modify if not really necessary. -# Command used: ./xdcgen.py -c afc-v3 -m 0:fmc-4sfp+-caen-v1 afc_fmc_4sfp+_caen.xdc -# xdcgen pin assignments for mezzanine fmc-4sfp+-caen-v1 slot 0 -set_property PACKAGE_PIN F17 [get_ports fmc0_sfp_rx_p_i[0]] -set_property PACKAGE_PIN E17 [get_ports fmc0_sfp_rx_n_i[0]] -set_property PACKAGE_PIN F15 [get_ports fmc0_sfp_rx_p_i[1]] -set_property PACKAGE_PIN E15 [get_ports fmc0_sfp_rx_n_i[1]] -set_property PACKAGE_PIN F13 [get_ports fmc0_sfp_rx_p_i[2]] -set_property PACKAGE_PIN E13 [get_ports fmc0_sfp_rx_n_i[2]] -set_property PACKAGE_PIN D16 [get_ports fmc0_sfp_rx_p_i[3]] -set_property PACKAGE_PIN C16 [get_ports fmc0_sfp_rx_n_i[3]] -set_property PACKAGE_PIN B17 [get_ports fmc0_sfp_tx_p_o[0]] -set_property PACKAGE_PIN A17 [get_ports fmc0_sfp_tx_n_o[0]] -set_property PACKAGE_PIN D14 [get_ports fmc0_sfp_tx_p_o[1]] -set_property PACKAGE_PIN C14 [get_ports fmc0_sfp_tx_n_o[1]] -set_property PACKAGE_PIN B13 [get_ports fmc0_sfp_tx_p_o[2]] -set_property PACKAGE_PIN A13 [get_ports fmc0_sfp_tx_n_o[2]] -set_property PACKAGE_PIN B15 [get_ports fmc0_sfp_tx_p_o[3]] -set_property PACKAGE_PIN A15 [get_ports fmc0_sfp_tx_n_o[3]] -set_property PACKAGE_PIN M7 [get_ports fmc0_sfp_scl_b[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_scl_b[0]] -set_property PACKAGE_PIN M6 [get_ports fmc0_sfp_sda_b[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_sda_b[0]] -set_property PACKAGE_PIN M5 [get_ports fmc0_sfp_scl_b[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_scl_b[1]] -set_property PACKAGE_PIN M4 [get_ports fmc0_sfp_sda_b[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_sda_b[1]] -set_property PACKAGE_PIN M11 [get_ports fmc0_sfp_scl_b[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_scl_b[2]] -set_property PACKAGE_PIN M10 [get_ports fmc0_sfp_sda_b[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_sda_b[2]] -set_property PACKAGE_PIN N3 [get_ports fmc0_sfp_scl_b[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_scl_b[3]] -set_property PACKAGE_PIN N2 [get_ports fmc0_sfp_sda_b[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_sda_b[3]] -set_property PACKAGE_PIN K2 [get_ports fmc0_sfp_mod_abs_i[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_mod_abs_i[0]] -set_property PACKAGE_PIN K3 [get_ports fmc0_sfp_mod_abs_i[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_mod_abs_i[1]] -set_property PACKAGE_PIN K5 [get_ports fmc0_sfp_mod_abs_i[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_mod_abs_i[2]] -set_property PACKAGE_PIN L5 [get_ports fmc0_sfp_mod_abs_i[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_mod_abs_i[3]] -set_property PACKAGE_PIN H3 [get_ports fmc0_sfp_rx_los_i[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rx_los_i[0]] -set_property PACKAGE_PIN H4 [get_ports fmc0_sfp_rx_los_i[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rx_los_i[1]] -set_property PACKAGE_PIN J1 [get_ports fmc0_sfp_rx_los_i[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rx_los_i[2]] -set_property PACKAGE_PIN K1 [get_ports fmc0_sfp_rx_los_i[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rx_los_i[3]] -set_property PACKAGE_PIN J3 [get_ports fmc0_sfp_tx_disable_o[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_disable_o[0]] -set_property PACKAGE_PIN J4 [get_ports fmc0_sfp_tx_disable_o[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_disable_o[1]] -set_property PACKAGE_PIN F2 [get_ports fmc0_sfp_tx_disable_o[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_disable_o[2]] -set_property PACKAGE_PIN F3 [get_ports fmc0_sfp_tx_disable_o[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_disable_o[3]] -set_property PACKAGE_PIN G1 [get_ports fmc0_sfp_tx_fault_i[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_fault_i[0]] -set_property PACKAGE_PIN H1 [get_ports fmc0_sfp_tx_fault_i[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_fault_i[1]] -set_property PACKAGE_PIN G6 [get_ports fmc0_sfp_tx_fault_i[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_fault_i[2]] -set_property PACKAGE_PIN G7 [get_ports fmc0_sfp_tx_fault_i[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_tx_fault_i[3]] -set_property PACKAGE_PIN L2 [get_ports fmc0_sfp_rs0_o[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs0_o[0]] -set_property PACKAGE_PIN M2 [get_ports fmc0_sfp_rs0_o[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs0_o[1]] -set_property PACKAGE_PIN G2 [get_ports fmc0_sfp_rs0_o[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs0_o[2]] -set_property PACKAGE_PIN H2 [get_ports fmc0_sfp_rs0_o[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs0_o[3]] -set_property PACKAGE_PIN G9 [get_ports fmc0_sfp_rs1_o[0]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs1_o[0]] -set_property PACKAGE_PIN G10 [get_ports fmc0_sfp_rs1_o[1]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs1_o[1]] -set_property PACKAGE_PIN K8 [get_ports fmc0_sfp_rs1_o[2]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs1_o[2]] -set_property PACKAGE_PIN L8 [get_ports fmc0_sfp_rs1_o[3]] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_sfp_rs1_o[3]] -set_property PACKAGE_PIN H16 [get_ports fmc0_si570_clk_p_i] -set_property PACKAGE_PIN G16 [get_ports fmc0_si570_clk_n_i] -set_property PACKAGE_PIN N8 [get_ports fmc0_si570_scl_b] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_si570_scl_b] -set_property PACKAGE_PIN N7 [get_ports fmc0_si570_sda_b] -set_property IOSTANDARD LVCMOS25 [get_ports fmc0_si570_sda_b] -# diff --git a/hdl/syn/afcv3_ref_design/afcv3_pins.xlsx b/hdl/syn/afcv3_ref_design/afcv3_pins.xlsx deleted file mode 100755 index 6f6ada1994f5cca6911384093298979dc9796168..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 57661 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a/hdl/syn/afcv3_ref_design/afcv3_ref_fofb_ctrl.xdc +++ /dev/null @@ -1,179 +0,0 @@ -####################################################################### -## Artix 7 AMC V3 ## -####################################################################### -# -####################################################################### -## Clocks ## -####################################################################### - -# Octo return clock -create_clock -period 10.000 -name rtmlamp_adc_octo_sck_ret [get_ports rtmlamp_adc_octo_sck_ret_p_i] -set rtmlamp_adc_octo_sck_ret_clk_period [get_property PERIOD [get_clocks rtmlamp_adc_octo_sck_ret]] -# Virtual clock for Octo return clock -create_clock -period 10.000 -name virt_rtmlamp_adc_octo_sck_ret - -# DAC clocks - -# Get master clock for DAC -set clk_dac_master [get_clocks -of_objects [get_nets -hier -filter {NAME =~ */clk_sys}]] -set clk_dac_master_period [get_property PERIOD [get_clocks $clk_dac_master]] - -# Get master clock for ADC -set clk_fast_spi [get_clocks -of_objects [get_nets -hier -filter {NAME =~ */clk_user2}]] -set clk_fast_spi_period [get_property PERIOD [get_clocks $clk_fast_spi]] - -# Get reference clocks for ADC/DAC/etc -set clk_adcdac_ref [get_clocks -of_objects [get_nets -hier -filter {NAME =~ */clk_aux_raw}]] -set clk_adcdac_ref_period [get_property PERIOD [get_clocks $clk_adcdac_ref]] - -####################################################################### -## DIFF_TERM ## -####################################################################### - -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sck_ret_n_i] -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sck_ret_p_i] - -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdoa_n_i] -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdoa_p_i] - -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdob_n_i] -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdob_p_i] - -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdoc_n_i] -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdoc_p_i] - -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdod_n_i] -set_property DIFF_TERM TRUE [get_ports rtmlamp_adc_octo_sdod_p_i] - -####################################################################### -## DELAYS ## -####################################################################### -# -# From LTC2324-16 and LTC2320-16 data sheet (page 06) -# -# SDO Data Remains Valid Delay from CLKOUT falling edge: -# tHSDO_SDR 0.00ns (min) / 1.5ns (max) -# -# So, the rising edge at 0ns generates the window from 6.5ns to 15ns, -# or, equivalently, the rising edge at -10ns generates the window from -# -3.5ns to 5ns. -# -# From Xilinx constraints guide: -# -# Center-Aligned Rising Edge Source Synchronous Inputs -# -# For a center-aligned Source Synchronous interface, the clock -# transition is aligned with the center of the data valid window. -# The same clock edge is used for launching and capturing the -# data. The constraints below rely on the default timing -# analysis (setup = 1 cycle, hold = 0 cycle). -# -# input ____ __________ -# clock |_________| |_____ -# | -# dv_bre | dv_are -# <------>|<------> -# __ ________|________ __ -# data __XXXX____Rise_Data____XXXX__ -# -# -# Input Delay Constraint -# set_input_delay -clock $input_clock -max [expr $input_clock_period - $dv_bre] [get_ports $input_ports]; -# set_input_delay -clock $input_clock -min $dv_are [get_ports $input_ports]; -# -# For our case: -# -# input ____ __________ -# clock |_________| |_____ -# | -# 3.5ns | 5ns -# <------>|<------> -# __ ________|________ __ -# data __XXXX____Rise_Data____XXXX__ -# - -# These will be ignored by a clock set_clock_groups -asynchronous, but we -# keep it here for reference. Also we sample SDO/SCK with IOB FF, so there is -# not much the tool can improve. -# -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -max 6.5 [get_ports rtmlamp_adc_octo_sdoa_p_i]; -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -min 5.0 [get_ports rtmlamp_adc_octo_sdoa_p_i]; -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -max 6.5 [get_ports rtmlamp_adc_octo_sdob_p_i]; -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -min 5.0 [get_ports rtmlamp_adc_octo_sdob_p_i]; -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -max 6.5 [get_ports rtmlamp_adc_octo_sdoc_p_i]; -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -min 5.0 [get_ports rtmlamp_adc_octo_sdoc_p_i]; -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -max 6.5 [get_ports rtmlamp_adc_octo_sdod_p_i]; -# set_input_delay -clock virt_rtmlamp_adc_octo_sck_ret -min 5.0 [get_ports rtmlamp_adc_octo_sdod_p_i]; -# -####################################################################### -## DELAY values ## -####################################################################### - -## Overrides default_delay hdl parameter for the VARIABLE mode. -## For Artix7: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps ??? - -####################################################################### -## CDC ## -####################################################################### - -# CDC FIFO between FAST SPI and CLK SYS domains -set_max_delay -datapath_only -from [get_clocks clk_sys] -to [get_clocks $clk_fast_spi] $clk_fast_spi_period -set_max_delay -datapath_only -from [get_clocks $clk_fast_spi] -to [get_clocks clk_sys] $clk_sys_period - -# CDC between Clk Aux (trigger clock) and FS clocks -# These are using pulse_synchronizer2 which is a full feedback sync. -# Give it 1x destination clock. -set_max_delay -datapath_only -from [get_clocks clk_aux] -to [get_clocks $clk_dac_master] $clk_dac_master_period -set_max_delay -datapath_only -from [get_clocks $clk_adcdac_ref] -to [get_clocks $clk_dac_master] $clk_dac_master_period -# CDC for done/ready flags -set_max_delay -datapath_only -from [get_clocks $clk_adcdac_ref] -to [get_clocks $clk_fast_spi] $clk_fast_spi_period - -# CDC between FS clocks and Clk Aux (trigger clock) -# These are using pulse_synchronizer2 which is a full feedback sync. -# Give it 1x destination clock. -set_max_delay -datapath_only -from [get_clocks $clk_dac_master] -to [get_clocks clk_aux] $clk_aux_period -set_max_delay -datapath_only -from [get_clocks $clk_dac_master] -to [get_clocks $clk_adcdac_ref] $clk_adcdac_ref_period -# CDC for done/ready flags -set_max_delay -datapath_only -from [get_clocks $clk_fast_spi] -to [get_clocks $clk_adcdac_ref] $clk_adcdac_ref_period - -# Cosntraint all ADC inputs as a max delay of clk_fast_spi_period, so theier difference -# are not too large -set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sck_ret_p_i] \ - -to [get_clocks $clk_fast_spi] $clk_fast_spi_period -set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdoa_p_i] \ - -to [get_clocks $clk_fast_spi] $clk_fast_spi_period -set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdob_p_i] \ - -to [get_clocks $clk_fast_spi] $clk_fast_spi_period -set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdoc_p_i] \ - -to [get_clocks $clk_fast_spi] $clk_fast_spi_period -set_max_delay -datapath_only -from [get_ports rtmlamp_adc_octo_sdod_p_i] \ - -to [get_clocks $clk_fast_spi] $clk_fast_spi_period - -# reset from UART. ORed with a negative reset pulse and an extension of it. -# That's why we have two sets of constraints. How to get all startpoints with -# a single set? -# -# Get all start valid startpoints from all the pins connected to the uart_rstn nets; -# filter it for leaf nodes and outputs; -# set max_delay from all those cells to all valid endpoints at the clk_fast_spi domain -set uart_rstn_startpoints [all_fanin -flat -only_cells -startpoints_only \ - [ get_pins -of_objects [ get_nets -hier -filter {NAME =~ *uart_rstn} ] -filter {IS_LEAF && (DIRECTION == "OUT")} ]] -set_max_delay -datapath_only -from [ get_cells $uart_rstn_startpoints ] -to [ get_clocks $clk_fast_spi ] $clk_sys_period - -# reset from button -set button_exted_rstn_startpoints [all_fanin -flat -only_cells -startpoints_only \ - [ get_pins -of_objects [ get_nets -hier -filter {NAME =~ *cmp_button_sys_rst/extended_int_reg*} ] -filter {IS_LEAF && (DIRECTION == "OUT")} ]] -set_max_delay -datapath_only -from [ get_cells $button_exted_rstn_startpoints ] -to [ get_clocks $clk_fast_spi ] $clk_sys_period - -set button_pp_rstn_startpoints [all_fanin -flat -only_cells -startpoints_only \ - [ get_pins -of_objects [ get_nets -hier -filter {NAME =~ *cmp_button_sys_ffs/*rst_button_sys_pp*} ] -filter {IS_LEAF && (DIRECTION == "OUT")} ]] -set_max_delay -datapath_only -from [ get_cells $button_pp_rstn_startpoints ] -to [ get_clocks $clk_fast_spi ] $clk_sys_period - -####################################################################### -## Placement Constraints ## -####################################################################### -# Constrain the PCIe core elements placement, so that it won't fail -# timing analysis. -#create_pblock GRP_pcie_core -#add_cells_to_pblock [get_pblocks GRP_pcie_core] [get_cells -hier -filter {NAME =~ *pcie_core_i/*}] -#resize_pblock [get_pblocks GRP_pcie_core] -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4} diff --git a/hdl/syn/afcv3_ref_design/afcv3_rtm_lamp_ohwr.xdc b/hdl/syn/afcv3_ref_design/afcv3_rtm_lamp_ohwr.xdc deleted file mode 100644 index 87aabec1..00000000 --- a/hdl/syn/afcv3_ref_design/afcv3_rtm_lamp_ohwr.xdc +++ /dev/null @@ -1,82 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - -# - -# This section has been generated automatically by xdcgen.py. Do not hand-modify if not really necessary. -# Command used: ./xdcgen.py -c afc-v3 -m 0:rtm-lamp-ohwr-v1 afcv3_1_rtm_lamp_ohwr.xdc -# xdcgen pin assignments for mezzanine rtm-lamp-ohwr-v1 slot 0 -set_property PACKAGE_PIN AA8 [get_ports rtmlamp_adc_cnv_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_adc_cnv_o] -set_property PACKAGE_PIN AN7 [get_ports rtmlamp_dac_ldac_n_o] -set_property IOSTANDARD LVCMOS15 [get_ports rtmlamp_dac_ldac_n_o] -set_property PACKAGE_PIN K12 [get_ports rtmlamp_adc_octo_sck_n_o] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sck_n_o] -set_property PACKAGE_PIN L12 [get_ports rtmlamp_adc_octo_sck_p_o] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sck_p_o] -set_property PACKAGE_PIN AD24 [get_ports rtmlamp_adc_octo_sck_ret_n_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sck_ret_n_i] -set_property PACKAGE_PIN AC24 [get_ports rtmlamp_adc_octo_sck_ret_p_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sck_ret_p_i] -set_property PACKAGE_PIN U11 [get_ports rtmlamp_amp_shift_clk_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_amp_shift_clk_o] -set_property PACKAGE_PIN W6 [get_ports rtmlamp_amp_shift_din_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_amp_shift_din_o] -set_property PACKAGE_PIN AC11 [get_ports rtmlamp_amp_shift_str_o] -set_property IOSTANDARD LVCMOS15 [get_ports rtmlamp_amp_shift_str_o] -set_property PACKAGE_PIN AE26 [get_ports rtmlamp_adc_octo_sdoa_n_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdoa_n_i] -set_property PACKAGE_PIN AD26 [get_ports rtmlamp_adc_octo_sdoa_p_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdoa_p_i] -set_property PACKAGE_PIN AE31 [get_ports rtmlamp_adc_octo_sdob_n_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdob_n_i] -set_property PACKAGE_PIN AD31 [get_ports rtmlamp_adc_octo_sdob_p_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdob_p_i] -set_property PACKAGE_PIN T10 [get_ports rtmlamp_adc_octo_sdoc_n_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdoc_n_i] -set_property PACKAGE_PIN U10 [get_ports rtmlamp_adc_octo_sdoc_p_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdoc_p_i] -set_property PACKAGE_PIN T9 [get_ports rtmlamp_adc_octo_sdod_n_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdod_n_i] -set_property PACKAGE_PIN U9 [get_ports rtmlamp_adc_octo_sdod_p_i] -set_property IOSTANDARD LVDS_25 [get_ports rtmlamp_adc_octo_sdod_p_i] -set_property PACKAGE_PIN M26 [get_ports rtmlamp_dac_sck_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_sck_o] -set_property PACKAGE_PIN L23 [get_ports rtmlamp_dac_cs_n_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_cs_n_o] -set_property PACKAGE_PIN AN6 [get_ports rtmlamp_dac_sdi_o[7]] -set_property IOSTANDARD LVCMOS15 [get_ports rtmlamp_dac_sdi_o[7]] -set_property PACKAGE_PIN R8 [get_ports rtmlamp_dac_sdi_o[6]] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_sdi_o[6]] -set_property PACKAGE_PIN T32 [get_ports rtmlamp_dac_sdi_o[5]] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_sdi_o[5]] -set_property PACKAGE_PIN AC28 [get_ports rtmlamp_dac_sdi_o[4]] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_sdi_o[4]] -set_property PACKAGE_PIN L4 [get_ports rtmlamp_dac_sdi_o[3]] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_sdi_o[3]] -set_property PACKAGE_PIN AF10 [get_ports rtmlamp_dac_sdi_o[2]] -set_property IOSTANDARD LVCMOS15 [get_ports rtmlamp_dac_sdi_o[2]] -set_property PACKAGE_PIN Y26 [get_ports rtmlamp_dac_sdi_o[1]] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_sdi_o[1]] -set_property PACKAGE_PIN AE32 [get_ports rtmlamp_dac_sdi_o[0]] -set_property IOSTANDARD LVCMOS25 [get_ports rtmlamp_dac_sdi_o[0]] -# diff --git a/hdl/syn/afcv3_ref_design/build_bitstream_local.sh b/hdl/syn/afcv3_ref_design/build_bitstream_local.sh deleted file mode 100755 index 047fff83..00000000 --- a/hdl/syn/afcv3_ref_design/build_bitstream_local.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afcv3_ref_design/build_bitstream_remote.sh b/hdl/syn/afcv3_ref_design/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afcv3_ref_design/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afcv3_ref_design/build_synthesis_sdb.sh b/hdl/syn/afcv3_ref_design/build_synthesis_sdb.sh deleted file mode 100755 index 5ffa0c29..00000000 --- a/hdl/syn/afcv3_ref_design/build_synthesis_sdb.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -# Maximum of 16 chars -SYNTH_INFO_PROJECT="afc_fofb_ctrl" -SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) - -SYNTH_INFO_COMMAND="../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" - -# Generate synthesis file -echo $SYNTH_INFO_COMMAND -eval $SYNTH_INFO_COMMAND diff --git a/hdl/syn/afcv3_ref_design/commands.tcl b/hdl/syn/afcv3_ref_design/commands.tcl deleted file mode 100644 index 36773b44..00000000 --- a/hdl/syn/afcv3_ref_design/commands.tcl +++ /dev/null @@ -1,2 +0,0 @@ -puts "Setting all VHDL source files file_type to VHDL 2008" -set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] diff --git a/hdl/syn/afcv3_ref_design/fmc-4sfp+-caen.pins b/hdl/syn/afcv3_ref_design/fmc-4sfp+-caen.pins deleted file mode 100644 index d06eb8d0..00000000 --- a/hdl/syn/afcv3_ref_design/fmc-4sfp+-caen.pins +++ /dev/null @@ -1,72 +0,0 @@ - -# -# Mezzanine top level pin assignment file: -# syntax: pin FMC_pin_name Core_Pin_name IO_Standard -# % is replaced with FMC number if the carrier supports more than 1 mezzanine -# - -mezzanine fmc-4sfp+-caen-v1 - -pin dp0_m2c_p fmc%_sfp_rx_p_i[0] -pin dp0_m2c_n fmc%_sfp_rx_n_i[0] -pin dp1_m2c_p fmc%_sfp_rx_p_i[1] -pin dp1_m2c_n fmc%_sfp_rx_n_i[1] -pin dp2_m2c_p fmc%_sfp_rx_p_i[2] -pin dp2_m2c_n fmc%_sfp_rx_n_i[2] -pin dp3_m2c_p fmc%_sfp_rx_p_i[3] -pin dp3_m2c_n fmc%_sfp_rx_n_i[3] - -pin dp0_c2m_p fmc%_sfp_tx_p_o[0] -pin dp0_c2m_n fmc%_sfp_tx_n_o[0] -pin dp1_c2m_p fmc%_sfp_tx_p_o[1] -pin dp1_c2m_n fmc%_sfp_tx_n_o[1] -pin dp2_c2m_p fmc%_sfp_tx_p_o[2] -pin dp2_c2m_n fmc%_sfp_tx_n_o[2] -pin dp3_c2m_p fmc%_sfp_tx_p_o[3] -pin dp3_c2m_n fmc%_sfp_tx_n_o[3] - -pin la_p21 fmc%_sfp_scl_b[0] lvcmos25 -pin la_n21 fmc%_sfp_sda_b[0] lvcmos25 -pin la_p22 fmc%_sfp_scl_b[1] lvcmos25 -pin la_n22 fmc%_sfp_sda_b[1] lvcmos25 -pin la_p24 fmc%_sfp_scl_b[2] lvcmos25 -pin la_n24 fmc%_sfp_sda_b[2] lvcmos25 -pin la_p23 fmc%_sfp_scl_b[3] lvcmos25 -pin la_n23 fmc%_sfp_sda_b[3] lvcmos25 - -pin la_n07 fmc%_sfp_mod_abs_i[0] lvcmos25 -pin la_p07 fmc%_sfp_mod_abs_i[1] lvcmos25 -pin la_n06 fmc%_sfp_mod_abs_i[2] lvcmos25 -pin la_p06 fmc%_sfp_mod_abs_i[3] lvcmos25 - -pin la_n05 fmc%_sfp_rx_los_i[0] lvcmos25 -pin la_p05 fmc%_sfp_rx_los_i[1] lvcmos25 -pin la_n04 fmc%_sfp_rx_los_i[2] lvcmos25 -pin la_p04 fmc%_sfp_rx_los_i[3] lvcmos25 - -pin la_n09 fmc%_sfp_tx_disable_o[0] lvcmos25 -pin la_p09 fmc%_sfp_tx_disable_o[1] lvcmos25 -pin la_n08 fmc%_sfp_tx_disable_o[2] lvcmos25 -pin la_p08 fmc%_sfp_tx_disable_o[3] lvcmos25 - -pin la_n03 fmc%_sfp_tx_fault_i[0] lvcmos25 -pin la_p03 fmc%_sfp_tx_fault_i[1] lvcmos25 -pin la_n02 fmc%_sfp_tx_fault_i[2] lvcmos25 -pin la_p02 fmc%_sfp_tx_fault_i[3] lvcmos25 - -pin la_n11 fmc%_sfp_rs0_o[0] lvcmos25 -pin la_p11 fmc%_sfp_rs0_o[1] lvcmos25 -pin la_n10 fmc%_sfp_rs0_o[2] lvcmos25 -pin la_p10 fmc%_sfp_rs0_o[3] lvcmos25 - -pin la_n13 fmc%_sfp_rs1_o[0] lvcmos25 -pin la_p13 fmc%_sfp_rs1_o[1] lvcmos25 -pin la_n12 fmc%_sfp_rs1_o[2] lvcmos25 -pin la_p12 fmc%_sfp_rs1_o[3] lvcmos25 - -pin clk0m2c_p fmc%_si570_clk_p_i -pin clk0m2c_n fmc%_si570_clk_n_i -pin la_p25 fmc%_si570_scl_b lvcmos25 -pin la_n25 fmc%_si570_sda_b lvcmos25 - -#eof diff --git a/hdl/syn/afcv3_ref_design/rtm-lamp-ohwr.pins b/hdl/syn/afcv3_ref_design/rtm-lamp-ohwr.pins deleted file mode 100644 index eb89595a..00000000 --- a/hdl/syn/afcv3_ref_design/rtm-lamp-ohwr.pins +++ /dev/null @@ -1,78 +0,0 @@ - -# -# Mezzanine top level pin assignment file: -# syntax: pin FMC_pin_name Core_Pin_name IO_Standard -# % is replaced with FMC number if the carrier supports more than 1 mezzanine -# - -mezzanine rtm-lamp-ohwr-v1 - -# Not connected in the carrier. Goes to clock switch. -# pin j1_b3 rtmlamp_sync_clk1_n_o lvds_33 -# pin j1_a3 rtmlamp_sync_clk1_p_o lvds_33 - -# Connected through a level translator from VADJ (2.5V) to 3.3V -pin j1_c8 rtmlamp_adc_cnv_o lvcmos25 - -# Connected through a level translator from 1.5V to 3.3V -pin j1_a8 rtmlamp_dac_ldac_n_o lvcmos15 - -pin j1_f5 rtmlamp_adc_octo_sck_n_o lvds_25 -pin j1_e5 rtmlamp_adc_octo_sck_p_o lvds_25 - -pin j1_f8 rtmlamp_adc_octo_sck_ret_n_i lvds_25 -pin j1_e8 rtmlamp_adc_octo_sck_ret_p_i lvds_25 - -# Not connected to the AFC v3.1 carrier -# pin j1_b5 rtmlamp_adc_quad_sck_n_o lvds_25 -# pin j1_a5 rtmlamp_adc_quad_sck_p_o lvds_25 -# -# pin j1_b6 rtmlamp_adc_quad_sck_ret_n_i lvds_25 -# pin j1_a6 rtmlamp_adc_quad_sck_ret_p_i lvds_25 - -# Not connected to the AFC v3.1 carrier -# Connected through a level translator from VADJ (2.5V) to 3.3V -pin j1_c9 rtmlamp_amp_shift_clk_o lvcmos25 -pin j1_c7 rtmlamp_amp_shift_din_o lvcmos25 -# pin j1_b7 rtmlamp_amp_shift_oe_o lvcmos25 -# Connected through a level translator from 1.5V to 3.3V -pin j1_a7 rtmlamp_amp_shift_str_o lvcmos15 -# pin j1_d5 rtmlamp_amp_shift_pl_o lvcmos25 -# pin j1_d10 rtmlamp_amp_shift_dout_i lvcmos25 - -pin j1_f10 rtmlamp_adc_octo_sdoa_n_i lvds_25 -pin j1_e10 rtmlamp_adc_octo_sdoa_p_i lvds_25 -pin j1_f9 rtmlamp_adc_octo_sdob_n_i lvds_25 -pin j1_e9 rtmlamp_adc_octo_sdob_p_i lvds_25 -pin j1_f7 rtmlamp_adc_octo_sdoc_n_i lvds_25 -pin j1_e7 rtmlamp_adc_octo_sdoc_p_i lvds_25 -pin j1_f6 rtmlamp_adc_octo_sdod_n_i lvds_25 -pin j1_e6 rtmlamp_adc_octo_sdod_p_i lvds_25 - -pin j1_c5 rtmlamp_dac_sck_o lvcmos25 -pin j1_c6 rtmlamp_dac_cs_n_o lvcmos25 - -# Not connected to the AFC v3.1 carrier -# pin j1_d6 rtmlamp_dac_sdi_o[11] lvcmos25 -# pin j1_d7 rtmlamp_dac_sdi_o[10] lvcmos25 -# pin j1_d8 rtmlamp_dac_sdi_o[9] lvcmos25 -# pin j1_d9 rtmlamp_dac_sdi_o[8] lvcmos25 - -# Connected through a level translator from 1.5V to 3.3V -pin j1_a9 rtmlamp_dac_sdi_o[7] lvcmos15 -pin j1_c10 rtmlamp_dac_sdi_o[6] lvcmos25 -pin j2_e1 rtmlamp_dac_sdi_o[5] lvcmos25 -pin j2_c1 rtmlamp_dac_sdi_o[4] lvcmos25 -pin j2_a1 rtmlamp_dac_sdi_o[3] lvcmos25 -# Connected through a level translator from 1.5V to 3.3V -pin j2_e2 rtmlamp_dac_sdi_o[2] lvcmos15 -pin j2_c2 rtmlamp_dac_sdi_o[1] lvcmos25 -pin j2_a2 rtmlamp_dac_sdi_o[0] lvcmos25 - -# Not connected to the AFC v3.1 carrier -# pin j2_b4 rtmlamp_adc_quad_sdoa_n_i lvds_25 -# pin j2_a4 rtmlamp_adc_quad_sdoa_p_i lvds_25 -# pin j2_b3 rtmlamp_adc_quad_sdoc_n_i lvds_25 -# pin j2_a3 rtmlamp_adc_quad_sdoc_p_i lvds_25 - -#eof diff --git a/hdl/syn/afcv3_ref_design/xdcgen.py b/hdl/syn/afcv3_ref_design/xdcgen.py deleted file mode 100755 index 7ea4ea3d..00000000 --- a/hdl/syn/afcv3_ref_design/xdcgen.py +++ /dev/null @@ -1,250 +0,0 @@ -#!/usr/bin/python - -# Modified from https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-tst/raw/dev/scripts/ucfgen.py - -import re, os - -def find_first(cond, l): - x = filter(cond, l) - if len(x): - return x[0] - else: - return None - -class MezzaninePin: - def __init__(self, fmc_line=None, port_name=None, io_standard=None): - self.fmc_line = fmc_line - self.port_name = port_name - self.io_standard = io_standard - - def parse(self, s): - self.fmc_line = s[1] - self.port_name = s[2] - self.io_standard= s[3] if len(s) > 3 else None - - def __str__(self): - return "FMC Pin: name %s port %s io %s" % ( self.fmc_line, self.port_name, self.io_standard) - -class CarrierPin: - def __init__(self, fmc_line=None, fmc_slot=None, fpga_pin=None): - self.fmc_slot = fmc_slot - self.fmc_line = fmc_line - self.fpga_pin = fpga_pin - - def parse(self, s): - self.fmc_slot = int(s[1], 10) - self.fmc_line = s[2] - self.fpga_pin = s[3] - - def __str__(self): - return "Carrier Pin: name %s slot %d pin %s" % ( self.fmc_line, self.fmc_slot, self.fpga_pin) - -class Carrier: - def __init__(self, name, num_slots): - self.name = name - self.num_slots = num_slots - self.pins = [] - - def add_pin(self, pin): - self.pins.append(pin) - -class Mezzanine: - def __init__(self, name): - self.name = name - self.pins = [] - - def add_pin(self, pin): - self.pins.append(pin) - -class XDCGen: - - desc_files_path = ["./", "./pin_defs"]; - - def __init__(self): - self.carriers = [] - self.mezzanines = [] - pass - - def load_desc_file(self, name): - lines=open(name,"r").read().splitlines() - import re - m_ncomments = re.compile("^\s*([^#]+)\s*#?.*$") - car = mez = None - for l in lines: - m=re.match(m_ncomments, l) - if not m: - continue - - tokens = m.group(1).split() - command = tokens[0] - - if(command == "carrier"): - car = Carrier(tokens[1], int(tokens[2], 10)) - elif(command == "mezzanine"): - mez = Mezzanine(tokens[1]) - elif(command == "pin"): - if(car): - p=CarrierPin() - p.parse(tokens) - car.add_pin(p) - elif(mez): - p=MezzaninePin() - p.parse(tokens) - mez.add_pin(p) - else: - raise Exception("%s: define a carrier/mezzanine before defining pins." % name) - else: - raise Exception("%s: Unrecognized command '%s'." % (name, command)) - if(car): - self.carriers.append(car) - elif(mez): - self.mezzanines.append(mez) - - def load_descs(self): - for d in self.desc_files_path: - if not os.path.isdir(d): - continue - for f in os.listdir(d): - fname=d+"/"+f - if(os.path.isfile(fname) and fname.endswith(".pins")): - self.load_desc_file(fname) -# print("Loaded %d carrier and %d mezzanine pin descriptions." % ( len(self.carriers), len(self.mezzanines))) - - def dump_descs(self): - print("Supported carriers:") - for c in self.carriers: - print("* %s" % c.name) - print("Supported mezzanines:") - for m in self.mezzanines: - print("* %s" % m.name) - - - def generate_xdc(self, xdc_filename, carrier_name, slot_mappings): - import sys - f = None - try: - f = open(xdc_filename,"r") - except: - pass - - xdc_user=[] - - if f: - xdc_lines=f.read().splitlines() - usermode = True - for l in xdc_lines: - if(l == "# "): - usermode = False - if(usermode): - xdc_user.append(l) - if (l == "# "): - usermode = True - f.close() - - car = find_first(lambda car: car.name == carrier_name, self.carriers) - if not car: - raise Exception("Unsupported carrier: %s" % carrier_name) - - - xdc_ours=[] - xdc_ours.append("") - xdc_ours.append("# ") - xdc_ours.append("") - xdc_ours.append("# This section has been generated automatically by xdcgen.py. Do not hand-modify if not really necessary.") - xdc_ours.append("# Command used: %s" % ' '.join(sys.argv)) - - slot = 0 - for mapping in slot_mappings: - if not mapping: - continue - mez = find_first(lambda mez: mez.name == mapping, self.mezzanines) - if not mez: - raise Exception("Unsupported mezzanine: %s " % mapping) - - print("Found mezzanine %s for slot %d." % (mez.name, slot)) - - if(car.num_slots > 1): - slot_str = str(slot) - else: - slot_str="" - - xdc_ours.append("# xdcgen pin assignments for mezzanine %s slot %d" % (mapping, slot)) - for p in mez.pins: - p_carrier = find_first(lambda f : f.fmc_line == p.fmc_line and f.fmc_slot == slot, car.pins) - if (not p_carrier): - raise Exception("Mezzanine FMC line %s not defined in the carrier description" % p.fmc_line) - - print(p.port_name.replace("%", slot_str)) - - xdc_ours.append("set_property PACKAGE_PIN %s [get_ports %s]" % ( p_carrier.fpga_pin, p.port_name.replace("%", slot_str) )) - if p.io_standard: - xdc_ours.append("set_property IOSTANDARD %s [get_ports %s]" % ( p.io_standard.upper(), p.port_name.replace("%", slot_str) )) - - slot=slot+1 - xdc_ours.append("# ") - - f_out = open(xdc_filename, "w") - for l in xdc_user: - f_out.write(l+"\n") - for l in xdc_ours: - f_out.write(l+"\n") - f_out.close() - - print("Successfully updated XDC file %s" % xdc_filename) - -def usage(): - import getopt, sys - print("Xdcgen, a trivial script for automatizing Xilinx XDC FMC Mezzanine-Carrier pin assignments.\n") - print("usage: %s [options] xdc_file" % sys.argv[0]) - print("Options:") - print(" -h, --help: print this message"); - print(" -c, --carrier : select carrier type"); - print(" -m, --mezzanine : select of mezzanine inserted into carrier slot "); - print(" -l, --list: list supported carriers and mezzanines"); - -def main(): - import getopt, sys, os - - if len(sys.argv) == 1: - print("Missing command line option. Type %s --help for spiritual guidance." % sys.argv[0]) - sys.exit(0) - - try: - opts, args = getopt.getopt(sys.argv[1:], "hlo:m:c:", ["help", "list", "output=", "mezzanine=slot:type", "carrier="]) - except getopt.GetoptError, err: - print str(err) - usage() - sys.exit(1) - - output = None - carrier = None - u = XDCGen() - u.desc_files_path.append(os.path.dirname(os.path.realpath(sys.argv[0]))) - u.load_descs() - mezzanines=[] - for i in range(0,128): - mezzanines.append(None) - - for o, a in opts: - if o in [ "-h", "--help" ]: - usage() - sys.exit() - elif o in ("-l", "--list"): - u.dump_descs() - sys.exit() - elif o in ("-c", "--carrier"): - carrier = a - elif o in ("-m", "--mezzanine"): - t=a.split(":") - mezzanines[int(t[0])] = t[1] - else: - assert False, "unhandled option" - - xdc_name = sys.argv[len(sys.argv)-1] - - u.generate_xdc(xdc_name, carrier, mezzanines) - -main() - - -#u.generate_xdc("svec_top.xdc", "svec-v0", [ "fmc-delay-v4", "fmc-delay-v4" ]) diff --git a/hdl/syn/afcv3_rtm_sfp_design/Manifest.py b/hdl/syn/afcv3_rtm_sfp_design/Manifest.py deleted file mode 100644 index c814802a..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/Manifest.py +++ /dev/null @@ -1,64 +0,0 @@ -target = "xilinx" -action = "synthesis" - -language = "vhdl" - -# Allow the user to override fetchto using: -# hdlmake -p "fetchto='xxx'" -if locals().get('fetchto', None) is None: - fetchto = "../../ip_cores" - -syn_device = "xc7a200t" -syn_grade = "-2" -syn_package = "ffg1156" -syn_top = "afcv3_rtm_sfp_fofb_ctrl" -syn_project = "afcv3_rtm_sfp_fofb_ctrl" -syn_tool = "vivado" -syn_properties = [ - ["steps.synth_design.args.more options", "-verbose"], - ["steps.synth_design.args.retiming", "1"], - ["steps.synth_design.args.assert", "1"], - ["steps.opt_design.args.verbose", "1"], - ["steps.opt_design.is_enabled", "1"], - ["steps.phys_opt_design.args.directive", "Explore"], - ["steps.phys_opt_design.args.more options", "-verbose"], - ["steps.phys_opt_design.is_enabled", "1"], - ["steps.write_bitstream.args.verbose", "1"] -] - -board = "afc" - -# For appending the afc_ref_design.xdc to synthesis -afc_base_xdc = ['acq'] - -files = [] - -import os -import sys -if os.path.isfile("synthesis_descriptor_pkg.vhd"): - files.append("synthesis_descriptor_pkg.vhd") -else: - sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)") - -# TCL commands file -files.append("commands.tcl") - -# Pass more XDC to afc-gw so it will merge it last with -# other .xdc. We need this as we depend on variables defined -# on afc_base xdc files. -xdc_files = [ - "afc_rtm_8sfp+_ohwr.xdc", - "afcv3_rtm_sfp_fofb_ctrl.xdc", - "../afc_common/afc_p2p_gts.xdc", - "../afc_common/afc_rtm_8sfp+_ohwr_gts.xdc", -] - -additional_xdc = [] -for f in xdc_files: - additional_xdc.append(os.path.abspath(f)) - -modules = { - "local" : [ - "../../top/afcv3_rtm_sfp_design", - ] -} diff --git a/hdl/syn/afcv3_rtm_sfp_design/afc.pins b/hdl/syn/afcv3_rtm_sfp_design/afc.pins deleted file mode 100644 index d5860b9a..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/afc.pins +++ /dev/null @@ -1,363 +0,0 @@ -# -# Carrier FMC pins description file -# -# Syntax: -# carrier carrier_name number_of_fmc_slots -# pin FMC_Slot signal_name FPGA_pin - -carrier afc-v3 2 - -pin 0 la_p28 T8 -pin 0 la_n26 T2 -pin 0 la_p32 R1 -pin 0 la_n32 P1 -pin 0 la_p33 U2 -pin 0 la_n33 U1 -pin 0 ha_n12 G34 -pin 0 ha_p13 K25 -pin 0 ha_p12 H33 -pin 0 la_n13 G9 -pin 0 la_p13 G10 -pin 0 la_n09 J3 -pin 0 la_p14 H9 -pin 0 la_n14 H8 -pin 0 la_p15 K11 -pin 0 la_n15 J11 -pin 0 la_p09 J4 -# Conflicts with RTM -# pin 0 clk0m2c_p H16 -# pin 0 clk0m2c_n G16 -pin 0 la_p30 N1 -pin 0 la_n30 M1 -pin 0 la_p31 U7 -pin 0 la_n31 U6 -pin 0 la_p27 R3 -pin 0 la_n27 R2 -pin 0 la_n28 T7 -pin 0 la_p06 L5 -pin 0 la_p10 H2 -pin 0 la_n10 G2 -pin 0 la_n06 K5 -pin 0 la_n16 L9 -pin 0 la_p16 L10 -pin 0 la_p26 T3 -pin 0 la_p17 T5 -pin 0 la_n17 T4 -pin 0 la_p24 M11 -pin 0 la_n24 M10 -pin 0 la_p25 N8 -pin 0 la_n25 N7 -pin 0 la_p21 M7 -pin 0 la_n21 M6 -pin 0 la_p22 M5 -pin 0 la_n22 M4 -pin 0 la_n23 N2 -pin 0 la_n19 U4 -pin 0 la_n18 P3 -pin 0 la_p23 N3 -pin 0 la_n20 P10 -pin 0 la_p19 U5 -pin 0 la_p18 P4 -pin 0 la_p20 R10 -pin 0 la_p29 P9 -pin 0 la_n29 P8 -pin 0 ha_p17 J28 -pin 0 ha_p10 H32 -pin 0 ha_p11 M25 -pin 0 ha_n10 G32 -pin 0 ha_n11 L25 -pin 0 ha_p15 G29 -pin 0 ha_p14 M24 -pin 0 ha_n15 G30 -pin 0 ha_n14 L24 -pin 0 ha_n18 G27 -pin 0 ha_p18 H27 -pin 0 ha_n19 G26 -pin 0 ha_p21 G24 -pin 0 ha_p22 J24 -pin 0 ha_n21 G25 -pin 0 ha_p23 K23 -pin 0 ha_n22 H24 -pin 0 ha_n23 J23 -pin 0 la_p00 K7 -pin 0 la_n00 K6 -pin 0 la_p01 J6 -pin 0 la_p02 G7 -pin 0 la_n01 J5 -pin 0 la_n02 G6 -pin 0 la_n03 G1 -pin 0 la_p03 H1 -pin 0 la_n04 J1 -pin 0 la_p04 K1 -pin 0 la_n05 H3 -pin 0 la_p05 H4 -pin 0 la_n08 F2 -pin 0 la_p08 F3 -pin 0 la_n07 K2 -pin 0 la_p07 K3 -pin 0 la_n12 K8 -pin 0 la_p12 L8 -pin 0 la_p11 M2 -pin 0 la_n11 L2 -pin 0 ha_p01 L28 -pin 0 ha_n00 H29 -pin 0 ha_p00 J29 -pin 0 ha_n05 H34 -pin 0 ha_p05 J33 -pin 0 ha_n04 L34 -pin 0 ha_p04 L33 -pin 0 ha_n09 J31 -pin 0 ha_p09 K31 -pin 0 ha_n03 J30 -pin 0 ha_p03 K30 -pin 0 ha_p08 L29 -pin 0 ha_p02 K33 -pin 0 ha_p07 L32 -pin 0 ha_n02 J34 -pin 0 ha_p06 L27 -pin 0 ha_n07 K32 -pin 0 ha_n06 K27 -# Conflicts with RTM -# -# # RX116_3_N MGTPRXN3_116 E17 -# # RX116_3_P MGTPRXP3_116 F17 -# pin 0 dp3_m2c_n E17 -# pin 0 dp3_m2c_p F17 -# # RX116_2_N MGTPRXN2_116 C16 -# # RX116_2_P MGTPRXP2_116 D16 -# pin 0 dp2_m2c_n C16 -# pin 0 dp2_m2c_p D16 -# # RX116_1_N MGTPRXN1_116 E15 -# # RX116_1_P MGTPRXP1_116 F15 -# pin 0 dp1_m2c_n E15 -# pin 0 dp1_m2c_p F15 -# # RX116_0_N MGTPRXN0_116 E13 -# # RX116_0_P MGTPRXP0_116 F13 -# pin 0 dp0_m2c_n E13 -# pin 0 dp0_m2c_p F13 -# # TX116_3_N MGTPTXN3_116 A17 -# # TX116_3_P MGTPTXP3_116 B17 -# pin 0 dp3_c2m_n A17 -# pin 0 dp3_c2m_p B17 -# # TX116_2_N MGTPTXN2_116 A15 -# # TX116_2_P MGTPTXP2_116 B15 -# pin 0 dp2_c2m_n A15 -# pin 0 dp2_c2m_p B15 -# # TX116_1_N MGTPTXN1_116 C14 -# # TX116_1_P MGTPTXP1_116 D14 -# pin 0 dp1_c2m_n C14 -# pin 0 dp1_c2m_p D14 -# # TX116_0_N MGTPTXN0_116 A13 -# # TX116_0_P MGTPTXP0_116 B13 -# pin 0 dp0_c2m_n A13 -# pin 0 dp0_c2m_p B13 - -pin 1 la_p17 AB31 -pin 1 la_n17 AB32 -pin 1 la_p24 Y32 -pin 1 la_n24 Y33 -pin 1 la_p25 AA29 -pin 1 la_n25 AB29 -pin 1 la_p21 AA32 -pin 1 la_n21 AA33 -pin 1 la_p22 AA24 -pin 1 la_n22 AA25 -pin 1 la_n23 Y25 -pin 1 la_n19 AB27 -pin 1 la_n18 W31 -pin 1 la_p23 W25 -pin 1 la_n20 AB25 -pin 1 la_p19 AB26 -pin 1 la_p18 W30 -pin 1 la_p20 AB24 -pin 1 la_p29 AC33 -pin 1 la_n29 AC34 -pin 1 la_p30 W33 -pin 1 la_n30 W34 -pin 1 ha_p17 AJ28 -pin 1 ha_p10 AP25 -pin 1 ha_p11 AK33 -pin 1 ha_n10 AP26 -pin 1 ha_n11 AL33 -pin 1 ha_p15 AJ29 -pin 1 ha_p14 AN34 -pin 1 ha_n15 AK30 -pin 1 ha_n14 AP34 -pin 1 ha_n18 AP33 -pin 1 ha_p18 AN33 -pin 1 ha_n19 AK31 -pin 1 ha_p21 AP29 -pin 1 ha_p22 AL34 -pin 1 ha_n21 AP30 -pin 1 ha_p23 AJ33 -pin 1 ha_n22 AM34 -pin 1 ha_n23 AJ34 -pin 1 la_p00 AE28 -pin 1 la_n00 AF28 -pin 1 la_p01 AF29 -pin 1 la_p02 AG31 -pin 1 la_n01 AF30 -pin 1 la_n02 AH31 -pin 1 la_n03 AH24 -pin 1 la_p03 AG24 -pin 1 la_n04 AC27 -pin 1 la_p04 AC26 -pin 1 la_n05 AH34 -pin 1 la_p05 AH33 -pin 1 la_n08 AE25 -pin 1 la_p08 AD25 -pin 1 la_n07 AH27 -pin 1 la_p07 AG27 -pin 1 la_n12 AF27 -pin 1 la_p12 AE27 -pin 1 la_p11 AD30 -pin 1 la_n11 AE30 -pin 1 ha_p01 AL28 -pin 1 ha_n00 AM30 -pin 1 ha_p00 AL30 -pin 1 ha_n05 AM25 -pin 1 ha_p05 AL25 -pin 1 ha_n04 AK25 -pin 1 ha_p04 AJ25 -pin 1 ha_n09 AK26 -pin 1 ha_p09 AJ26 -pin 1 ha_n03 AN26 -pin 1 ha_p03 AM26 -pin 1 ha_p08 AM27 -pin 1 ha_p02 AN31 -pin 1 ha_p07 AM31 -pin 1 ha_n02 AP31 -pin 1 ha_p06 AL32 -pin 1 ha_n07 AN32 -pin 1 ha_n06 AM32 -pin 1 la_p28 W28 -pin 1 la_n26 AC32 -pin 1 la_p32 AA34 -pin 1 la_n32 AB34 -pin 1 la_p33 V33 -pin 1 la_n33 V34 -pin 1 ha_n12 AN29 -pin 1 ha_p13 AN28 -pin 1 ha_p12 AM29 -pin 1 la_n13 AG34 -pin 1 la_p13 AF34 -pin 1 la_n09 AG25 -pin 1 la_p14 AE33 -pin 1 la_n14 AF33 -pin 1 la_p15 AD28 -pin 1 la_n15 AD29 -pin 1 la_p09 AF25 -# Conflicts with RTM -# -# pin 1 clk0m2c_p AG20 -# pin 1 clk0m2c_n AH20 -pin 1 la_p31 V31 -pin 1 la_n31 V32 -pin 1 la_p27 AA27 -pin 1 la_n27 AA28 -pin 1 la_n28 W29 -pin 1 la_p06 AE23 -pin 1 la_p10 AG32 -pin 1 la_n10 AH32 -pin 1 la_n06 AF23 -pin 1 la_n16 AD34 -pin 1 la_p16 AD33 -pin 1 la_p26 AC31 -# Conflicts with RTM -# -# # RX213_3_P MGTPRXP3_213 AJ21 -# # RX213_3_N MGTPRXN3_213 AK21 -# pin 1 dp3_m2c_p AJ21 -# pin 1 dp3_m2c_n AK21 -# # RX213_2_P MGTPRXP2_213 AL20 -# # RX213_2_N MGTPRXN2_213 AM20 -# pin 1 dp2_m2c_p AL20 -# pin 1 dp2_m2c_n AM20 -# # RX213_1_P MGTPRXP1_213 AJ19 -# # RX213_1_N MGTPRXN1_213 AK19 -# pin 1 dp1_m2c_p AJ19 -# pin 1 dp1_m2c_n AK19 -# # RX213_0_P MGTPRXP0_213 AL18 -# # RX213_0_N MGTPRXN0_213 AM18 -# pin 1 dp0_m2c_p AL18 -# pin 1 dp0_m2c_n AM18 -# # TX213_3_P MGTPTXP3_213 AN23 -# # TX213_3_N MGTPTXN3_213 AP23 -# pin 1 dp3_c2m_p AN23 -# pin 1 dp3_c2m_n AP23 -# # TX213_2_P MGTPTXP2_213 AL22 -# # TX213_2_N MGTPTXN2_213 AM22 -# pin 1 dp2_c2m_p AL22 -# pin 1 dp2_c2m_n AM22 -# # TX213_1_PMGTPTXP1_213 AN21 -# # TX213_1_NMGTPTXN1_213 AP21 -# pin 1 dp1_c2m_p AN21 -# pin 1 dp1_c2m_n AP21 -# # TX213_0_P MGTPTXP0_213 AN19 -# # TX213_0_N MGTPTXN0_213 AP19 -# pin 1 dp0_c2m_p AN19 -# pin 1 dp0_c2m_n AP19 - -# RTM connections - -# Not connected to FPGA -# pin 0 j6_b3 -# pin 0 j6_a3 -pin 0 j6_c10 R8 -pin 0 j6_c9 U11 -pin 0 j6_c8 AA8 -pin 0 j6_c7 W6 -pin 0 j6_c6 L23 - -# Not connected to FPGA -# pin 0 j6_d3 -# pin 0 j6_c3 - -pin 0 j2_b9 AH20 -pin 0 j2_a9 AG20 -pin 0 j2_b5 G16 -pin 0 j2_a5 H16 - -pin 0 j2_a1 L4 - -pin 0 j2_d10 AM18 -pin 0 j2_c10 AL18 -pin 0 j2_d9 AK19 -pin 0 j2_c9 AJ19 -pin 0 j2_d8 AM20 -pin 0 j2_c8 AL20 -pin 0 j2_d7 AK21 -pin 0 j2_c7 AJ21 -pin 0 j2_d6 E17 -pin 0 j2_c6 F17 -pin 0 j2_d5 E13 -pin 0 j2_c5 F13 -pin 0 j2_d4 E15 -pin 0 j2_c4 F15 -pin 0 j2_d3 C16 -pin 0 j2_c3 D16 - -pin 0 j2_f10 AP19 -pin 0 j2_e10 AN19 -pin 0 j2_f9 AP21 -pin 0 j2_e9 AN21 -pin 0 j2_f8 AM22 -pin 0 j2_e8 AL22 -pin 0 j2_f7 AP23 -pin 0 j2_e7 AN23 -pin 0 j2_f6 A17 -pin 0 j2_e6 B17 -pin 0 j2_f5 A13 -pin 0 j2_e5 B13 -pin 0 j2_f4 C14 -pin 0 j2_e4 D14 -pin 0 j2_f3 A15 -pin 0 j2_e3 B15 - -pin 0 j2_c2 Y26 -pin 0 j2_c1 AC28 - -pin 0 j2_e2 AF10 -pin 0 j2_e1 T32 - -#eof diff --git a/hdl/syn/afcv3_rtm_sfp_design/afc_rtm_8sfp+_ohwr.xdc b/hdl/syn/afcv3_rtm_sfp_design/afc_rtm_8sfp+_ohwr.xdc deleted file mode 100644 index 05aec8af..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/afc_rtm_8sfp+_ohwr.xdc +++ /dev/null @@ -1,61 +0,0 @@ - - - - - - - - - - - - - - - -# - -# This section has been generated automatically by xdcgen.py. Do not hand-modify if not really necessary. -# Command used: ./xdcgen.py -c afc-v3 -m 0:rtm-8sfp+-ohwr-v1 afc_rtm_8sfp+_ohwr.xdc -# xdcgen pin assignments for mezzanine rtm-8sfp+-ohwr-v1 slot 0 -set_property PACKAGE_PIN R8 [get_ports rtm_sfp_ctl_din_n_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_sfp_ctl_din_n_o] -set_property PACKAGE_PIN U11 [get_ports rtm_sfp_ctl_str_n_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_sfp_ctl_str_n_o] -set_property PACKAGE_PIN AA8 [get_ports rtm_sfp_status_reg_clk_n_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_sfp_status_reg_clk_n_o] -set_property PACKAGE_PIN W6 [get_ports rtm_sfp_ctl_oe_n_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_sfp_ctl_oe_n_o] -set_property PACKAGE_PIN L23 [get_ports rtm_sfp_status_reg_out_i] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_sfp_status_reg_out_i] -set_property PACKAGE_PIN AH20 [get_ports rtm_fpga_clk2_n_i] -set_property PACKAGE_PIN AG20 [get_ports rtm_fpga_clk2_p_i] -set_property PACKAGE_PIN G16 [get_ports rtm_fpga_clk1_n_i] -set_property PACKAGE_PIN H16 [get_ports rtm_fpga_clk1_p_i] -set_property PACKAGE_PIN L4 [get_ports rtm_sfp_status_reg_pl_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_sfp_status_reg_pl_o] -set_property PACKAGE_PIN E17 [get_ports rtm_sfp_rx_n_i[4]] -set_property PACKAGE_PIN F17 [get_ports rtm_sfp_rx_p_i[4]] -set_property PACKAGE_PIN E13 [get_ports rtm_sfp_rx_n_i[5]] -set_property PACKAGE_PIN F13 [get_ports rtm_sfp_rx_p_i[5]] -set_property PACKAGE_PIN E15 [get_ports rtm_sfp_rx_n_i[6]] -set_property PACKAGE_PIN F15 [get_ports rtm_sfp_rx_p_i[6]] -set_property PACKAGE_PIN C16 [get_ports rtm_sfp_rx_n_i[7]] -set_property PACKAGE_PIN D16 [get_ports rtm_sfp_rx_p_i[7]] -set_property PACKAGE_PIN A17 [get_ports rtm_sfp_tx_n_o[4]] -set_property PACKAGE_PIN B17 [get_ports rtm_sfp_tx_p_o[4]] -set_property PACKAGE_PIN A13 [get_ports rtm_sfp_tx_n_o[5]] -set_property PACKAGE_PIN B13 [get_ports rtm_sfp_tx_p_o[5]] -set_property PACKAGE_PIN C14 [get_ports rtm_sfp_tx_n_o[6]] -set_property PACKAGE_PIN D14 [get_ports rtm_sfp_tx_p_o[6]] -set_property PACKAGE_PIN A15 [get_ports rtm_sfp_tx_n_o[7]] -set_property PACKAGE_PIN B15 [get_ports rtm_sfp_tx_p_o[7]] -set_property PACKAGE_PIN Y26 [get_ports rtm_si570_oe_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_si570_oe_o] -set_property PACKAGE_PIN AC28 [get_ports rtm_clk_in_sel_o] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_clk_in_sel_o] -set_property PACKAGE_PIN AF10 [get_ports rtm_sda_b] -set_property IOSTANDARD LVCMOS15 [get_ports rtm_sda_b] -set_property PACKAGE_PIN T32 [get_ports rtm_scl_b] -set_property IOSTANDARD LVCMOS25 [get_ports rtm_scl_b] -# diff --git a/hdl/syn/afcv3_rtm_sfp_design/afcv3_pins.xlsx b/hdl/syn/afcv3_rtm_sfp_design/afcv3_pins.xlsx deleted file mode 100755 index 6f6ada1994f5cca6911384093298979dc9796168..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 57661 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a/hdl/syn/afcv3_rtm_sfp_design/afcv3_rtm_sfp_fofb_ctrl.xdc +++ /dev/null @@ -1,31 +0,0 @@ -####################################################################### -## Artix 7 AMC V3 ## -####################################################################### - -####################################################################### -## Clocks ## -####################################################################### - -####################################################################### -## DELAYS ## -####################################################################### - -####################################################################### -## DELAY values ## -####################################################################### - -## Overrides default_delay hdl parameter for the VARIABLE mode. -## For Artix7: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps ??? - -####################################################################### -## CDC ## -####################################################################### - -####################################################################### -## Placement Constraints ## -####################################################################### -# Constrain the PCIe core elements placement, so that it won't fail -# timing analysis. -#create_pblock GRP_pcie_core -#add_cells_to_pblock [get_pblocks GRP_pcie_core] [get_cells -hier -filter {NAME =~ *pcie_core_i/*}] -#resize_pblock [get_pblocks GRP_pcie_core] -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4} diff --git a/hdl/syn/afcv3_rtm_sfp_design/build_bitstream_local.sh b/hdl/syn/afcv3_rtm_sfp_design/build_bitstream_local.sh deleted file mode 100755 index 047fff83..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/build_bitstream_local.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(./build_synthesis_sdb.sh; hdlmake -a makefile; time make; date) 2>&1 | tee make_output" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afcv3_rtm_sfp_design/build_bitstream_remote.sh b/hdl/syn/afcv3_rtm_sfp_design/build_bitstream_remote.sh deleted file mode 100755 index 9846b1af..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/build_bitstream_remote.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &" - -echo $COMMAND -eval $COMMAND diff --git a/hdl/syn/afcv3_rtm_sfp_design/build_synthesis_sdb.sh b/hdl/syn/afcv3_rtm_sfp_design/build_synthesis_sdb.sh deleted file mode 100755 index 5ffa0c29..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/build_synthesis_sdb.sh +++ /dev/null @@ -1,17 +0,0 @@ -#!/bin/bash - -# Exit on error -set -e -# Check for uninitialized variables -set -u - -# Maximum of 16 chars -SYNTH_INFO_PROJECT="afc_fofb_ctrl" -SYNTH_INFO_TOOL="VIVADO" -SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2) - -SYNTH_INFO_COMMAND="../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}" - -# Generate synthesis file -echo $SYNTH_INFO_COMMAND -eval $SYNTH_INFO_COMMAND diff --git a/hdl/syn/afcv3_rtm_sfp_design/commands.tcl b/hdl/syn/afcv3_rtm_sfp_design/commands.tcl deleted file mode 100644 index 36773b44..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/commands.tcl +++ /dev/null @@ -1,2 +0,0 @@ -puts "Setting all VHDL source files file_type to VHDL 2008" -set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}] diff --git a/hdl/syn/afcv3_rtm_sfp_design/rtm-8sfp+-ohwr.pins b/hdl/syn/afcv3_rtm_sfp_design/rtm-8sfp+-ohwr.pins deleted file mode 100644 index 1b815728..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/rtm-8sfp+-ohwr.pins +++ /dev/null @@ -1,85 +0,0 @@ - -# -# Mezzanine top level pin assignment file: -# syntax: pin FMC_pin_name Core_Pin_name IO_Standard -# % is replaced with FMC number if the carrier supports more than 1 mezzanine -# - -mezzanine rtm-8sfp+-ohwr-v1 - -# Not connected in the carrier -# pin j6_b3 rtm_clk_ext_n_i lvds_33 -# pin j6_a3 rtm_clk_ext_p_i lvds_33 -# -# Connected through a level translator -# pin j6_c10 rtm_sfp_ctl_din_n_o lvcmos33 -# pin j6_c9 rtm_sfp_ctl_str_n_o lvcmos33 -# pin j6_c8 rtm_sfp_status_reg_clk_n_o lvcmos33 -# pin j6_c7 rtm_sfp_ctl_oe_n_o lvcmos33 -# pin j6_c6 rtm_sfp_status_reg_out_i lvcmos33 -pin j6_c10 rtm_sfp_ctl_din_n_o lvcmos25 -pin j6_c9 rtm_sfp_ctl_str_n_o lvcmos25 -pin j6_c8 rtm_sfp_status_reg_clk_n_o lvcmos25 -pin j6_c7 rtm_sfp_ctl_oe_n_o lvcmos25 -pin j6_c6 rtm_sfp_status_reg_out_i lvcmos25 - -# Not connected in the carrier -# pin j6_d3 rtm_sync_clk_n_o lvds_25 -# pin j6_c3 rtm_sync_clk_p_o lvds_25 - -pin j2_b9 rtm_fpga_clk2_n_i -pin j2_a9 rtm_fpga_clk2_p_i -pin j2_b5 rtm_fpga_clk1_n_i -pin j2_a5 rtm_fpga_clk1_p_i - -# Connected through a level translator -# pin j2_a1 rtm_sfp_status_reg_pl_o lvcmos33 -pin j2_a1 rtm_sfp_status_reg_pl_o lvcmos25 - -#pin j2_d10 rtm_sfp_rx_n_i[0] -#pin j2_c10 rtm_sfp_rx_p_i[0] -#pin j2_d9 rtm_sfp_rx_n_i[1] -#pin j2_c9 rtm_sfp_rx_p_i[1] -#pin j2_d8 rtm_sfp_rx_n_i[2] -#pin j2_c8 rtm_sfp_rx_p_i[2] -#pin j2_d7 rtm_sfp_rx_n_i[3] -#pin j2_c7 rtm_sfp_rx_p_i[3] -# Incompatible electrical standard with AFC when using -# the Flash SPI -pin j2_d6 rtm_sfp_rx_n_i[4] -pin j2_c6 rtm_sfp_rx_p_i[4] -pin j2_d5 rtm_sfp_rx_n_i[5] -pin j2_c5 rtm_sfp_rx_p_i[5] -pin j2_d4 rtm_sfp_rx_n_i[6] -pin j2_c4 rtm_sfp_rx_p_i[6] -pin j2_d3 rtm_sfp_rx_n_i[7] -pin j2_c3 rtm_sfp_rx_p_i[7] - -#pin j2_f10 rtm_sfp_tx_n_o[0] -#pin j2_e10 rtm_sfp_tx_p_o[0] -#pin j2_f9 rtm_sfp_tx_n_o[1] -#pin j2_e9 rtm_sfp_tx_p_o[1] -#pin j2_f8 rtm_sfp_tx_n_o[2] -#pin j2_e8 rtm_sfp_tx_p_o[2] -#pin j2_f7 rtm_sfp_tx_n_o[3] -#pin j2_e7 rtm_sfp_tx_p_o[3] -# Incompatible electrical standard with AFC when using -# the Flash SPI -pin j2_f6 rtm_sfp_tx_n_o[4] -pin j2_e6 rtm_sfp_tx_p_o[4] -pin j2_f5 rtm_sfp_tx_n_o[5] -pin j2_e5 rtm_sfp_tx_p_o[5] -pin j2_f4 rtm_sfp_tx_n_o[6] -pin j2_e4 rtm_sfp_tx_p_o[6] -pin j2_f3 rtm_sfp_tx_n_o[7] -pin j2_e3 rtm_sfp_tx_p_o[7] - -pin j2_c2 rtm_si570_oe_o lvcmos25 -pin j2_c1 rtm_clk_in_sel_o lvcmos25 - -# Connected through a level translator -# pin j2_e2 rtm_sda_b lvcmos25 -pin j2_e2 rtm_sda_b lvcmos15 -pin j2_e1 rtm_scl_b lvcmos25 - -#eof diff --git a/hdl/syn/afcv3_rtm_sfp_design/xdcgen.py b/hdl/syn/afcv3_rtm_sfp_design/xdcgen.py deleted file mode 100755 index 7ea4ea3d..00000000 --- a/hdl/syn/afcv3_rtm_sfp_design/xdcgen.py +++ /dev/null @@ -1,250 +0,0 @@ -#!/usr/bin/python - -# Modified from https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-tst/raw/dev/scripts/ucfgen.py - -import re, os - -def find_first(cond, l): - x = filter(cond, l) - if len(x): - return x[0] - else: - return None - -class MezzaninePin: - def __init__(self, fmc_line=None, port_name=None, io_standard=None): - self.fmc_line = fmc_line - self.port_name = port_name - self.io_standard = io_standard - - def parse(self, s): - self.fmc_line = s[1] - self.port_name = s[2] - self.io_standard= s[3] if len(s) > 3 else None - - def __str__(self): - return "FMC Pin: name %s port %s io %s" % ( self.fmc_line, self.port_name, self.io_standard) - -class CarrierPin: - def __init__(self, fmc_line=None, fmc_slot=None, fpga_pin=None): - self.fmc_slot = fmc_slot - self.fmc_line = fmc_line - self.fpga_pin = fpga_pin - - def parse(self, s): - self.fmc_slot = int(s[1], 10) - self.fmc_line = s[2] - self.fpga_pin = s[3] - - def __str__(self): - return "Carrier Pin: name %s slot %d pin %s" % ( self.fmc_line, self.fmc_slot, self.fpga_pin) - -class Carrier: - def __init__(self, name, num_slots): - self.name = name - self.num_slots = num_slots - self.pins = [] - - def add_pin(self, pin): - self.pins.append(pin) - -class Mezzanine: - def __init__(self, name): - self.name = name - self.pins = [] - - def add_pin(self, pin): - self.pins.append(pin) - -class XDCGen: - - desc_files_path = ["./", "./pin_defs"]; - - def __init__(self): - self.carriers = [] - self.mezzanines = [] - pass - - def load_desc_file(self, name): - lines=open(name,"r").read().splitlines() - import re - m_ncomments = re.compile("^\s*([^#]+)\s*#?.*$") - car = mez = None - for l in lines: - m=re.match(m_ncomments, l) - if not m: - continue - - tokens = m.group(1).split() - command = tokens[0] - - if(command == "carrier"): - car = Carrier(tokens[1], int(tokens[2], 10)) - elif(command == "mezzanine"): - mez = Mezzanine(tokens[1]) - elif(command == "pin"): - if(car): - p=CarrierPin() - p.parse(tokens) - car.add_pin(p) - elif(mez): - p=MezzaninePin() - p.parse(tokens) - mez.add_pin(p) - else: - raise Exception("%s: define a carrier/mezzanine before defining pins." % name) - else: - raise Exception("%s: Unrecognized command '%s'." % (name, command)) - if(car): - self.carriers.append(car) - elif(mez): - self.mezzanines.append(mez) - - def load_descs(self): - for d in self.desc_files_path: - if not os.path.isdir(d): - continue - for f in os.listdir(d): - fname=d+"/"+f - if(os.path.isfile(fname) and fname.endswith(".pins")): - self.load_desc_file(fname) -# print("Loaded %d carrier and %d mezzanine pin descriptions." % ( len(self.carriers), len(self.mezzanines))) - - def dump_descs(self): - print("Supported carriers:") - for c in self.carriers: - print("* %s" % c.name) - print("Supported mezzanines:") - for m in self.mezzanines: - print("* %s" % m.name) - - - def generate_xdc(self, xdc_filename, carrier_name, slot_mappings): - import sys - f = None - try: - f = open(xdc_filename,"r") - except: - pass - - xdc_user=[] - - if f: - xdc_lines=f.read().splitlines() - usermode = True - for l in xdc_lines: - if(l == "# "): - usermode = False - if(usermode): - xdc_user.append(l) - if (l == "# "): - usermode = True - f.close() - - car = find_first(lambda car: car.name == carrier_name, self.carriers) - if not car: - raise Exception("Unsupported carrier: %s" % carrier_name) - - - xdc_ours=[] - xdc_ours.append("") - xdc_ours.append("# ") - xdc_ours.append("") - xdc_ours.append("# This section has been generated automatically by xdcgen.py. Do not hand-modify if not really necessary.") - xdc_ours.append("# Command used: %s" % ' '.join(sys.argv)) - - slot = 0 - for mapping in slot_mappings: - if not mapping: - continue - mez = find_first(lambda mez: mez.name == mapping, self.mezzanines) - if not mez: - raise Exception("Unsupported mezzanine: %s " % mapping) - - print("Found mezzanine %s for slot %d." % (mez.name, slot)) - - if(car.num_slots > 1): - slot_str = str(slot) - else: - slot_str="" - - xdc_ours.append("# xdcgen pin assignments for mezzanine %s slot %d" % (mapping, slot)) - for p in mez.pins: - p_carrier = find_first(lambda f : f.fmc_line == p.fmc_line and f.fmc_slot == slot, car.pins) - if (not p_carrier): - raise Exception("Mezzanine FMC line %s not defined in the carrier description" % p.fmc_line) - - print(p.port_name.replace("%", slot_str)) - - xdc_ours.append("set_property PACKAGE_PIN %s [get_ports %s]" % ( p_carrier.fpga_pin, p.port_name.replace("%", slot_str) )) - if p.io_standard: - xdc_ours.append("set_property IOSTANDARD %s [get_ports %s]" % ( p.io_standard.upper(), p.port_name.replace("%", slot_str) )) - - slot=slot+1 - xdc_ours.append("# ") - - f_out = open(xdc_filename, "w") - for l in xdc_user: - f_out.write(l+"\n") - for l in xdc_ours: - f_out.write(l+"\n") - f_out.close() - - print("Successfully updated XDC file %s" % xdc_filename) - -def usage(): - import getopt, sys - print("Xdcgen, a trivial script for automatizing Xilinx XDC FMC Mezzanine-Carrier pin assignments.\n") - print("usage: %s [options] xdc_file" % sys.argv[0]) - print("Options:") - print(" -h, --help: print this message"); - print(" -c, --carrier : select carrier type"); - print(" -m, --mezzanine : select of mezzanine inserted into carrier slot "); - print(" -l, --list: list supported carriers and mezzanines"); - -def main(): - import getopt, sys, os - - if len(sys.argv) == 1: - print("Missing command line option. Type %s --help for spiritual guidance." % sys.argv[0]) - sys.exit(0) - - try: - opts, args = getopt.getopt(sys.argv[1:], "hlo:m:c:", ["help", "list", "output=", "mezzanine=slot:type", "carrier="]) - except getopt.GetoptError, err: - print str(err) - usage() - sys.exit(1) - - output = None - carrier = None - u = XDCGen() - u.desc_files_path.append(os.path.dirname(os.path.realpath(sys.argv[0]))) - u.load_descs() - mezzanines=[] - for i in range(0,128): - mezzanines.append(None) - - for o, a in opts: - if o in [ "-h", "--help" ]: - usage() - sys.exit() - elif o in ("-l", "--list"): - u.dump_descs() - sys.exit() - elif o in ("-c", "--carrier"): - carrier = a - elif o in ("-m", "--mezzanine"): - t=a.split(":") - mezzanines[int(t[0])] = t[1] - else: - assert False, "unhandled option" - - xdc_name = sys.argv[len(sys.argv)-1] - - u.generate_xdc(xdc_name, carrier, mezzanines) - -main() - - -#u.generate_xdc("svec_top.xdc", "svec-v0", [ "fmc-delay-v4", "fmc-delay-v4" ]) diff --git a/hdl/syn/generate-all-bits.sh b/hdl/syn/generate-all-bits.sh deleted file mode 100755 index be25f3cd..00000000 --- a/hdl/syn/generate-all-bits.sh +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/bash - -for target in \ - afcv3_rtm_sfp_design\ - afcv3_ref_design \ - afcv4_ref_design \ - ; do - TOP=$(pwd) - cd ${target} && hdlmake makefile && make clean && rm -rf *.sim && ./build_bitstream_local.sh ; cd ${TOP}; -done diff --git a/hdl/top/afcv3_ref_design/Manifest.py b/hdl/top/afcv3_ref_design/Manifest.py deleted file mode 100644 index aa38d5c1..00000000 --- a/hdl/top/afcv3_ref_design/Manifest.py +++ /dev/null @@ -1,9 +0,0 @@ -files = [ - "afcv3_ref_fofb_ctrl.vhd", -] - -modules = { - "local" : [ - "../afc_ref_design_gen", - ], -} diff --git a/hdl/top/afcv3_ref_design/afcv3_ref_fofb_ctrl.vhd b/hdl/top/afcv3_ref_design/afcv3_ref_fofb_ctrl.vhd deleted file mode 100644 index 6539df5b..00000000 --- a/hdl/top/afcv3_ref_design/afcv3_ref_fofb_ctrl.vhd +++ /dev/null @@ -1,478 +0,0 @@ ------------------------------------------------------------------------------- --- Title : AFC design for FOFB Controller + 1 FMC SFPs ------------------------------------------------------------------------------- --- Author : Lucas Maziero Russo --- Company : CNPEM LNLS-DIG --- Created : 2020-10-26 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: AFC design for FOFB Controller + 1 FMC SFPs -------------------------------------------------------------------------------- --- Copyright (c) 2020 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2020-10-26 1.0 lucas.russo Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Custom common cores -use work.ifc_common_pkg.all; --- Custom generic cores -use work.ifc_generic_pkg.all; --- Trigger definitions -use work.trigger_common_pkg.all; --- Trigger Modules -use work.trigger_pkg.all; --- AFC base definitions -use work.afc_base_pkg.all; --- AFC base wrappers definitions -use work.afc_base_wrappers_pkg.all; --- IP cores constants -use work.ipcores_pkg.all; --- Meta Package -use work.synthesis_descriptor_pkg.all; --- Data Acquisition core -use work.acq_core_pkg.all; --- AXI cores -use work.pcie_cntr_axi_pkg.all; --- FOFC CC wrapper -use work.fofb_ctrl_pkg.all; --- FOFC CC -use work.fofb_cc_pkg.all; - -entity afcv3_ref_fofb_ctrl is -generic ( - -- Number of P2P GTs - g_NUM_P2P_GTS : integer := 8; - -- Starting index of used P2P GTs - g_P2P_GT_START_ID : integer := 0; - -- Number of RTM LAMP channels - g_RTMLAMP_CHANNELS : natural := 8 -); -port ( - --------------------------------------------------------------------------- - -- Clocking pins - --------------------------------------------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - aux_clk_p_i : in std_logic; - aux_clk_n_i : in std_logic; - - afc_fp2_clk1_p_i : in std_logic; - afc_fp2_clk1_n_i : in std_logic; - - --------------------------------------------------------------------------- - -- Reset Button - --------------------------------------------------------------------------- - sys_rst_button_n_i : in std_logic := '1'; - - --------------------------------------------------------------------------- - -- UART pins - --------------------------------------------------------------------------- - - uart_rxd_i : in std_logic := '1'; - uart_txd_o : out std_logic; - - --------------------------------------------------------------------------- - -- Trigger pins - --------------------------------------------------------------------------- - trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0); - trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0); - - --------------------------------------------------------------------------- - -- AFC Diagnostics - --------------------------------------------------------------------------- - - diag_spi_cs_i : in std_logic := '0'; - diag_spi_si_i : in std_logic := '0'; - diag_spi_so_o : out std_logic; - diag_spi_clk_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- ADN4604ASVZ - --------------------------------------------------------------------------- - adn4604_vadj2_clk_updt_n_o : out std_logic; - - --------------------------------------------------------------------------- - -- AFC I2C. - --------------------------------------------------------------------------- - -- Si57x oscillator - afc_si57x_scl_b : inout std_logic; - afc_si57x_sda_b : inout std_logic; - - -- Si57x oscillator output enable - afc_si57x_oe_o : out std_logic; - - --------------------------------------------------------------------------- - -- PCIe pins - --------------------------------------------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0); - ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0); - ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0); - ddr3_cs_n_o : out std_logic_vector(0 downto 0); - ddr3_ras_n_o : out std_logic; - ddr3_cas_n_o : out std_logic; - ddr3_we_n_o : out std_logic; - ddr3_reset_n_o : out std_logic; - ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0); - ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0); - ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0); - ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0); - - -- PCIe transceivers - pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0); - - -- PCI clock and reset signals - pcie_clk_p_i : in std_logic; - pcie_clk_n_i : in std_logic; - - --------------------------------------------------------------------------- - -- User LEDs - --------------------------------------------------------------------------- - leds_o : out std_logic_vector(2 downto 0); - - --------------------------------------------------------------------------- - -- FMC interface - --------------------------------------------------------------------------- - - board_i2c_scl_b : inout std_logic; - board_i2c_sda_b : inout std_logic; - - --------------------------------------------------------------------------- - -- Flash memory SPI interface - --------------------------------------------------------------------------- - -- - -- spi_sclk_o : out std_logic; - -- spi_cs_n_o : out std_logic; - -- spi_mosi_o : out std_logic; - -- spi_miso_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- P2P GT pins - --------------------------------------------------------------------------- - -- P2P - p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - - --------------------------------------------------------------------------- - -- FMC slot 0 - CAEN 4 SFP+ - --------------------------------------------------------------------------- - - fmc0_sfp_rx_p_i : in std_logic_vector(3 downto 0); - fmc0_sfp_rx_n_i : in std_logic_vector(3 downto 0); - fmc0_sfp_tx_p_o : out std_logic_vector(3 downto 0); - fmc0_sfp_tx_n_o : out std_logic_vector(3 downto 0); - - fmc0_sfp_scl_b : inout std_logic_vector(3 downto 0); - fmc0_sfp_sda_b : inout std_logic_vector(3 downto 0); - fmc0_sfp_mod_abs_i : in std_logic_vector(3 downto 0); - fmc0_sfp_rx_los_i : in std_logic_vector(3 downto 0); - fmc0_sfp_tx_disable_o : out std_logic_vector(3 downto 0); - fmc0_sfp_tx_fault_i : in std_logic_vector(3 downto 0); - fmc0_sfp_rs0_o : out std_logic_vector(3 downto 0); - fmc0_sfp_rs1_o : out std_logic_vector(3 downto 0); - - fmc0_si570_clk_p_i : in std_logic; - fmc0_si570_clk_n_i : in std_logic; - fmc0_si570_scl_b : inout std_logic; - fmc0_si570_sda_b : inout std_logic; - - --------------------------------------------------------------------------- - -- FMC slot 0 management - --------------------------------------------------------------------------- - fmc0_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low) - -- fmc0_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM) - -- fmc0_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM) - - --------------------------------------------------------------------------- - -- FMC slot 1 management - --------------------------------------------------------------------------- - fmc1_prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low) - -- fmc1_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM) - -- fmc1_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM) - - --------------------------------------------------------------------------- - -- RTM LAMP board pins - --------------------------------------------------------------------------- - - --------------------------------------------------------------------------- - -- RTM ADC interface - --------------------------------------------------------------------------- - rtmlamp_adc_cnv_o : out std_logic; - - rtmlamp_adc_octo_sck_p_o : out std_logic; - rtmlamp_adc_octo_sck_n_o : out std_logic; - rtmlamp_adc_octo_sck_ret_p_i : in std_logic; - rtmlamp_adc_octo_sck_ret_n_i : in std_logic; - rtmlamp_adc_octo_sdoa_p_i : in std_logic; - rtmlamp_adc_octo_sdoa_n_i : in std_logic; - rtmlamp_adc_octo_sdob_p_i : in std_logic; - rtmlamp_adc_octo_sdob_n_i : in std_logic; - rtmlamp_adc_octo_sdoc_p_i : in std_logic; - rtmlamp_adc_octo_sdoc_n_i : in std_logic; - rtmlamp_adc_octo_sdod_p_i : in std_logic; - rtmlamp_adc_octo_sdod_n_i : in std_logic; - - -- Only for AFCv4 - -- rtmlamp_adc_quad_sck_p_o : out std_logic; - -- rtmlamp_adc_quad_sck_n_o : out std_logic; - -- rtmlamp_adc_quad_sck_ret_p_i : in std_logic := '0'; - -- rtmlamp_adc_quad_sck_ret_n_i : in std_logic := '0'; - -- rtmlamp_adc_quad_sdoa_p_i : in std_logic := '0'; - -- rtmlamp_adc_quad_sdoa_n_i : in std_logic := '0'; - -- rtmlamp_adc_quad_sdoc_p_i : in std_logic := '0'; - -- rtmlamp_adc_quad_sdoc_n_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- RTM DAC interface - --------------------------------------------------------------------------- - rtmlamp_dac_ldac_n_o : out std_logic; - rtmlamp_dac_cs_n_o : out std_logic; - rtmlamp_dac_sck_o : out std_logic; - rtmlamp_dac_sdi_o : out std_logic_vector(g_RTMLAMP_CHANNELS-1 downto 0); - - --------------------------------------------------------------------------- - -- RTM Serial registers interface - --------------------------------------------------------------------------- - rtmlamp_amp_shift_clk_o : out std_logic; - -- Only for AFCv4 - -- rtmlamp_amp_shift_dout_i : in std_logic; - -- rtmlamp_amp_shift_pl_o : out std_logic; - - -- rtmlamp_amp_shift_oe_n_o : out std_logic; - rtmlamp_amp_shift_din_o : out std_logic; - rtmlamp_amp_shift_str_o : out std_logic -); -end entity afcv3_ref_fofb_ctrl; - -architecture top of afcv3_ref_fofb_ctrl is - -begin - - cmp_afc_ref_fofb_ctrl_gen : entity work.afc_ref_fofb_ctrl_gen - generic map ( - g_BOARD => "AFCv3", - -- Select RTM LAMP or RTM SFP - g_RTM => "RTMLAMP", - -- Number of P2P GTs - g_NUM_P2P_GTS => g_NUM_P2P_GTS, - -- Starting index of used P2P GTs - g_P2P_GT_START_ID => g_P2P_GT_START_ID, - -- Number of RTM LAMP channels - g_RTMLAMP_CHANNELS => g_RTMLAMP_CHANNELS - ) - port map ( - --------------------------------------------------------------------------- - -- Clocking pins - --------------------------------------------------------------------------- - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - - aux_clk_p_i => aux_clk_p_i, - aux_clk_n_i => aux_clk_n_i, - - afc_fp2_clk1_p_i => afc_fp2_clk1_p_i, - afc_fp2_clk1_n_i => afc_fp2_clk1_n_i, - - --------------------------------------------------------------------------- - -- Reset Button - --------------------------------------------------------------------------- - sys_rst_button_n_i => sys_rst_button_n_i, - - --------------------------------------------------------------------------- - -- UART pins - --------------------------------------------------------------------------- - - uart_rxd_i => uart_rxd_i, - uart_txd_o => uart_txd_o, - - --------------------------------------------------------------------------- - -- Trigger pins - --------------------------------------------------------------------------- - trig_dir_o => trig_dir_o, - -- AFCv3 - trig_b => trig_b, - - --------------------------------------------------------------------------- - -- AFC Diagnostics - --------------------------------------------------------------------------- - - diag_spi_cs_i => diag_spi_cs_i, - diag_spi_si_i => diag_spi_si_i, - diag_spi_so_o => diag_spi_so_o, - diag_spi_clk_i => diag_spi_clk_i, - - --------------------------------------------------------------------------- - -- ADN4604ASVZ. AFCv3 - --------------------------------------------------------------------------- - adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o, - - --------------------------------------------------------------------------- - -- AFC I2C. - --------------------------------------------------------------------------- - -- Si57x oscillator - afc_si57x_scl_b => afc_si57x_scl_b, - afc_si57x_sda_b => afc_si57x_sda_b, - - -- Si57x oscillator output enable - afc_si57x_oe_o => afc_si57x_oe_o, - - --------------------------------------------------------------------------- - -- PCIe pins - --------------------------------------------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b => ddr3_dq_b, - ddr3_dqs_p_b => ddr3_dqs_p_b, - ddr3_dqs_n_b => ddr3_dqs_n_b, - ddr3_addr_o => ddr3_addr_o, - ddr3_ba_o => ddr3_ba_o, - ddr3_cs_n_o => ddr3_cs_n_o, - ddr3_ras_n_o => ddr3_ras_n_o, - ddr3_cas_n_o => ddr3_cas_n_o, - ddr3_we_n_o => ddr3_we_n_o, - ddr3_reset_n_o => ddr3_reset_n_o, - ddr3_ck_p_o => ddr3_ck_p_o, - ddr3_ck_n_o => ddr3_ck_n_o, - ddr3_cke_o => ddr3_cke_o, - ddr3_dm_o => ddr3_dm_o, - ddr3_odt_o => ddr3_odt_o, - - -- PCIe transceivers - pci_exp_rxp_i => pci_exp_rxp_i, - pci_exp_rxn_i => pci_exp_rxn_i, - pci_exp_txp_o => pci_exp_txp_o, - pci_exp_txn_o => pci_exp_txn_o, - - -- PCI clock and reset signals - pcie_clk_p_i => pcie_clk_p_i, - pcie_clk_n_i => pcie_clk_n_i, - - --------------------------------------------------------------------------- - -- User LEDs - --------------------------------------------------------------------------- - leds_o => leds_o, - - --------------------------------------------------------------------------- - -- FMC interface - --------------------------------------------------------------------------- - - board_i2c_scl_b => board_i2c_scl_b, - board_i2c_sda_b => board_i2c_sda_b, - - --------------------------------------------------------------------------- - -- Flash memory SPI interface - --------------------------------------------------------------------------- - -- - -- spi_sclk_o : out std_logic; - -- spi_cs_n_o : out std_logic; - -- spi_mosi_o : out std_logic; - -- spi_miso_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- P2P GT pins - --------------------------------------------------------------------------- - -- P2P - p2p_gt_rx_p_i => p2p_gt_rx_p_i, - p2p_gt_rx_n_i => p2p_gt_rx_n_i, - p2p_gt_tx_p_o => p2p_gt_tx_p_o, - p2p_gt_tx_n_o => p2p_gt_tx_n_o, - - --------------------------------------------------------------------------- - -- FMC slot 0 - CAEN 4 SFP+ - --------------------------------------------------------------------------- - - fmc0_sfp_rx_p_i => fmc0_sfp_rx_p_i, - fmc0_sfp_rx_n_i => fmc0_sfp_rx_n_i, - fmc0_sfp_tx_p_o => fmc0_sfp_tx_p_o, - fmc0_sfp_tx_n_o => fmc0_sfp_tx_n_o, - - fmc0_sfp_scl_b => fmc0_sfp_scl_b, - fmc0_sfp_sda_b => fmc0_sfp_sda_b, - fmc0_sfp_mod_abs_i => fmc0_sfp_mod_abs_i, - fmc0_sfp_rx_los_i => fmc0_sfp_rx_los_i, - fmc0_sfp_tx_disable_o => fmc0_sfp_tx_disable_o, - fmc0_sfp_tx_fault_i => fmc0_sfp_tx_fault_i, - fmc0_sfp_rs0_o => fmc0_sfp_rs0_o, - fmc0_sfp_rs1_o => fmc0_sfp_rs1_o, - - fmc0_si570_clk_p_i => fmc0_si570_clk_p_i, - fmc0_si570_clk_n_i => fmc0_si570_clk_n_i, - fmc0_si570_scl_b => fmc0_si570_scl_b, - fmc0_si570_sda_b => fmc0_si570_sda_b, - - --------------------------------------------------------------------------- - -- FMC slot 0 management - --------------------------------------------------------------------------- - fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i, - -- fmc0_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM) - -- fmc0_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM) - - --------------------------------------------------------------------------- - -- FMC slot 1 management - --------------------------------------------------------------------------- - fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i, - -- fmc1_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM) - -- fmc1_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM) - - --------------------------------------------------------------------------- - -- RTM LAMP board pins - --------------------------------------------------------------------------- - - --------------------------------------------------------------------------- - -- RTM ADC interface - --------------------------------------------------------------------------- - rtmlamp_adc_cnv_o => rtmlamp_adc_cnv_o, - - rtmlamp_adc_octo_sck_p_o => rtmlamp_adc_octo_sck_p_o, - rtmlamp_adc_octo_sck_n_o => rtmlamp_adc_octo_sck_n_o, - rtmlamp_adc_octo_sck_ret_p_i => rtmlamp_adc_octo_sck_ret_p_i, - rtmlamp_adc_octo_sck_ret_n_i => rtmlamp_adc_octo_sck_ret_n_i, - rtmlamp_adc_octo_sdoa_p_i => rtmlamp_adc_octo_sdoa_p_i, - rtmlamp_adc_octo_sdoa_n_i => rtmlamp_adc_octo_sdoa_n_i, - rtmlamp_adc_octo_sdob_p_i => rtmlamp_adc_octo_sdob_p_i, - rtmlamp_adc_octo_sdob_n_i => rtmlamp_adc_octo_sdob_n_i, - rtmlamp_adc_octo_sdoc_p_i => rtmlamp_adc_octo_sdoc_p_i, - rtmlamp_adc_octo_sdoc_n_i => rtmlamp_adc_octo_sdoc_n_i, - rtmlamp_adc_octo_sdod_p_i => rtmlamp_adc_octo_sdod_p_i, - rtmlamp_adc_octo_sdod_n_i => rtmlamp_adc_octo_sdod_n_i, - - --------------------------------------------------------------------------- - -- RTM DAC interface - --------------------------------------------------------------------------- - rtmlamp_dac_ldac_n_o => rtmlamp_dac_ldac_n_o, - rtmlamp_dac_cs_n_o => rtmlamp_dac_cs_n_o, - rtmlamp_dac_sck_o => rtmlamp_dac_sck_o, - rtmlamp_dac_sdi_o => rtmlamp_dac_sdi_o, - - --------------------------------------------------------------------------- - -- RTM Serial registers interface - --------------------------------------------------------------------------- - rtmlamp_amp_shift_clk_o => rtmlamp_amp_shift_clk_o, - - rtmlamp_amp_shift_din_o => rtmlamp_amp_shift_din_o, - rtmlamp_amp_shift_str_o => rtmlamp_amp_shift_str_o - ); - -end architecture top; diff --git a/hdl/top/afcv3_rtm_sfp_design/Manifest.py b/hdl/top/afcv3_rtm_sfp_design/Manifest.py deleted file mode 100644 index b084cf13..00000000 --- a/hdl/top/afcv3_rtm_sfp_design/Manifest.py +++ /dev/null @@ -1,9 +0,0 @@ -files = [ - "afcv3_rtm_sfp_fofb_ctrl.vhd", -] - -modules = { - "local" : [ - "../afc_ref_design_gen", - ], -} diff --git a/hdl/top/afcv3_rtm_sfp_design/afcv3_rtm_sfp_fofb_ctrl.vhd b/hdl/top/afcv3_rtm_sfp_design/afcv3_rtm_sfp_fofb_ctrl.vhd deleted file mode 100644 index c7b5ff42..00000000 --- a/hdl/top/afcv3_rtm_sfp_design/afcv3_rtm_sfp_fofb_ctrl.vhd +++ /dev/null @@ -1,443 +0,0 @@ ------------------------------------------------------------------------------- --- Title : AFC RTM SFP design for FOFB Controller ------------------------------------------------------------------------------- --- Author : Melissa Aguiar --- Company : CNPEM LNLS-DIG --- Created : 2021-09-16 --- Platform : FPGA-generic -------------------------------------------------------------------------------- --- Description: AFC design for FOFB Controller + 1 FMC SFPs -------------------------------------------------------------------------------- --- Copyright (c) 2020 CNPEM --- Licensed under GNU Lesser General Public License (LGPL) v3.0 -------------------------------------------------------------------------------- --- Revisions : --- Date Version Author Description --- 2021-09-16 1.0 melissa.aguiar Created -------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; --- Main Wishbone Definitions -use work.wishbone_pkg.all; --- Custom Wishbone Modules -use work.ifc_wishbone_pkg.all; --- Custom common cores -use work.ifc_common_pkg.all; --- Custom generic cores -use work.ifc_generic_pkg.all; --- Trigger definitions -use work.trigger_common_pkg.all; --- Trigger Modules -use work.trigger_pkg.all; --- AFC base definitions -use work.afc_base_pkg.all; --- AFC base wrappers definitions -use work.afc_base_wrappers_pkg.all; --- General-cores Common -use work.gencores_pkg.all; --- IP cores constants -use work.ipcores_pkg.all; --- Meta Package -use work.synthesis_descriptor_pkg.all; --- Data Acquisition core -use work.acq_core_pkg.all; --- AXI cores -use work.pcie_cntr_axi_pkg.all; --- FOFC CC wrapper -use work.fofb_ctrl_pkg.all; --- FOFC CC -use work.fofb_cc_pkg.all; --- Dot product package -use work.dot_prod_pkg.all; --- RAM package -use work.genram_pkg.all; - -entity afcv3_rtm_sfp_fofb_ctrl is -generic ( - -- Number of SFP GTs - g_NUM_SFPS : integer := 4; - -- Starting index of used SFP GTs - g_SFP_START_ID : integer := 4; - -- Number of P2P GTs - g_NUM_P2P_GTS : integer := 8; - -- Starting index of used P2P GTs - g_P2P_GT_START_ID : integer := 0; - -- Number of RTM LAMP ADC channels - g_ADC_CHANNELS : natural := 8; - -- Number of RTM LAMP DAC channels - g_DAC_CHANNELS : natural := 8 -); -port ( - --------------------------------------------------------------------------- - -- Clocking pins - --------------------------------------------------------------------------- - sys_clk_p_i : in std_logic; - sys_clk_n_i : in std_logic; - - aux_clk_p_i : in std_logic; - aux_clk_n_i : in std_logic; - - afc_fp2_clk1_p_i : in std_logic; - afc_fp2_clk1_n_i : in std_logic; - - --------------------------------------------------------------------------- - -- Reset Button - --------------------------------------------------------------------------- - sys_rst_button_n_i : in std_logic := '1'; - - --------------------------------------------------------------------------- - -- UART pins - --------------------------------------------------------------------------- - - uart_rxd_i : in std_logic := '1'; - uart_txd_o : out std_logic; - - --------------------------------------------------------------------------- - -- Trigger pins - --------------------------------------------------------------------------- - trig_dir_o : out std_logic_vector(c_NUM_TRIG-1 downto 0); - trig_b : inout std_logic_vector(c_NUM_TRIG-1 downto 0); - - --------------------------------------------------------------------------- - -- AFC Diagnostics - --------------------------------------------------------------------------- - - diag_spi_cs_i : in std_logic := '0'; - diag_spi_si_i : in std_logic := '0'; - diag_spi_so_o : out std_logic; - diag_spi_clk_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- ADN4604ASVZ - --------------------------------------------------------------------------- - adn4604_vadj2_clk_updt_n_o : out std_logic; - - --------------------------------------------------------------------------- - -- AFC I2C. - --------------------------------------------------------------------------- - -- Si57x oscillator - afc_si57x_scl_b : inout std_logic; - afc_si57x_sda_b : inout std_logic; - - -- Si57x oscillator output enable - afc_si57x_oe_o : out std_logic; - - --------------------------------------------------------------------------- - -- PCIe pins - --------------------------------------------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b : inout std_logic_vector(c_DDR_DQ_WIDTH-1 downto 0); - ddr3_dqs_p_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0); - ddr3_dqs_n_b : inout std_logic_vector(c_DDR_DQS_WIDTH-1 downto 0); - ddr3_addr_o : out std_logic_vector(c_DDR_ROW_WIDTH-1 downto 0); - ddr3_ba_o : out std_logic_vector(c_DDR_BANK_WIDTH-1 downto 0); - ddr3_cs_n_o : out std_logic_vector(0 downto 0); - ddr3_ras_n_o : out std_logic; - ddr3_cas_n_o : out std_logic; - ddr3_we_n_o : out std_logic; - ddr3_reset_n_o : out std_logic; - ddr3_ck_p_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0); - ddr3_ck_n_o : out std_logic_vector(c_DDR_CK_WIDTH-1 downto 0); - ddr3_cke_o : out std_logic_vector(c_DDR_CKE_WIDTH-1 downto 0); - ddr3_dm_o : out std_logic_vector(c_DDR_DM_WIDTH-1 downto 0); - ddr3_odt_o : out std_logic_vector(c_DDR_ODT_WIDTH-1 downto 0); - - -- PCIe transceivers - pci_exp_rxp_i : in std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_rxn_i : in std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_txp_o : out std_logic_vector(c_PCIELANES - 1 downto 0); - pci_exp_txn_o : out std_logic_vector(c_PCIELANES - 1 downto 0); - - -- PCI clock and reset signals - pcie_clk_p_i : in std_logic; - pcie_clk_n_i : in std_logic; - - --------------------------------------------------------------------------- - -- User LEDs - --------------------------------------------------------------------------- - leds_o : out std_logic_vector(2 downto 0); - - --------------------------------------------------------------------------- - -- FMC interface - --------------------------------------------------------------------------- - - board_i2c_scl_b : inout std_logic; - board_i2c_sda_b : inout std_logic; - - --------------------------------------------------------------------------- - -- Flash memory SPI interface - --------------------------------------------------------------------------- - -- - -- spi_sclk_o : out std_logic; - -- spi_cs_n_o : out std_logic; - -- spi_mosi_o : out std_logic; - -- spi_miso_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- P2P GT pins - --------------------------------------------------------------------------- - -- P2P - p2p_gt_rx_p_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - p2p_gt_rx_n_i : in std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - p2p_gt_tx_p_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - p2p_gt_tx_n_o : out std_logic_vector(g_NUM_P2P_GTS+g_P2P_GT_START_ID-1 downto g_P2P_GT_START_ID); - - --------------------------------------------------------------------------- - -- RTM SFP board pins - --------------------------------------------------------------------------- - -- SFP - rtm_sfp_rx_p_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID); - rtm_sfp_rx_n_i : in std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID); - rtm_sfp_tx_p_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID); - rtm_sfp_tx_n_o : out std_logic_vector(g_NUM_SFPS+g_SFP_START_ID-1 downto g_SFP_START_ID); - - -- RTM I2C. - -- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8 - -- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55 - rtm_scl_b : inout std_logic; - rtm_sda_b : inout std_logic; - - -- Si570 oscillator output enable - rtm_si570_oe_o : out std_logic; - - ---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected directly to - -- AFC - --rtm_rtm_sync_clk_p_o : out std_logic; - --rtm_rtm_sync_clk_n_o : out std_logic; - - -- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock - rtm_clk_in_sel_o : out std_logic; - - -- FPGA clocks from CDCLVD1212 - rtm_fpga_clk1_p_i : in std_logic; - rtm_fpga_clk1_n_i : in std_logic; - rtm_fpga_clk2_p_i : in std_logic; - rtm_fpga_clk2_n_i : in std_logic; - - -- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits. - -- The PISO chips are organized like this: - -- - -- Parallel load - rtm_sfp_status_reg_pl_o : out std_logic; - -- Clock N - rtm_sfp_status_reg_clk_n_o : out std_logic; - -- Serial output - rtm_sfp_status_reg_out_i : in std_logic; - - -- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits. - -- The SIPO chips are organized like this: - -- - -- Strobe - rtm_sfp_ctl_str_n_o : out std_logic; - -- Data input - rtm_sfp_ctl_din_n_o : out std_logic; - -- Parallel output enable - rtm_sfp_ctl_oe_n_o : out std_logic; - - -- External clock from RTM to FPGA - rtm_ext_clk_p_i : in std_logic; - rtm_ext_clk_n_i : in std_logic -); -end entity afcv3_rtm_sfp_fofb_ctrl; - -architecture top of afcv3_rtm_sfp_fofb_ctrl is - -begin - - cmp_afc_ref_fofb_ctrl_gen : entity work.afc_ref_fofb_ctrl_gen - generic map ( - g_BOARD => "AFCv3", - g_RTM => "RTMSFP", - -- Number of SFP GTs - g_NUM_SFPS => g_NUM_SFPS, - -- Starting index of used SFP GTs - g_SFP_START_ID => g_SFP_START_ID, - -- Number of P2P GTs - g_NUM_P2P_GTS => g_NUM_P2P_GTS, - -- Starting index of used P2P GTs - g_P2P_GT_START_ID => g_P2P_GT_START_ID, - -- Number of RTM LAMP ADC channels - g_ADC_CHANNELS => g_ADC_CHANNELS, - -- Number of RTM LAMP DAC channels - g_DAC_CHANNELS => g_DAC_CHANNELS - ) - port map ( - --------------------------------------------------------------------------- - -- Clocking pins - --------------------------------------------------------------------------- - sys_clk_p_i => sys_clk_p_i, - sys_clk_n_i => sys_clk_n_i, - - aux_clk_p_i => aux_clk_p_i, - aux_clk_n_i => aux_clk_n_i, - - afc_fp2_clk1_p_i => afc_fp2_clk1_p_i, - afc_fp2_clk1_n_i => afc_fp2_clk1_n_i, - - --------------------------------------------------------------------------- - -- Reset Button - --------------------------------------------------------------------------- - sys_rst_button_n_i => sys_rst_button_n_i, - - --------------------------------------------------------------------------- - -- UART pins - --------------------------------------------------------------------------- - - uart_rxd_i => uart_rxd_i, - uart_txd_o => uart_txd_o, - - --------------------------------------------------------------------------- - -- Trigger pins - --------------------------------------------------------------------------- - trig_dir_o => trig_dir_o, - -- AFCv3 - trig_b => trig_b, - - --------------------------------------------------------------------------- - -- AFC Diagnostics - --------------------------------------------------------------------------- - - diag_spi_cs_i => diag_spi_cs_i, - diag_spi_si_i => diag_spi_si_i, - diag_spi_so_o => diag_spi_so_o, - diag_spi_clk_i => diag_spi_clk_i, - - --------------------------------------------------------------------------- - -- ADN4604ASVZ. AFCv3 - --------------------------------------------------------------------------- - adn4604_vadj2_clk_updt_n_o => adn4604_vadj2_clk_updt_n_o, - - --------------------------------------------------------------------------- - -- AFC I2C. - --------------------------------------------------------------------------- - -- Si57x oscillator - afc_si57x_scl_b => afc_si57x_scl_b, - afc_si57x_sda_b => afc_si57x_sda_b, - - -- Si57x oscillator output enable - afc_si57x_oe_o => afc_si57x_oe_o, - - --------------------------------------------------------------------------- - -- PCIe pins - --------------------------------------------------------------------------- - - -- DDR3 memory pins - ddr3_dq_b => ddr3_dq_b, - ddr3_dqs_p_b => ddr3_dqs_p_b, - ddr3_dqs_n_b => ddr3_dqs_n_b, - ddr3_addr_o => ddr3_addr_o, - ddr3_ba_o => ddr3_ba_o, - ddr3_cs_n_o => ddr3_cs_n_o, - ddr3_ras_n_o => ddr3_ras_n_o, - ddr3_cas_n_o => ddr3_cas_n_o, - ddr3_we_n_o => ddr3_we_n_o, - ddr3_reset_n_o => ddr3_reset_n_o, - ddr3_ck_p_o => ddr3_ck_p_o, - ddr3_ck_n_o => ddr3_ck_n_o, - ddr3_cke_o => ddr3_cke_o, - ddr3_dm_o => ddr3_dm_o, - ddr3_odt_o => ddr3_odt_o, - - -- PCIe transceivers - pci_exp_rxp_i => pci_exp_rxp_i, - pci_exp_rxn_i => pci_exp_rxn_i, - pci_exp_txp_o => pci_exp_txp_o, - pci_exp_txn_o => pci_exp_txn_o, - - -- PCI clock and reset signals - pcie_clk_p_i => pcie_clk_p_i, - pcie_clk_n_i => pcie_clk_n_i, - - --------------------------------------------------------------------------- - -- User LEDs - --------------------------------------------------------------------------- - leds_o => leds_o, - - --------------------------------------------------------------------------- - -- FMC interface - --------------------------------------------------------------------------- - - board_i2c_scl_b => board_i2c_scl_b, - board_i2c_sda_b => board_i2c_sda_b, - - --------------------------------------------------------------------------- - -- Flash memory SPI interface - --------------------------------------------------------------------------- - -- - -- spi_sclk_o : out std_logic; - -- spi_cs_n_o : out std_logic; - -- spi_mosi_o : out std_logic; - -- spi_miso_i : in std_logic := '0'; - - --------------------------------------------------------------------------- - -- P2P GT pins - --------------------------------------------------------------------------- - -- P2P - p2p_gt_rx_p_i => p2p_gt_rx_p_i, - p2p_gt_rx_n_i => p2p_gt_rx_n_i, - p2p_gt_tx_p_o => p2p_gt_tx_p_o, - p2p_gt_tx_n_o => p2p_gt_tx_n_o, - - --------------------------------------------------------------------------- - -- RTM SFP board pins - --------------------------------------------------------------------------- - -- SFP - rtm_sfp_rx_p_i => rtm_sfp_rx_p_i, - rtm_sfp_rx_n_i => rtm_sfp_rx_n_i, - rtm_sfp_tx_p_o => rtm_sfp_tx_p_o, - rtm_sfp_tx_n_o => rtm_sfp_tx_n_o, - - -- RTM I2C. - -- SFP configuration pins, behind a I2C MAX7356. I2C addr = 1110_100 & '0' = 0xE8 - -- Si570 oscillator. Input 0 of CDCLVD1212. I2C addr = 1010101 & '0' = 0x55 - rtm_scl_b => rtm_scl_b, - rtm_sda_b => rtm_sda_b, - - -- Si570 oscillator output enable - rtm_si570_oe_o => rtm_si570_oe_o, - - ---- Clock to RTM connector. Input 1 of CDCLVD1212. Not connected directly to - -- AFC - --rtm_rtm_sync_clk_p_o : out std_logic; - --rtm_rtm_sync_clk_n_o : out std_logic; - - -- Select between input 0 or 1 or CDCLVD1212. 0 is Si570, 1 is RTM sync clock - rtm_clk_in_sel_o => rtm_clk_in_sel_o, - - -- FPGA clocks from CDCLVD1212 - rtm_fpga_clk1_p_i => rtm_fpga_clk1_p_i, - rtm_fpga_clk1_n_i => rtm_fpga_clk1_n_i, - rtm_fpga_clk2_p_i => rtm_fpga_clk2_p_i, - rtm_fpga_clk2_n_i => rtm_fpga_clk2_n_i, - - -- SFP status bits. Behind 4 74HC165, 8-parallel-in/serial-out. 4 x 8 bits. - -- The PISO chips are organized like this: - -- - -- Parallel load - rtm_sfp_status_reg_pl_o => rtm_sfp_status_reg_pl_o, - -- Clock N - rtm_sfp_status_reg_clk_n_o => rtm_sfp_status_reg_clk_n_o, - -- Serial output - rtm_sfp_status_reg_out_i => rtm_sfp_status_reg_out_i, - - -- SFP control bits. Behind 4 74HC4094D, serial-in/8-parallel-out. 5 x 8 bits. - -- The SIPO chips are organized like this: - -- - -- Strobe - rtm_sfp_ctl_str_n_o => rtm_sfp_ctl_str_n_o, - -- Data input - rtm_sfp_ctl_din_n_o => rtm_sfp_ctl_din_n_o, - -- Parallel output enable - rtm_sfp_ctl_oe_n_o => rtm_sfp_ctl_oe_n_o, - - -- External clock from RTM to FPGA - rtm_ext_clk_p_i => rtm_ext_clk_p_i, - rtm_ext_clk_n_i => rtm_ext_clk_n_i - ); - -end architecture top; From 87b28e9e50208bc3feb59fade320d215f889d1fb Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Tue, 7 May 2024 16:49:38 -0300 Subject: [PATCH 23/26] Update afc-gw submodule to replace rs232_syscon with xwb_master_uart The rs232_syscon core is hard to use from a software perspective, and it had some bug that caused frequent hangs during usage. xwb_master_uart is a much simpler implementation solves these issues. --- hdl/ip_cores/afc-gw | 2 +- .../afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd | 8 ++++++++ hdl/top/afcv4_ref_design/afcv4_ref_fofb_ctrl.vhd | 14 +++++++++++--- 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/hdl/ip_cores/afc-gw b/hdl/ip_cores/afc-gw index 51edb056..242f3436 160000 --- a/hdl/ip_cores/afc-gw +++ b/hdl/ip_cores/afc-gw @@ -1 +1 @@ -Subproject commit 51edb05638503bf7138c00c1f25d3e1cd4795520 +Subproject commit 242f3436bad08d63369bd870ab55a7a195aeec9b diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 97a2e61f..5efa0d9e 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -64,6 +64,10 @@ use work.genram_pkg.all; entity afc_ref_fofb_ctrl_gen is generic ( + g_UART_MASTER_BAUD : integer := 115200; + -- Configure Wishbone master UART baudrate + g_BENCH_MODE : boolean := false; + -- Enable bench mode (disable PCIe reset) g_BOARD : string := "AFCv4"; -- Select RTM LAMP or RTM SFP g_RTM : string := "RTMLAMP"; @@ -936,6 +940,7 @@ begin gen_afcv4_base : if g_BOARD = "AFCv4" generate cmp_afc_base_acq : afcv4_base_acq generic map ( + g_BENCH_MODE => g_BENCH_MODE, g_DIVCLK_DIVIDE => 5, g_CLKBOUT_MULT_F => 48, g_CLK0_DIVIDE_F => 12, -- 100 MHz @@ -961,6 +966,7 @@ begin -- If true, instantiate a VIC/UART/SPI. g_WITH_VIC => true, g_WITH_UART_MASTER => true, + g_UART_MASTER_BAUD => g_UART_MASTER_BAUD, g_WITH_TRIGGER => true, g_WITH_SPI => false, g_WITH_AFC_SI57x => true, @@ -1169,6 +1175,7 @@ begin gen_afcv3_base : if g_BOARD = "AFCv3" generate cmp_afc_base_acq : afcv3_base_acq generic map ( + g_BENCH_MODE => g_BENCH_MODE, g_DIVCLK_DIVIDE => 5, g_CLKBOUT_MULT_F => 48, g_CLK0_DIVIDE_F => 12, -- 100 MHz @@ -1194,6 +1201,7 @@ begin -- If true, instantiate a VIC/UART/SPI. g_WITH_VIC => true, g_WITH_UART_MASTER => true, + g_UART_MASTER_BAUD => g_UART_MASTER_BAUD, g_WITH_TRIGGER => true, g_WITH_SPI => false, g_WITH_AFC_SI57x => true, diff --git a/hdl/top/afcv4_ref_design/afcv4_ref_fofb_ctrl.vhd b/hdl/top/afcv4_ref_design/afcv4_ref_fofb_ctrl.vhd index f8801ee5..c7797b41 100644 --- a/hdl/top/afcv4_ref_design/afcv4_ref_fofb_ctrl.vhd +++ b/hdl/top/afcv4_ref_design/afcv4_ref_fofb_ctrl.vhd @@ -56,12 +56,16 @@ use work.rtm_lamp_pkg.all; entity afcv4_ref_fofb_ctrl is generic ( + -- Configure Wishbone master UART baudrate + g_UART_MASTER_BAUD : integer := 115200; + -- Enable bench mode (disable PCIe reset) + g_BENCH_MODE : boolean := false; -- Number of P2P GTs - g_NUM_P2P_GTS : integer := 8; + g_NUM_P2P_GTS : integer := 8; -- Starting index of used P2P GTs - g_P2P_GT_START_ID : integer := 0; + g_P2P_GT_START_ID : integer := 0; -- Number of RTM LAMP ADC channels - g_RTMLAMP_CHANNELS : natural := 12 + g_RTMLAMP_CHANNELS : natural := 12 ); port ( --------------------------------------------------------------------------- @@ -271,6 +275,10 @@ begin cmp_afc_ref_fofb_ctrl_gen : entity work.afc_ref_fofb_ctrl_gen generic map ( + -- Enable bench mode (disable PCIe reset) + g_BENCH_MODE => g_BENCH_MODE, + -- Configure Wishbone master UART baudrate + g_UART_MASTER_BAUD => g_UART_MASTER_BAUD, g_BOARD => "AFCv4", -- Select RTM LAMP or RTM SFP g_RTM => "RTMLAMP", From 06199ee54b4c55875eeeb8616a4ae1241ddc7cb3 Mon Sep 17 00:00:00 2001 From: Augusto Fraga Giachero Date: Wed, 8 May 2024 08:05:43 -0300 Subject: [PATCH 24/26] Update rtm-lamp-gw submodule Include fixes for the CDC logic in the ADC clock counter. --- hdl/ip_cores/rtm-lamp-gw | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hdl/ip_cores/rtm-lamp-gw b/hdl/ip_cores/rtm-lamp-gw index e144d66a..5aab5c23 160000 --- a/hdl/ip_cores/rtm-lamp-gw +++ b/hdl/ip_cores/rtm-lamp-gw @@ -1 +1 @@ -Subproject commit e144d66a797ffdfc02cdc2df7141cb61a2af0b82 +Subproject commit 5aab5c2356b814c3507d890f35fc613c8dc8ebe4 From 4ee6a32cf6f9ba0f5299b0ca58286bcb2419794c Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 17 May 2024 13:43:34 -0300 Subject: [PATCH 25/26] xwb_fofb_shaper_filt.vhd: fix wrong internal sizes Although the ABI supports up to 10 biquads, internal signals were sized to hold g_NUM_BIQUADS coefficients only. This can lead to wrong register accesses depending on the dimensions. So, proper size these signals to avoid this. --- .../fofb_shaper_filt/xwb_fofb_shaper_filt.vhd | 11 +++++---- .../fofb_shaper_filt_coeffs.dat | 24 +++++++++---------- .../xwb_fofb_shaper_filt_tb.vhd | 3 ++- 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd index aaddd20e..de381d37 100644 --- a/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd +++ b/hdl/modules/fofb_shaper_filt/xwb_fofb_shaper_filt.vhd @@ -99,6 +99,7 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS CONSTANT c_PERIPH_ADDR_SIZE : NATURAL := 2+2; CONSTANT c_MAX_CHANNELS : NATURAL := 12; + CONSTANT c_MAX_ABI_BIQUADS : NATURAL := 10; CONSTANT c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_I_IFC_0s : t_wb_fofb_shaper_filt_regs_coeffs_i_ifc := (data => (OTHERS => '0')); @@ -138,17 +139,17 @@ ARCHITECTURE behave OF xwb_fofb_shaper_filt IS (OTHERS => c_WB_FOFB_SHAPER_FILT_REGS_COEFFS_O_IFC_0s); SIGNAL coeffs : t_fofb_shaper_filt_coeffs(g_CHANNELS-1 DOWNTO 0)( - g_NUM_BIQUADS-1 DOWNTO 0)( + c_MAX_ABI_BIQUADS-1 DOWNTO 0)( b0(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), b1(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), b2(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), a1(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH), a2(g_COEFF_INT_WIDTH-1 DOWNTO -g_COEFF_FRAC_WIDTH)); - SIGNAL biquad_idx : NATURAL RANGE 0 to g_NUM_BIQUADS-1 := 0; - SIGNAL coeff_idx : NATURAL RANGE 0 to 4 := 0; + SIGNAL biquad_idx : NATURAL RANGE 0 TO c_MAX_ABI_BIQUADS-1 := 0; + SIGNAL coeff_idx : NATURAL RANGE 0 TO 7 := 0; BEGIN - ASSERT g_NUM_BIQUADS <= 10 + ASSERT g_NUM_BIQUADS <= c_MAX_ABI_BIQUADS REPORT "ABI supports up to 20th order filters (i.e. 10 biquads)" SEVERITY FAILURE; @@ -252,7 +253,7 @@ BEGIN rst_n_i => rst_n_i, x_i => iir_filts_x(idx), x_valid_i => sp_valid_arr_i(idx), - coeffs_i => coeffs(idx), + coeffs_i => coeffs(idx)(g_NUM_BIQUADS-1 DOWNTO 0), busy_o => busy_arr_o(idx), y_o => iir_filts_y(idx), y_valid_o => filt_sp_valid_arr_o(idx) diff --git a/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat index 2a02f909..fed80750 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat +++ b/hdl/testbench/xwb_fofb_shaper_filt/fofb_shaper_filt_coeffs.dat @@ -1,12 +1,12 @@ -9.26728558e-03 1.85345712e-02 9.26728558e-03 -1.38777878e-16 9.70055654e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.94289029e-16 9.20192105e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 2.85702154e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 6.73513678e-01 -9.26728558e-03 1.85345712e-02 9.26728558e-03 -1.38777878e-16 9.70055654e-03 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.94289029e-16 9.20192105e-02 1.00000000e+00 2.00000000e+00 1.00000000e+00 -1.66533454e-16 2.85702154e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 6.73513678e-01 -9.26728558e-03 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2.85702154e-01 1.00000000e+00 2.00000000e+00 1.00000000e+00 -2.22044605e-16 6.73513678e-01 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 diff --git a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd index 3f0fb33d..a25759a8 100644 --- a/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd +++ b/hdl/testbench/xwb_fofb_shaper_filt/xwb_fofb_shaper_filt_tb.vhd @@ -57,6 +57,7 @@ END ENTITY xwb_fofb_shaper_filt_tb; ARCHITECTURE test OF xwb_fofb_shaper_filt_tb IS CONSTANT c_SYS_CLOCK_FREQ : NATURAL := 100_000_000; + CONSTANT c_MAX_ABI_BIQUADS : NATURAL := 10; SIGNAL clk : STD_LOGIC := '0'; SIGNAL rst_n : STD_LOGIC := '1'; @@ -151,7 +152,7 @@ BEGIN ch_idx*c_WB_FOFB_SHAPER_FILT_REGS_CH_0_SIZE; readline(fin, lin); - FOR biquad_idx IN 0 TO g_NUM_BIQUADS-1 + FOR biquad_idx IN 0 TO c_MAX_ABI_BIQUADS-1 LOOP FOR coeff_idx IN 0 TO 4 LOOP From e0cc39f521a5fe5c10621974dda9446372895a9a Mon Sep 17 00:00:00 2001 From: "guilherme.ricioli" Date: Fri, 17 May 2024 15:50:34 -0300 Subject: [PATCH 26/26] afc_ref_fofb_ctrl_gen.vhd: remove unused constant --- hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd index 5efa0d9e..609d40ca 100644 --- a/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd +++ b/hdl/top/afc_ref_design_gen/afc_ref_fofb_ctrl_gen.vhd @@ -763,12 +763,6 @@ architecture top of afc_ref_fofb_ctrl_gen is atom_width => to_unsigned(16, c_ACQ_ATOM_WIDTH_LOG2) ); - constant c_FACQ_PARAMS_DCC : t_facq_chan_param := ( - width => to_unsigned(256, c_ACQ_CHAN_CMPLT_WIDTH_LOG2), - num_atoms => to_unsigned(8, c_ACQ_NUM_ATOMS_WIDTH_LOG2), - atom_width => to_unsigned(32, c_ACQ_ATOM_WIDTH_LOG2) - ); - constant c_FACQ_PARAMS_SYS_ID : t_facq_chan_param := ( -- NOTE: Altough 768 bits would be enough, using this value as width somehow -- causes ACQ samples to be weirdly misaligned (see https://github.com/lnls-dig/infra-cores/issues/18).