AFCv3 doesn't check success and propagate errors in clock switch configuration

[gustavosr8]

The AFCv3 clock switch configuration doesn't check when the I2C calls have success of not, and do nothing if the configuration fails somehow. The functions must be refactored to check if the configuration works and propagate this.
Related code:

openMMC/port/board/afc-v3/payload.c

Lines 480 to 547 in d7c579f

	void clock_configuration()
	{
	adn_connect_map_t con;
	/* Read the clock configuration from the eeprom */
	eeprom_24xx02_read(CHIP_ID_RTC_EEPROM, 0x0, clock_config, 16, 10);
	/* Translate the configuration to enable or disable the outputs */
	uint16_t out_enable_flag = {
	((clock_config[0] & 0x80) >> 7) << 0 |
	((clock_config[1] & 0x80) >> 7) << 1 |
	((clock_config[2] & 0x80) >> 7) << 2 |
	((clock_config[3] & 0x80) >> 7) << 3 |
	((clock_config[4] & 0x80) >> 7) << 4 |
	((clock_config[5] & 0x80) >> 7) << 5 |
	((clock_config[6] & 0x80) >> 7) << 6 |
	((clock_config[7] & 0x80) >> 7) << 7 |
	((clock_config[8] & 0x80) >> 7) << 8 |
	((clock_config[9] & 0x80) >> 7) << 9 |
	((clock_config[10] & 0x80) >> 7) << 10 |
	((clock_config[11] & 0x80) >> 7) << 11 |
	((clock_config[12] & 0x80) >> 7) << 12 |
	((clock_config[13] & 0x80) >> 7) << 13 |
	((clock_config[14] & 0x80) >> 7) << 14 |
	((clock_config[15] & 0x80) >> 7) << 15
	};
	/* Disable UPDATE' pin by pulling it GPIO_LEVEL_HIGH */
	gpio_set_pin_state( PIN_PORT(GPIO_ADN_UPDATE), PIN_NUMBER(GPIO_ADN_UPDATE), GPIO_LEVEL_HIGH );
	/* There's a delay circuit in the Reset pin of the clock switch, we must wait until it clears out */
	while( gpio_read_pin( PIN_PORT(GPIO_ADN_RESETN), PIN_NUMBER(GPIO_ADN_RESETN) ) == 0 ) {
	vTaskDelay( 50 );
	}
	/* Configure the interconnects*/
	con.out0 = clock_config[0] & 0x0F;
	con.out1 = clock_config[1] & 0x0F;
	con.out2 = clock_config[2] & 0x0F;
	con.out3 = clock_config[3] & 0x0F;
	con.out4 = clock_config[4] & 0x0F;
	con.out5 = clock_config[5] & 0x0F;
	con.out6 = clock_config[6] & 0x0F;
	con.out7 = clock_config[7] & 0x0F;
	con.out8 = clock_config[8] & 0x0F;
	con.out9 = clock_config[9] & 0x0F;
	con.out10 = clock_config[10] & 0x0F;
	con.out11 = clock_config[11] & 0x0F;
	con.out12 = clock_config[12] & 0x0F;
	con.out13 = clock_config[13] & 0x0F;
	con.out14 = clock_config[14] & 0x0F;
	con.out15 = clock_config[15] & 0x0F;
	adn4604_xpt_config( ADN_XPT_MAP0_CON_REG, con );
	/* Enable desired outputs */
	for ( uint8_t i = 0; i < 16; i++ ) {
	if ( ( out_enable_flag >> i ) & 0x1 ) {
	adn4604_tx_control( i, TX_ENABLED );
	} else {
	adn4604_tx_control( i, TX_DISABLED );
	}
	}
	adn4604_active_map( ADN_XPT_MAP0 );
	adn4604_update();
	}

openMMC/modules/adn4604.c

Lines 32 to 151 in d7c579f

	#include "FreeRTOS.h"
	/* Project Includes */
	#include "port.h"
	#include "adn4604.h"
	#include "i2c.h"
	#include "i2c_mapping.h"
	adn_connect_map_t con;
	void adn4604_tx_control( uint8_t output, uint8_t tx_mode )
	{
	uint8_t i2c_addr, i2c_interf;
	uint8_t enable[2];
	/* TX Enable registers have an 0x20 offset from their value */
	enable[0] = 0x20 + output;
	/* TX Basic Control Register flags:
	* [6] TX CTL SELECT - 0: PE and output level control is derived from common lookup table
	* 1: PE and output level control is derived from per port drive control registers
	* [5:4] TX EN[1:0] - 00: TX disabled, lowest power state
	* 01: TX standby
	* 10: TX squelched
	* 11: TX enabled
	* [3] Reserved - Set to 0
	* [2:1] PE[2:0] - If TX CTL SELECT = 0,
	* 000: Table Entry 0
	* 001: Table Entry 1
	* 010: Table Entry 2
	* 011: Table Entry 3
	* 100: Table Entry 4
	* 101: Table Entry 5
	* 110: Table Entry 6
	* 111: Table Entry 7
	* - If TX CTL SELECT = 1, PE[2:0] are ignored
	*/
	enable[1] = tx_mode << 4;
	if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) {
	xI2CMasterWrite( i2c_interf, i2c_addr, enable, sizeof(enable) );
	i2c_give(i2c_interf);
	}
	}
	void adn4604_update( void )
	{
	uint8_t i2c_addr, i2c_interf;
	uint8_t update[2] = { ADN_XPT_UPDATE_REG, 0x01 };
	if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) {
	xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) );
	i2c_give(i2c_interf);
	}
	}
	void adn4604_reset( void )
	{
	uint8_t i2c_addr, i2c_interf;
	uint8_t update[2] = { ADN_RESET_REG, 0x01 };
	if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) {
	xI2CMasterWrite( i2c_interf, i2c_addr, update, sizeof(update) );
	i2c_give(i2c_interf);
	}
	}
	void adn4604_xpt_config( uint8_t map, adn_connect_map_t xpt_con )
	{
	uint8_t i2c_addr, i2c_interf;
	adn_connect_cfg_t cfg = { map, xpt_con };
	if (i2c_take_by_chipid(CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10) ) {
	xI2CMasterWrite( i2c_interf, i2c_addr, (uint8_t *)&cfg, sizeof(cfg) );
	i2c_give(i2c_interf);
	}
	}
	void adn4604_active_map( uint8_t map )
	{
	uint8_t i2c_addr, i2c_interf;
	/* Select the active map */
	uint8_t map_sel[2] = { ADN_XPT_MAP_TABLE_SEL_REG, map };
	if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) {
	xI2CMasterWrite( i2c_interf, i2c_addr, map_sel, sizeof(map_sel) );
	i2c_give( i2c_interf );
	}
	}
	adn_connect_map_t adn4604_out_status( void )
	{
	uint8_t i2c_addr, i2c_interf;
	uint8_t i;
	adn_connect_map_t stat_map = {0};
	if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) {
	/* Read all outputs status */
	for ( i = 0; i < 8; i++ ) {
	xI2CMasterWriteRead( i2c_interf, i2c_addr, ADN_XPT_STATUS_REG+i, (uint8_t *)(&stat_map)+i, 1 );
	}
	i2c_give( i2c_interf );
	}
	return stat_map;
	}
	void adn4604_termination_ctl( uint8_t cfg )
	{
	uint8_t i2c_addr, i2c_interf;
	uint8_t msg[2] = { ADN_TERMINATION_CTL_REG, (cfg & 0xF0) };
	if ( i2c_take_by_chipid( CHIP_ID_ADN, &i2c_addr, &i2c_interf, (TickType_t)10 ) ) {
	xI2CMasterWrite( i2c_interf, i2c_addr, msg, sizeof(msg) );
	i2c_give( i2c_interf );
	}
	}