ASSERT FAILED

[rezot98]

Hello,
I am running a simulation for Ibex demo system. I created a testbench file that instantiates ibex_demo_system.sv. The simulation works however in a TCL console I get a periodic messages that some asserts fail. For example this one `ASSERT_KNOWN(IbexDataReqX, data_req_o), that is given on ibex_top.sv on line 1097. This tells that the signal data_req_o should have known values (0 or 1), I check in the simulation and it has indeed only known values, however I am still getting [ASSERT FAILED] message. Could you help me to find out what can be a problem? Thanks.

[marnovandermaas]

Thanks for looking at the demo system. Can you help me reproduce your error? What environment are you using, and what commands did you run?

[rezot98]

Hello, thanks for your reply.
I am using vivado 2023.1.
I ran tcl commands to create a project and add all of the necessary files.
For some reason I cant upload .tcl file therefore I upload .txt file instead where all of the tcl commands are given.

ibex_demo_system.tcl.txt

[marnovandermaas]

I have personally never done a simulation test using Vivado. Is there any reason why you don't use our FuseSoC builds?

This gives you a Verilator simulator: https://github.com/lowRISC/ibex-demo-system?tab=readme-ov-file#building-simulation

This give you a Vivado bitstream project: https://github.com/lowRISC/ibex-demo-system?tab=readme-ov-file#building-fpga-bitstream

Let me know if you still get those issues when using the supported Vivado project.