Update Ibex #85
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Update Ibex #85
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Update code from upstream repository https://github.com/lowRISC/ibex.git to revision df88055aa38868451ce90d7fcc2bbf172a2dc8a0 * [util] Update check_tool_requirements.py (Gary Guo) * [ci] Run CI in merge queue and not master (James Wainwright) * [CI] change pr_lint to run on pull_request instead of target (Gary Guo) * [CI] add GitHub action version of the CI (Gary Guo) * [rtl] Avoid name collision in ibex_pmp.sv (Rupert Swarbrick) * [dv] Fix performance counter printing in simple system (Rupert Swarbrick) * Fix spelling of separator (Rupert Swarbrick) * [doc] Describe counters more explicitly in simple_system README (Rupert Swarbrick) * Update lowrisc_ip to lowRISC/opentitan@e6a0e9a136 (Rupert Swarbrick) * [dv] Add an extra key to common_project_cfg.hjson (Rupert Swarbrick) * [verilator] Slight refactor in ibex_tracer to avoid BLKSEQ warning (Rupert Swarbrick) * [verilator] Waive MULTIDRIVEN warning in ibex_tracer.sv (Rupert Swarbrick) * [ibex_pmp/lint] Declare functions before using them (Michael Schaffner) * Update google_riscv-dv to chipsalliance/riscv-dv@71666eb (Greg Chadwick) * [dv,vendor] Pin bitstring version to fix gen_csr_test.py (Greg Chadwick) * [dv] Fix ibex_cmd.py (Greg Chadwick) * Port directed_test_schema.py to recent versions of Pydantic (Rupert Swarbrick) * [doc] Bump minimum Verilator version (Rupert Swarbrick) * Tweak ibex_cmd.py to fail more cleanly (Rupert Swarbrick) * Remove (empty) Verible waiver file (Rupert Swarbrick) * [doc] Fix background of Icache block (Marno van der Maas) * [doc] Fix background in block diagram (Marno van der Maas) * [ci] Consolidate Verible linting workflow into one stage (James Wainwright) * [credits] Add names of recent contributors (Marno van der Maas) * Update google_riscv-dv to chipsalliance/riscv-dv@08b1206 (Marno van der Maas) * [vendor] Use new RISCV-DV URL (Marno van der Maas) * [dv,doc] Point reference to lowRISC branch (Marno van der Maas) * Update riscv-isa-sim to lowRISC/riscv-isa-sim@a4b823a1 (Marno van der Maas) * Update riscv-isa-sim to lowRISC/riscv-isa-sim@a7c5d5d8 (Marno van der Maas) * [vendor] Use lowRISC repo for vendoring (Marno van der Maas) * Update README.md (Katharina) * Remove initialisation for sim_finish in simulator_ctrl.sv (Rupert Swarbrick) * Use correct width for 1-bit inputs in ibex_simple_system.sv (Rupert Swarbrick) * Use named constant for default RAM behaviour (Rupert Swarbrick) Signed-off-by: Gary Guo <[email protected]>
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@rswarbrick I changed ibex_demo_system.sv to account for the mhpmcounter_num addition, PTAL. |
Merged
hcallahan-lowrisc
approved these changes
Jan 3, 2024
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