fuse.log

Running: fuse.exe -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Practicos Arquitectura/Pipeline/registers_test_isim_beh.exe" -prj "C:/Practicos Arquitectura/Pipeline/registers_test_beh.prj" "work.registers_test" "work.glbl" 
ISim P.15xf (signature 0xc3576ebc)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Analyzing Verilog file "C:/Practicos Arquitectura/Pipeline/registers.v" into library work
Analyzing Verilog file "C:/Practicos Arquitectura/Pipeline/registers_test.v" into library work
Analyzing Verilog file "C:/Xilinx/14.1/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Compiling module registers
Compiling module registers_test
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 2 sub-compilation(s) to finish...
Compiled 3 Verilog Units
Built simulation executable C:/Practicos Arquitectura/Pipeline/registers_test_isim_beh.exe
Fuse Memory Usage: 28224 KB
Fuse CPU Usage: 389 ms