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IP updated for 10M16
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mbtaylor1982 committed Dec 6, 2024
1 parent b52c3f8 commit 11430d8
Showing 38 changed files with 9,585 additions and 57 deletions.
Original file line number Diff line number Diff line change
@@ -4,11 +4,11 @@ preplace inst flash_interface_10M16SCU169C8G.avalon_bridge -pg 1 -lvl 2 -y 90
preplace inst flash_interface_10M16SCU169C8G -pg 1 -lvl 1 -y 40 -regy -20
preplace inst flash_interface_10M16SCU169C8G.clk_source -pg 1 -lvl 1 -y 50
preplace inst flash_interface_10M16SCU169C8G.onchip_flash -pg 1 -lvl 3 -y 70
preplace netloc FAN_OUT<net_container>flash_interface_10M16SCU169C8G</net_container>(SLAVE)onchip_flash.data,(MASTER)avalon_bridge.avalon_master,(SLAVE)onchip_flash.csr) 1 2 1 620
preplace netloc EXPORT<net_container>flash_interface_10M16SCU169C8G</net_container>(SLAVE)flash_interface_10M16SCU169C8G.clk,(SLAVE)clk_source.clk_in) 1 0 1 NJ
preplace netloc FAN_OUT<net_container>flash_interface_10M16SCU169C8G</net_container>(MASTER)avalon_bridge.avalon_master,(SLAVE)onchip_flash.csr,(SLAVE)onchip_flash.data) 1 2 1 620
preplace netloc EXPORT<net_container>flash_interface_10M16SCU169C8G</net_container>(SLAVE)clk_source.clk_in,(SLAVE)flash_interface_10M16SCU169C8G.clk) 1 0 1 NJ
preplace netloc EXPORT<net_container>flash_interface_10M16SCU169C8G</net_container>(SLAVE)clk_source.clk_in_reset,(SLAVE)flash_interface_10M16SCU169C8G.reset) 1 0 1 NJ
preplace netloc FAN_OUT<net_container>flash_interface_10M16SCU169C8G</net_container>(SLAVE)avalon_bridge.clk,(MASTER)clk_source.clk,(SLAVE)onchip_flash.clk) 1 1 2 330 180 600
preplace netloc FAN_OUT<net_container>flash_interface_10M16SCU169C8G</net_container>(SLAVE)onchip_flash.nreset,(MASTER)clk_source.clk_reset,(SLAVE)avalon_bridge.reset) 1 1 2 310 200 620
preplace netloc EXPORT<net_container>flash_interface_10M16SCU169C8G</net_container>(SLAVE)avalon_bridge.external_interface,(SLAVE)flash_interface_10M16SCU169C8G.external_interface) 1 0 2 NJ 40 NJ
preplace netloc FAN_OUT<net_container>flash_interface_10M16SCU169C8G</net_container>(MASTER)clk_source.clk,(SLAVE)onchip_flash.clk,(SLAVE)avalon_bridge.clk) 1 1 2 330 180 600
levelinfo -pg 1 0 110 750
levelinfo -hier flash_interface_10M16SCU169C8G 120 150 380 650 740
6 changes: 3 additions & 3 deletions Quartus/IP/flash_interface_10M16SCU169C8G.qsys
Original file line number Diff line number Diff line change
@@ -101,14 +101,14 @@
kind="altera_up_external_bus_to_avalon_bridge"
version="18.0"
enabled="1">
<parameter name="AUTO_CLK_CLOCK_RATE" value="6250000" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="25000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="addr_size" value="16" />
<parameter name="addr_size_multiplier" value="Mbytes" />
<parameter name="data_size" value="32" />
</module>
<module name="clk_source" kind="clock_source" version="22.1" enabled="1">
<parameter name="clockFrequency" value="6250000" />
<parameter name="clockFrequency" value="25000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
@@ -118,7 +118,7 @@
kind="altera_onchip_flash"
version="22.1"
enabled="1">
<parameter name="AUTO_CLOCK_RATE" value="6250000" />
<parameter name="AUTO_CLOCK_RATE" value="25000000" />
<parameter name="CLOCK_FREQUENCY" value="25.0" />
<parameter name="CONFIGURATION_MODE">Single Compressed Image</parameter>
<parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
26 changes: 13 additions & 13 deletions Quartus/IP/flash_interface_10M16SCU169C8G.sopcinfo
Original file line number Diff line number Diff line change
@@ -5,11 +5,11 @@
version="1.0"
fabric="QSYS">
<!-- Format version 22.1 922 (Future versions may contain additional information.) -->
<!-- 2024.11.26.08:50:30 -->
<!-- 2024.12.06.18:20:37 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1732611030</value>
<value>1733509237</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@@ -141,7 +141,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="AUTO_CLK_CLOCK_RATE">
<type>java.lang.Long</type>
<value>6250000</value>
<value>25000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@@ -212,7 +212,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>6250000</value>
<value>25000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
@@ -684,7 +684,7 @@ parameters are a RESULT of the module parameters. -->
the requested settings for a module instance. -->
<parameter name="clockFrequency">
<type>long</type>
<value>6250000</value>
<value>25000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -782,7 +782,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>6250000</value>
<value>25000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
@@ -860,7 +860,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="clockRate">
<type>long</type>
<value>6250000</value>
<value>25000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -1269,7 +1269,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="AUTO_CLOCK_RATE">
<type>long</type>
<value>6250000</value>
<value>25000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@@ -1535,31 +1535,31 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="FLASH_RESET_CYCLE_MAX_INDEX">
<type>int</type>
<value>1</value>
<value>6</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX">
<type>int</type>
<value>7</value>
<value>30</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX">
<type>int</type>
<value>2187500</value>
<value>8750000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
<valid>true</valid>
</parameter>
<parameter name="FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX">
<type>int</type>
<value>1906</value>
<value>7625</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
@@ -1675,7 +1675,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="clockRate">
<type>java.lang.Long</type>
<value>6250000</value>
<value>25000000</value>
<derived>true</derived>
<enabled>true</enabled>
<visible>false</visible>
Original file line number Diff line number Diff line change
@@ -67,7 +67,7 @@
</table>
<table class="blueBar">
<tr>
<td class="l">2024.11.26.08:50:30</td>
<td class="l">2024.12.06.18:20:37</td>
<td class="r">Datasheet</td>
</tr>
</table>
@@ -194,7 +194,7 @@ <h2>Parameters</h2>
</tr>
<tr>
<td class="parametername">AUTO_CLK_CLOCK_RATE</td>
<td class="parametervalue">6250000</td>
<td class="parametervalue">25000000</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
@@ -229,7 +229,7 @@ <h2>Parameters</h2>
<table>
<tr>
<td class="parametername">clockFrequency</td>
<td class="parametervalue">6250000</td>
<td class="parametervalue">25000000</td>
</tr>
<tr>
<td class="parametername">clockFrequencyKnown</td>
@@ -390,7 +390,7 @@ <h2>Parameters</h2>
</tr>
<tr>
<td class="parametername">AUTO_CLOCK_RATE</td>
<td class="parametervalue">6250000</td>
<td class="parametervalue">25000000</td>
</tr>
<tr>
<td class="parametername">DEVICE_ID</td>
@@ -522,19 +522,19 @@ <h2>Parameters</h2>
</tr>
<tr>
<td class="parametername">FLASH_RESET_CYCLE_MAX_INDEX</td>
<td class="parametervalue">1</td>
<td class="parametervalue">6</td>
</tr>
<tr>
<td class="parametername">FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX</td>
<td class="parametervalue">7</td>
<td class="parametervalue">30</td>
</tr>
<tr>
<td class="parametername">FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX</td>
<td class="parametervalue">2187500</td>
<td class="parametervalue">8750000</td>
</tr>
<tr>
<td class="parametername">FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX</td>
<td class="parametervalue">1906</td>
<td class="parametervalue">7625</td>
</tr>
<tr>
<td class="parametername">PARALLEL_MODE</td>
Original file line number Diff line number Diff line change
@@ -0,0 +1,109 @@
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
type="SYSTEM_VERILOG"
library="error_adapter_0" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_avalon_st_adapter.v"
type="VERILOG"
library="avalon_st_adapter" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_rsp_mux.sv"
type="SYSTEM_VERILOG"
library="rsp_mux" />
<file
path="simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="rsp_mux" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_rsp_demux.sv"
type="SYSTEM_VERILOG"
library="rsp_demux" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_cmd_mux.sv"
type="SYSTEM_VERILOG"
library="cmd_mux" />
<file
path="simulation/submodules/altera_merlin_arbitrator.sv"
type="SYSTEM_VERILOG"
library="cmd_mux" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_cmd_demux.sv"
type="SYSTEM_VERILOG"
library="cmd_demux" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_router_001.sv"
type="SYSTEM_VERILOG"
library="router_001" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0_router.sv"
type="SYSTEM_VERILOG"
library="router" />
<file
path="simulation/submodules/altera_avalon_sc_fifo.v"
type="VERILOG"
library="onchip_flash_csr_agent_rsp_fifo" />
<file
path="simulation/submodules/altera_merlin_slave_agent.sv"
type="SYSTEM_VERILOG"
library="onchip_flash_csr_agent" />
<file
path="simulation/submodules/altera_merlin_burst_uncompressor.sv"
type="SYSTEM_VERILOG"
library="onchip_flash_csr_agent" />
<file
path="simulation/submodules/altera_merlin_master_agent.sv"
type="SYSTEM_VERILOG"
library="avalon_bridge_avalon_master_agent" />
<file
path="simulation/submodules/altera_merlin_slave_translator.sv"
type="SYSTEM_VERILOG"
library="onchip_flash_csr_translator" />
<file
path="simulation/submodules/altera_merlin_master_translator.sv"
type="SYSTEM_VERILOG"
library="avalon_bridge_avalon_master_translator" />
<file
path="simulation/submodules/altera_reset_controller.v"
type="VERILOG"
library="rst_controller" />
<file
path="simulation/submodules/altera_reset_synchronizer.v"
type="VERILOG"
library="rst_controller" />
<file
path="simulation/submodules/altera_reset_controller.sdc"
type="SDC"
library="rst_controller" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_mm_interconnect_0.v"
type="VERILOG"
library="mm_interconnect_0" />
<file
path="simulation/submodules/altera_onchip_flash_util.v"
type="VERILOG"
library="onchip_flash" />
<file
path="simulation/submodules/altera_onchip_flash.v"
type="VERILOG"
library="onchip_flash" />
<file
path="simulation/submodules/altera_onchip_flash_avmm_data_controller.v"
type="VERILOG"
library="onchip_flash" />
<file
path="simulation/submodules/altera_onchip_flash_avmm_csr_controller.v"
type="VERILOG"
library="onchip_flash" />
<file
path="simulation/submodules/flash_interface_10M16SCU169C8G_avalon_bridge.v"
type="VERILOG"
library="avalon_bridge" />
<file path="simulation/flash_interface_10M16SCU169C8G.v" type="VERILOG" />
<topLevel name="flash_interface_10M16SCU169C8G" />
<deviceFamily name="max10" />
<modelMap
controllerPath="flash_interface_10M16SCU169C8G.onchip_flash"
modelPath="flash_interface_10M16SCU169C8G.onchip_flash" />
</simPackage>
Original file line number Diff line number Diff line change
@@ -1,3 +1,53 @@
Info: Starting: Create simulation model
Info: qsys-generate C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M16SCU169C8G.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M16SCU169C8G\simulation --family="MAX 10" --part=10M16SCU169C8G
Progress: Loading IP/flash_interface_10M16SCU169C8G.qsys
Progress: Reading input file
Progress: Adding avalon_bridge [altera_up_external_bus_to_avalon_bridge 18.0]
Progress: Parameterizing module avalon_bridge
Progress: Adding clk_source [clock_source 22.1]
Progress: Parameterizing module clk_source
Progress: Adding onchip_flash [altera_onchip_flash 22.1]
Progress: Parameterizing module onchip_flash
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: flash_interface_10M16SCU169C8G: Generating flash_interface_10M16SCU169C8G "flash_interface_10M16SCU169C8G" for SIM_VERILOG
Info: avalon_bridge: Starting Generation of External Bus to Avalon Bridge
Info: avalon_bridge: "flash_interface_10M16SCU169C8G" instantiated altera_up_external_bus_to_avalon_bridge "avalon_bridge"
Info: onchip_flash: "flash_interface_10M16SCU169C8G" instantiated altera_onchip_flash "onchip_flash"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "flash_interface_10M16SCU169C8G" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: rst_controller: "flash_interface_10M16SCU169C8G" instantiated altera_reset_controller "rst_controller"
Info: avalon_bridge_avalon_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "avalon_bridge_avalon_master_translator"
Info: onchip_flash_csr_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "onchip_flash_csr_translator"
Info: avalon_bridge_avalon_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "avalon_bridge_avalon_master_agent"
Info: onchip_flash_csr_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "onchip_flash_csr_agent"
Info: onchip_flash_csr_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "onchip_flash_csr_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M16SCU169C8G/simulation/submodules/altera_merlin_arbitrator.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: flash_interface_10M16SCU169C8G: Done "flash_interface_10M16SCU169C8G" with 18 modules, 25 files
Info: qsys-generate succeeded.
Info: Finished: Create simulation model
Info: Starting: Create Modelsim Project.
Info: sim-script-gen --spd=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M16SCU169C8G\flash_interface_10M16SCU169C8G.spd --output-directory=C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M16SCU169C8G/simulation/ --use-relative-paths=true
Info: Doing: ip-make-simscript --spd=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M16SCU169C8G\flash_interface_10M16SCU169C8G.spd --output-directory=C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M16SCU169C8G/simulation/ --use-relative-paths=true
Info: Generating the following file(s) for RIVIERA simulator in C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M16SCU169C8G/simulation/ directory:
Info: aldec/rivierapro_setup.tcl
Info: Generating the following file(s) for MODELSIM simulator in C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M16SCU169C8G/simulation/ directory:
Info: mentor/msim_setup.tcl
Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M16SCU169C8G/simulation/.
Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
Info: Finished: Create Modelsim Project.
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M16SCU169C8G.qsys --synthesis=VERILOG --output-directory=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M16SCU169C8G\synthesis --family="MAX 10" --part=10M16SCU169C8G
Progress: Loading IP/flash_interface_10M16SCU169C8G.qsys
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