From b3b694ecb9a8f8fa8d8105e8bfe07b1e45940431 Mon Sep 17 00:00:00 2001
From: mbtaylor1982 <mike@dewberryfields.com>
Date: Fri, 6 Dec 2024 18:25:16 +0000
Subject: [PATCH] IP updated for 10M04

---
 ...ash_interface_10M04SCU169C8G_schematic.nlv |   18 +-
 .../flash_interface_10M04SCU169C8G.sopcinfo   |    4 +-
 .../flash_interface_10M04SCU169C8G.html       |    2 +-
 .../flash_interface_10M04SCU169C8G.spd        |  109 ++
 ...sh_interface_10M04SCU169C8G_generation.rpt |   50 +
 ...ace_10M04SCU169C8G_generation_previous.rpt |   40 +
 .../simulation/aldec/rivierapro_setup.tcl     |  326 +++++
 .../flash_interface_10M04SCU169C8G.sip        |   31 +
 .../flash_interface_10M04SCU169C8G.v          |  212 +++
 .../simulation/mentor/msim_setup.tcl          |  320 +++++
 .../submodules/altera_avalon_sc_fifo.v        |  915 ++++++++++++
 .../submodules/altera_merlin_arbitrator.sv    |  272 ++++
 .../altera_merlin_burst_uncompressor.sv       |  296 ++++
 .../submodules/altera_merlin_master_agent.sv  |  303 ++++
 .../altera_merlin_master_translator.sv        |  556 +++++++
 .../submodules/altera_merlin_slave_agent.sv   |  622 ++++++++
 .../altera_merlin_slave_translator.sv         |  482 +++++++
 .../submodules/altera_onchip_flash.v          |  324 +++++
 .../altera_onchip_flash_avmm_csr_controller.v |  182 +++
 ...altera_onchip_flash_avmm_data_controller.v | 1271 +++++++++++++++++
 .../submodules/altera_onchip_flash_util.v     |  270 ++++
 .../submodules/altera_reset_controller.sdc    |   30 +
 .../submodules/altera_reset_controller.v      |  319 +++++
 .../submodules/altera_reset_synchronizer.v    |   87 ++
 ...h_interface_10M04SCU169C8G_avalon_bridge.v |  138 ++
 ...terface_10M04SCU169C8G_mm_interconnect_0.v |  916 ++++++++++++
 ...9C8G_mm_interconnect_0_avalon_st_adapter.v |  202 +++
 ...ect_0_avalon_st_adapter_error_adapter_0.sv |  107 ++
 ...04SCU169C8G_mm_interconnect_0_cmd_demux.sv |  115 ++
 ...0M04SCU169C8G_mm_interconnect_0_cmd_mux.sv |   96 ++
 ...10M04SCU169C8G_mm_interconnect_0_router.sv |  227 +++
 ...4SCU169C8G_mm_interconnect_0_router_001.sv |  215 +++
 ...04SCU169C8G_mm_interconnect_0_rsp_demux.sv |  100 ++
 ...0M04SCU169C8G_mm_interconnect_0_rsp_mux.sv |  345 +++++
 .../flash_interface_10M04SCU169C8G.debuginfo  |    6 +-
 .../flash_interface_10M04SCU169C8G.qip        |    4 +-
 36 files changed, 9495 insertions(+), 17 deletions(-)
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.spd
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation_previous.rpt
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/aldec/rivierapro_setup.tcl
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.sip
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/mentor/msim_setup.tcl
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_avalon_sc_fifo.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_arbitrator.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_burst_uncompressor.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_agent.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_translator.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_agent.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_translator.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_csr_controller.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_data_controller.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_util.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.sdc
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_synchronizer.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv
 create mode 100644 Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv

diff --git a/Quartus/IP/.qsys_edit/flash_interface_10M04SCU169C8G_schematic.nlv b/Quartus/IP/.qsys_edit/flash_interface_10M04SCU169C8G_schematic.nlv
index 174b839..c0b3bc6f 100644
--- a/Quartus/IP/.qsys_edit/flash_interface_10M04SCU169C8G_schematic.nlv
+++ b/Quartus/IP/.qsys_edit/flash_interface_10M04SCU169C8G_schematic.nlv
@@ -1,14 +1,14 @@
 # # File gsaved with Nlview version 6.3.8  2013-12-19 bk=1.2992 VDI=34 GEI=35
 # 
-preplace inst flash_interface_10M04SCU169C8G.clk_source -pg 1 -lvl 1 -y 30
-preplace inst flash_interface_10M04SCU169C8G.avalon_bridge -pg 1 -lvl 2 -y 70
+preplace inst flash_interface_10M04SCU169C8G.clk_source -pg 1 -lvl 1 -y 50
+preplace inst flash_interface_10M04SCU169C8G.avalon_bridge -pg 1 -lvl 2 -y 90
 preplace inst flash_interface_10M04SCU169C8G -pg 1 -lvl 1 -y 40 -regy -20
-preplace inst flash_interface_10M04SCU169C8G.onchip_flash -pg 1 -lvl 3 -y 50
-preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)clk_source.clk,(SLAVE)avalon_bridge.clk,(SLAVE)onchip_flash.clk) 1 1 2 330 60 N
-preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)avalon_bridge.avalon_master,(SLAVE)onchip_flash.data,(SLAVE)onchip_flash.csr) 1 2 1 580
+preplace inst flash_interface_10M04SCU169C8G.onchip_flash -pg 1 -lvl 3 -y 70
 preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)clk_source.clk_in,(SLAVE)flash_interface_10M04SCU169C8G.clk) 1 0 1 NJ
+preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)clk_source.clk_reset,(SLAVE)avalon_bridge.reset,(SLAVE)onchip_flash.nreset) 1 1 2 310 180 620
 preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)flash_interface_10M04SCU169C8G.reset,(SLAVE)clk_source.clk_in_reset) 1 0 1 NJ
-preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.reset,(MASTER)clk_source.clk_reset,(SLAVE)onchip_flash.nreset) 1 1 2 310 160 580
-preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.external_interface,(SLAVE)flash_interface_10M04SCU169C8G.external_interface) 1 0 2 NJ 100 NJ
-levelinfo -pg 1 0 110 710
-levelinfo -hier flash_interface_10M04SCU169C8G 120 150 360 610 700
+preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.clk,(SLAVE)onchip_flash.clk,(MASTER)clk_source.clk) 1 1 2 330 200 600
+preplace netloc EXPORT<net_container>flash_interface_10M04SCU169C8G</net_container>(SLAVE)avalon_bridge.external_interface,(SLAVE)flash_interface_10M04SCU169C8G.external_interface) 1 0 2 NJ 40 NJ
+preplace netloc FAN_OUT<net_container>flash_interface_10M04SCU169C8G</net_container>(MASTER)avalon_bridge.avalon_master,(SLAVE)onchip_flash.csr,(SLAVE)onchip_flash.data) 1 2 1 620
+levelinfo -pg 1 0 110 750
+levelinfo -hier flash_interface_10M04SCU169C8G 120 150 380 650 740
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G.sopcinfo b/Quartus/IP/flash_interface_10M04SCU169C8G.sopcinfo
index 586488b..ecfbfed 100644
--- a/Quartus/IP/flash_interface_10M04SCU169C8G.sopcinfo
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G.sopcinfo
@@ -5,11 +5,11 @@
  version="1.0"
  fabric="QSYS">
  <!-- Format version 22.1 922 (Future versions may contain additional information.) -->
- <!-- 2024.11.11.08:27:21 -->
+ <!-- 2024.12.06.18:24:38 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1731313641</value>
+  <value>1733509478</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.html b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.html
index e7ce5ad..00e67cd 100644
--- a/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.html
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.html
@@ -67,7 +67,7 @@
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2024.11.11.08:27:21</td>
+    <td class="l">2024.12.06.18:24:38</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.spd b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.spd
new file mode 100644
index 0000000..01a0b3e
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G.spd
@@ -0,0 +1,109 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
+   type="SYSTEM_VERILOG"
+   library="error_adapter_0" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v"
+   type="VERILOG"
+   library="avalon_st_adapter" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_mux" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv"
+   type="SYSTEM_VERILOG"
+   library="rsp_demux" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux" />
+ <file
+   path="simulation/submodules/altera_merlin_arbitrator.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_mux" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv"
+   type="SYSTEM_VERILOG"
+   library="cmd_demux" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv"
+   type="SYSTEM_VERILOG"
+   library="router_001" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv"
+   type="SYSTEM_VERILOG"
+   library="router" />
+ <file
+   path="simulation/submodules/altera_avalon_sc_fifo.v"
+   type="VERILOG"
+   library="onchip_flash_csr_agent_rsp_fifo" />
+ <file
+   path="simulation/submodules/altera_merlin_slave_agent.sv"
+   type="SYSTEM_VERILOG"
+   library="onchip_flash_csr_agent" />
+ <file
+   path="simulation/submodules/altera_merlin_burst_uncompressor.sv"
+   type="SYSTEM_VERILOG"
+   library="onchip_flash_csr_agent" />
+ <file
+   path="simulation/submodules/altera_merlin_master_agent.sv"
+   type="SYSTEM_VERILOG"
+   library="avalon_bridge_avalon_master_agent" />
+ <file
+   path="simulation/submodules/altera_merlin_slave_translator.sv"
+   type="SYSTEM_VERILOG"
+   library="onchip_flash_csr_translator" />
+ <file
+   path="simulation/submodules/altera_merlin_master_translator.sv"
+   type="SYSTEM_VERILOG"
+   library="avalon_bridge_avalon_master_translator" />
+ <file
+   path="simulation/submodules/altera_reset_controller.v"
+   type="VERILOG"
+   library="rst_controller" />
+ <file
+   path="simulation/submodules/altera_reset_synchronizer.v"
+   type="VERILOG"
+   library="rst_controller" />
+ <file
+   path="simulation/submodules/altera_reset_controller.sdc"
+   type="SDC"
+   library="rst_controller" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v"
+   type="VERILOG"
+   library="mm_interconnect_0" />
+ <file
+   path="simulation/submodules/altera_onchip_flash_util.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/altera_onchip_flash.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/altera_onchip_flash_avmm_data_controller.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/altera_onchip_flash_avmm_csr_controller.v"
+   type="VERILOG"
+   library="onchip_flash" />
+ <file
+   path="simulation/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v"
+   type="VERILOG"
+   library="avalon_bridge" />
+ <file path="simulation/flash_interface_10M04SCU169C8G.v" type="VERILOG" />
+ <topLevel name="flash_interface_10M04SCU169C8G" />
+ <deviceFamily name="max10" />
+ <modelMap
+   controllerPath="flash_interface_10M04SCU169C8G.onchip_flash"
+   modelPath="flash_interface_10M04SCU169C8G.onchip_flash" />
+</simPackage>
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation.rpt b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation.rpt
index f959fc4..e1aab46 100644
--- a/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation.rpt
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation.rpt
@@ -1,3 +1,53 @@
+Info: Starting: Create simulation model
+Info: qsys-generate C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G\simulation --family="MAX 10" --part=10M04SCU169C8G
+Progress: Loading IP/flash_interface_10M04SCU169C8G.qsys
+Progress: Reading input file
+Progress: Adding avalon_bridge [altera_up_external_bus_to_avalon_bridge 18.0]
+Progress: Parameterizing module avalon_bridge
+Progress: Adding clk_source [clock_source 22.1]
+Progress: Parameterizing module clk_source
+Progress: Adding onchip_flash [altera_onchip_flash 22.1]
+Progress: Parameterizing module onchip_flash
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: flash_interface_10M04SCU169C8G: Generating flash_interface_10M04SCU169C8G "flash_interface_10M04SCU169C8G" for SIM_VERILOG
+Info: avalon_bridge: Starting Generation of External Bus to Avalon Bridge
+Info: avalon_bridge: "flash_interface_10M04SCU169C8G" instantiated altera_up_external_bus_to_avalon_bridge "avalon_bridge"
+Info: onchip_flash: "flash_interface_10M04SCU169C8G" instantiated altera_onchip_flash "onchip_flash"
+Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
+Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
+Info: mm_interconnect_0: "flash_interface_10M04SCU169C8G" instantiated altera_mm_interconnect "mm_interconnect_0"
+Info: rst_controller: "flash_interface_10M04SCU169C8G" instantiated altera_reset_controller "rst_controller"
+Info: avalon_bridge_avalon_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "avalon_bridge_avalon_master_translator"
+Info: onchip_flash_csr_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "onchip_flash_csr_translator"
+Info: avalon_bridge_avalon_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "avalon_bridge_avalon_master_agent"
+Info: onchip_flash_csr_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "onchip_flash_csr_agent"
+Info: onchip_flash_csr_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "onchip_flash_csr_agent_rsp_fifo"
+Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
+Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
+Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
+Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
+Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
+Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
+Info: Reusing file C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_arbitrator.sv
+Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
+Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
+Info: flash_interface_10M04SCU169C8G: Done "flash_interface_10M04SCU169C8G" with 18 modules, 25 files
+Info: qsys-generate succeeded.
+Info: Finished: Create simulation model
+Info: Starting: Create Modelsim Project.
+Info: sim-script-gen --spd=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G\flash_interface_10M04SCU169C8G.spd --output-directory=C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/ --use-relative-paths=true
+Info: Doing: ip-make-simscript --spd=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G\flash_interface_10M04SCU169C8G.spd --output-directory=C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/ --use-relative-paths=true
+Info: Generating the following file(s) for MODELSIM simulator in C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/ directory:
+Info: 	mentor/msim_setup.tcl
+Info: Generating the following file(s) for RIVIERA simulator in C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/ directory:
+Info: 	aldec/rivierapro_setup.tcl
+Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/.
+Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project.
+Info: Finished: Create Modelsim Project.
+Info: 
 Info: Starting: Create HDL design files for synthesis
 Info: qsys-generate C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G.qsys --synthesis=VERILOG --output-directory=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G\synthesis --family="MAX 10" --part=10M04SCU169C8G
 Progress: Loading IP/flash_interface_10M04SCU169C8G.qsys
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation_previous.rpt b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation_previous.rpt
new file mode 100644
index 0000000..f959fc4
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/flash_interface_10M04SCU169C8G_generation_previous.rpt
@@ -0,0 +1,40 @@
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G.qsys --synthesis=VERILOG --output-directory=C:\Users\mbtay\SDMAC-Replacement\Quartus\IP\flash_interface_10M04SCU169C8G\synthesis --family="MAX 10" --part=10M04SCU169C8G
+Progress: Loading IP/flash_interface_10M04SCU169C8G.qsys
+Progress: Reading input file
+Progress: Adding avalon_bridge [altera_up_external_bus_to_avalon_bridge 18.0]
+Progress: Parameterizing module avalon_bridge
+Progress: Adding clk_source [clock_source 22.1]
+Progress: Parameterizing module clk_source
+Progress: Adding onchip_flash [altera_onchip_flash 22.1]
+Progress: Parameterizing module onchip_flash
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: flash_interface_10M04SCU169C8G: Generating flash_interface_10M04SCU169C8G "flash_interface_10M04SCU169C8G" for QUARTUS_SYNTH
+Info: avalon_bridge: Starting Generation of External Bus to Avalon Bridge
+Info: avalon_bridge: "flash_interface_10M04SCU169C8G" instantiated altera_up_external_bus_to_avalon_bridge "avalon_bridge"
+Info: onchip_flash: Generating top-level entity altera_onchip_flash
+Info: onchip_flash: "flash_interface_10M04SCU169C8G" instantiated altera_onchip_flash "onchip_flash"
+Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
+Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
+Info: mm_interconnect_0: "flash_interface_10M04SCU169C8G" instantiated altera_mm_interconnect "mm_interconnect_0"
+Info: rst_controller: "flash_interface_10M04SCU169C8G" instantiated altera_reset_controller "rst_controller"
+Info: avalon_bridge_avalon_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "avalon_bridge_avalon_master_translator"
+Info: onchip_flash_csr_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "onchip_flash_csr_translator"
+Info: avalon_bridge_avalon_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "avalon_bridge_avalon_master_agent"
+Info: onchip_flash_csr_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "onchip_flash_csr_agent"
+Info: onchip_flash_csr_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "onchip_flash_csr_agent_rsp_fifo"
+Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
+Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
+Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
+Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
+Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
+Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
+Info: Reusing file C:/Users/mbtay/SDMAC-Replacement/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/submodules/altera_merlin_arbitrator.sv
+Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
+Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
+Info: flash_interface_10M04SCU169C8G: Done "flash_interface_10M04SCU169C8G" with 18 modules, 27 files
+Info: qsys-generate succeeded.
+Info: Finished: Create HDL design files for synthesis
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/aldec/rivierapro_setup.tcl b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/aldec/rivierapro_setup.tcl
new file mode 100644
index 0000000..d7efee3
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/aldec/rivierapro_setup.tcl
@@ -0,0 +1,326 @@
+
+# (C) 2001-2024 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 22.1 922 win32 2024.12.06.18:24:38
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     flash_interface_10M04SCU169C8G
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If flash_interface_10M04SCU169C8G is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "flash_interface_10M04SCU169C8G"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/22.1std/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib                  ./libraries/altera_ver      
+vmap       altera_ver       ./libraries/altera_ver      
+ensure_lib                  ./libraries/lpm_ver         
+vmap       lpm_ver          ./libraries/lpm_ver         
+ensure_lib                  ./libraries/sgate_ver       
+vmap       sgate_ver        ./libraries/sgate_ver       
+ensure_lib                  ./libraries/altera_mf_ver   
+vmap       altera_mf_ver    ./libraries/altera_mf_ver   
+ensure_lib                  ./libraries/altera_lnsim_ver
+vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver
+ensure_lib                  ./libraries/fiftyfivenm_ver 
+vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver 
+ensure_lib                                        ./libraries/error_adapter_0                       
+vmap       error_adapter_0                        ./libraries/error_adapter_0                       
+ensure_lib                                        ./libraries/avalon_st_adapter                     
+vmap       avalon_st_adapter                      ./libraries/avalon_st_adapter                     
+ensure_lib                                        ./libraries/rsp_mux                               
+vmap       rsp_mux                                ./libraries/rsp_mux                               
+ensure_lib                                        ./libraries/rsp_demux                             
+vmap       rsp_demux                              ./libraries/rsp_demux                             
+ensure_lib                                        ./libraries/cmd_mux                               
+vmap       cmd_mux                                ./libraries/cmd_mux                               
+ensure_lib                                        ./libraries/cmd_demux                             
+vmap       cmd_demux                              ./libraries/cmd_demux                             
+ensure_lib                                        ./libraries/router_001                            
+vmap       router_001                             ./libraries/router_001                            
+ensure_lib                                        ./libraries/router                                
+vmap       router                                 ./libraries/router                                
+ensure_lib                                        ./libraries/onchip_flash_csr_agent_rsp_fifo       
+vmap       onchip_flash_csr_agent_rsp_fifo        ./libraries/onchip_flash_csr_agent_rsp_fifo       
+ensure_lib                                        ./libraries/onchip_flash_csr_agent                
+vmap       onchip_flash_csr_agent                 ./libraries/onchip_flash_csr_agent                
+ensure_lib                                        ./libraries/avalon_bridge_avalon_master_agent     
+vmap       avalon_bridge_avalon_master_agent      ./libraries/avalon_bridge_avalon_master_agent     
+ensure_lib                                        ./libraries/onchip_flash_csr_translator           
+vmap       onchip_flash_csr_translator            ./libraries/onchip_flash_csr_translator           
+ensure_lib                                        ./libraries/avalon_bridge_avalon_master_translator
+vmap       avalon_bridge_avalon_master_translator ./libraries/avalon_bridge_avalon_master_translator
+ensure_lib                                        ./libraries/rst_controller                        
+vmap       rst_controller                         ./libraries/rst_controller                        
+ensure_lib                                        ./libraries/mm_interconnect_0                     
+vmap       mm_interconnect_0                      ./libraries/mm_interconnect_0                     
+ensure_lib                                        ./libraries/onchip_flash                          
+vmap       onchip_flash                           ./libraries/onchip_flash                          
+ensure_lib                                        ./libraries/avalon_bridge                         
+vmap       avalon_bridge                          ./libraries/avalon_bridge                         
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"              -work altera_ver      
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                       -work lpm_ver         
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                          -work sgate_ver       
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                      -work altera_mf_ver   
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim_ver
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"              -work fiftyfivenm_ver 
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -work error_adapter_0                       
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v"                  -work avalon_st_adapter                     
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv"                           -work rsp_mux                               
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/altera_merlin_arbitrator.sv"                                                           -work rsp_mux                               
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv"                         -work rsp_demux                             
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv"                           -work cmd_mux                               
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/altera_merlin_arbitrator.sv"                                                           -work cmd_mux                               
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv"                         -work cmd_demux                             
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv"                        -work router_001                            
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv"                            -work router                                
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_avalon_sc_fifo.v"                                                               -work onchip_flash_csr_agent_rsp_fifo       
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/altera_merlin_slave_agent.sv"                                                          -work onchip_flash_csr_agent                
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/altera_merlin_burst_uncompressor.sv"                                                   -work onchip_flash_csr_agent                
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/altera_merlin_master_agent.sv"                                                         -work avalon_bridge_avalon_master_agent     
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/altera_merlin_slave_translator.sv"                                                     -work onchip_flash_csr_translator           
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QSYS_SIMDIR/submodules/altera_merlin_master_translator.sv"                                                    -work avalon_bridge_avalon_master_translator
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_reset_controller.v"                                                             -work rst_controller                        
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_reset_synchronizer.v"                                                           -work rst_controller                        
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v"                                    -work mm_interconnect_0                     
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_onchip_flash_util.v"                                                            -work onchip_flash                          
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_onchip_flash.v"                                                                 -work onchip_flash                          
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_onchip_flash_avmm_data_controller.v"                                            -work onchip_flash                          
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_onchip_flash_avmm_csr_controller.v"                                             -work onchip_flash                          
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v"                                        -work avalon_bridge                         
+  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/flash_interface_10M04SCU169C8G.v"                                                                                                             
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L error_adapter_0 -L avalon_st_adapter -L rsp_mux -L rsp_demux -L cmd_mux -L cmd_demux -L router_001 -L router -L onchip_flash_csr_agent_rsp_fifo -L onchip_flash_csr_agent -L avalon_bridge_avalon_master_agent -L onchip_flash_csr_translator -L avalon_bridge_avalon_master_translator -L rst_controller -L mm_interconnect_0 -L onchip_flash -L avalon_bridge -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L error_adapter_0 -L avalon_st_adapter -L rsp_mux -L rsp_demux -L cmd_mux -L cmd_demux -L router_001 -L router -L onchip_flash_csr_agent_rsp_fifo -L onchip_flash_csr_agent -L avalon_bridge_avalon_master_agent -L onchip_flash_csr_translator -L avalon_bridge_avalon_master_translator -L rst_controller -L mm_interconnect_0 -L onchip_flash -L avalon_bridge -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.sip b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.sip
new file mode 100644
index 0000000..76f06b3
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.sip
@@ -0,0 +1,31 @@
+set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "lib_flash_interface_10M04SCU169C8G" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "lib_flash_interface_10M04SCU169C8G" -name IP_TOOL_VERSION "22.1"
+set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "lib_flash_interface_10M04SCU169C8G" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name SPD_FILE [file join $::quartus(sip_path) "../flash_interface_10M04SCU169C8G.spd"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "../../flash_interface_10M04SCU169C8G.qsys"]
+
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "flash_interface_10M04SCU169C8G.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_reset_controller.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_reset_synchronizer.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_reset_controller.sdc"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_merlin_arbitrator.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_avalon_sc_fifo.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_merlin_slave_agent.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_merlin_burst_uncompressor.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_merlin_master_agent.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_merlin_slave_translator.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_merlin_master_translator.sv"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash_util.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash_avmm_data_controller.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_onchip_flash_avmm_csr_controller.v"]
+set_global_assignment -library "lib_flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(sip_path) "submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v"]
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.v
new file mode 100644
index 0000000..7f031a2
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/flash_interface_10M04SCU169C8G.v
@@ -0,0 +1,212 @@
+// flash_interface_10M04SCU169C8G.v
+
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module flash_interface_10M04SCU169C8G (
+		input  wire        clk_clk,                        //                clk.clk
+		input  wire [23:0] external_interface_address,     // external_interface.address
+		input  wire [3:0]  external_interface_byte_enable, //                   .byte_enable
+		input  wire        external_interface_read,        //                   .read
+		input  wire        external_interface_write,       //                   .write
+		input  wire [31:0] external_interface_write_data,  //                   .write_data
+		output wire        external_interface_acknowledge, //                   .acknowledge
+		output wire [31:0] external_interface_read_data,   //                   .read_data
+		input  wire        reset_reset_n                   //              reset.reset_n
+	);
+
+	wire  [31:0] avalon_bridge_avalon_master_readdata;              // mm_interconnect_0:avalon_bridge_avalon_master_readdata -> avalon_bridge:avalon_readdata
+	wire         avalon_bridge_avalon_master_waitrequest;           // mm_interconnect_0:avalon_bridge_avalon_master_waitrequest -> avalon_bridge:avalon_waitrequest
+	wire   [3:0] avalon_bridge_avalon_master_byteenable;            // avalon_bridge:avalon_byteenable -> mm_interconnect_0:avalon_bridge_avalon_master_byteenable
+	wire         avalon_bridge_avalon_master_read;                  // avalon_bridge:avalon_read -> mm_interconnect_0:avalon_bridge_avalon_master_read
+	wire  [23:0] avalon_bridge_avalon_master_address;               // avalon_bridge:avalon_address -> mm_interconnect_0:avalon_bridge_avalon_master_address
+	wire         avalon_bridge_avalon_master_write;                 // avalon_bridge:avalon_write -> mm_interconnect_0:avalon_bridge_avalon_master_write
+	wire  [31:0] avalon_bridge_avalon_master_writedata;             // avalon_bridge:avalon_writedata -> mm_interconnect_0:avalon_bridge_avalon_master_writedata
+	wire  [31:0] mm_interconnect_0_onchip_flash_csr_readdata;       // onchip_flash:avmm_csr_readdata -> mm_interconnect_0:onchip_flash_csr_readdata
+	wire   [0:0] mm_interconnect_0_onchip_flash_csr_address;        // mm_interconnect_0:onchip_flash_csr_address -> onchip_flash:avmm_csr_addr
+	wire         mm_interconnect_0_onchip_flash_csr_read;           // mm_interconnect_0:onchip_flash_csr_read -> onchip_flash:avmm_csr_read
+	wire         mm_interconnect_0_onchip_flash_csr_write;          // mm_interconnect_0:onchip_flash_csr_write -> onchip_flash:avmm_csr_write
+	wire  [31:0] mm_interconnect_0_onchip_flash_csr_writedata;      // mm_interconnect_0:onchip_flash_csr_writedata -> onchip_flash:avmm_csr_writedata
+	wire  [31:0] mm_interconnect_0_onchip_flash_data_readdata;      // onchip_flash:avmm_data_readdata -> mm_interconnect_0:onchip_flash_data_readdata
+	wire         mm_interconnect_0_onchip_flash_data_waitrequest;   // onchip_flash:avmm_data_waitrequest -> mm_interconnect_0:onchip_flash_data_waitrequest
+	wire  [15:0] mm_interconnect_0_onchip_flash_data_address;       // mm_interconnect_0:onchip_flash_data_address -> onchip_flash:avmm_data_addr
+	wire         mm_interconnect_0_onchip_flash_data_read;          // mm_interconnect_0:onchip_flash_data_read -> onchip_flash:avmm_data_read
+	wire         mm_interconnect_0_onchip_flash_data_readdatavalid; // onchip_flash:avmm_data_readdatavalid -> mm_interconnect_0:onchip_flash_data_readdatavalid
+	wire         mm_interconnect_0_onchip_flash_data_write;         // mm_interconnect_0:onchip_flash_data_write -> onchip_flash:avmm_data_write
+	wire  [31:0] mm_interconnect_0_onchip_flash_data_writedata;     // mm_interconnect_0:onchip_flash_data_writedata -> onchip_flash:avmm_data_writedata
+	wire   [3:0] mm_interconnect_0_onchip_flash_data_burstcount;    // mm_interconnect_0:onchip_flash_data_burstcount -> onchip_flash:avmm_data_burstcount
+	wire         rst_controller_reset_out_reset;                    // rst_controller:reset_out -> [avalon_bridge:reset, mm_interconnect_0:avalon_bridge_reset_reset_bridge_in_reset_reset, onchip_flash:reset_n]
+
+	flash_interface_10M04SCU169C8G_avalon_bridge avalon_bridge (
+		.clk                (clk_clk),                                 //                clk.clk
+		.reset              (rst_controller_reset_out_reset),          //              reset.reset
+		.avalon_readdata    (avalon_bridge_avalon_master_readdata),    //      avalon_master.readdata
+		.avalon_waitrequest (avalon_bridge_avalon_master_waitrequest), //                   .waitrequest
+		.avalon_byteenable  (avalon_bridge_avalon_master_byteenable),  //                   .byteenable
+		.avalon_read        (avalon_bridge_avalon_master_read),        //                   .read
+		.avalon_write       (avalon_bridge_avalon_master_write),       //                   .write
+		.avalon_writedata   (avalon_bridge_avalon_master_writedata),   //                   .writedata
+		.avalon_address     (avalon_bridge_avalon_master_address),     //                   .address
+		.address            (external_interface_address),              // external_interface.export
+		.byte_enable        (external_interface_byte_enable),          //                   .export
+		.read               (external_interface_read),                 //                   .export
+		.write              (external_interface_write),                //                   .export
+		.write_data         (external_interface_write_data),           //                   .export
+		.acknowledge        (external_interface_acknowledge),          //                   .export
+		.read_data          (external_interface_read_data)             //                   .export
+	);
+
+	altera_onchip_flash #(
+		.INIT_FILENAME                       (""),
+		.INIT_FILENAME_SIM                   (""),
+		.DEVICE_FAMILY                       ("MAX 10"),
+		.PART_NAME                           ("10M04SCU169C8G"),
+		.DEVICE_ID                           ("04"),
+		.SECTOR1_START_ADDR                  (0),
+		.SECTOR1_END_ADDR                    (4095),
+		.SECTOR2_START_ADDR                  (4096),
+		.SECTOR2_END_ADDR                    (18943),
+		.SECTOR3_START_ADDR                  (18944),
+		.SECTOR3_END_ADDR                    (54783),
+		.SECTOR4_START_ADDR                  (0),
+		.SECTOR4_END_ADDR                    (0),
+		.SECTOR5_START_ADDR                  (0),
+		.SECTOR5_END_ADDR                    (0),
+		.MIN_VALID_ADDR                      (0),
+		.MAX_VALID_ADDR                      (54783),
+		.MIN_UFM_VALID_ADDR                  (0),
+		.MAX_UFM_VALID_ADDR                  (18943),
+		.SECTOR1_MAP                         (2),
+		.SECTOR2_MAP                         (4),
+		.SECTOR3_MAP                         (5),
+		.SECTOR4_MAP                         (0),
+		.SECTOR5_MAP                         (0),
+		.ADDR_RANGE1_END_ADDR                (4095),
+		.ADDR_RANGE2_END_ADDR                (54783),
+		.ADDR_RANGE1_OFFSET                  (4608),
+		.ADDR_RANGE2_OFFSET                  (25600),
+		.ADDR_RANGE3_OFFSET                  (0),
+		.AVMM_DATA_ADDR_WIDTH                (16),
+		.AVMM_DATA_DATA_WIDTH                (32),
+		.AVMM_DATA_BURSTCOUNT_WIDTH          (4),
+		.SECTOR_READ_PROTECTION_MODE         (24),
+		.FLASH_SEQ_READ_DATA_COUNT           (2),
+		.FLASH_ADDR_ALIGNMENT_BITS           (1),
+		.FLASH_READ_CYCLE_MAX_INDEX          (4),
+		.FLASH_RESET_CYCLE_MAX_INDEX         (6),
+		.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX  (30),
+		.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (8750000),
+		.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (7625),
+		.PARALLEL_MODE                       (1),
+		.READ_AND_WRITE_MODE                 (1),
+		.WRAPPING_BURST_MODE                 (0),
+		.IS_DUAL_BOOT                        ("False"),
+		.IS_ERAM_SKIP                        ("True"),
+		.IS_COMPRESSED_IMAGE                 ("True")
+	) onchip_flash (
+		.clock                   (clk_clk),                                           //    clk.clk
+		.reset_n                 (~rst_controller_reset_out_reset),                   // nreset.reset_n
+		.avmm_data_addr          (mm_interconnect_0_onchip_flash_data_address),       //   data.address
+		.avmm_data_read          (mm_interconnect_0_onchip_flash_data_read),          //       .read
+		.avmm_data_writedata     (mm_interconnect_0_onchip_flash_data_writedata),     //       .writedata
+		.avmm_data_write         (mm_interconnect_0_onchip_flash_data_write),         //       .write
+		.avmm_data_readdata      (mm_interconnect_0_onchip_flash_data_readdata),      //       .readdata
+		.avmm_data_waitrequest   (mm_interconnect_0_onchip_flash_data_waitrequest),   //       .waitrequest
+		.avmm_data_readdatavalid (mm_interconnect_0_onchip_flash_data_readdatavalid), //       .readdatavalid
+		.avmm_data_burstcount    (mm_interconnect_0_onchip_flash_data_burstcount),    //       .burstcount
+		.avmm_csr_addr           (mm_interconnect_0_onchip_flash_csr_address),        //    csr.address
+		.avmm_csr_read           (mm_interconnect_0_onchip_flash_csr_read),           //       .read
+		.avmm_csr_writedata      (mm_interconnect_0_onchip_flash_csr_writedata),      //       .writedata
+		.avmm_csr_write          (mm_interconnect_0_onchip_flash_csr_write),          //       .write
+		.avmm_csr_readdata       (mm_interconnect_0_onchip_flash_csr_readdata)        //       .readdata
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0 mm_interconnect_0 (
+		.clk_source_clk_clk                              (clk_clk),                                           //                            clk_source_clk.clk
+		.avalon_bridge_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset),                    // avalon_bridge_reset_reset_bridge_in_reset.reset
+		.avalon_bridge_avalon_master_address             (avalon_bridge_avalon_master_address),               //               avalon_bridge_avalon_master.address
+		.avalon_bridge_avalon_master_waitrequest         (avalon_bridge_avalon_master_waitrequest),           //                                          .waitrequest
+		.avalon_bridge_avalon_master_byteenable          (avalon_bridge_avalon_master_byteenable),            //                                          .byteenable
+		.avalon_bridge_avalon_master_read                (avalon_bridge_avalon_master_read),                  //                                          .read
+		.avalon_bridge_avalon_master_readdata            (avalon_bridge_avalon_master_readdata),              //                                          .readdata
+		.avalon_bridge_avalon_master_write               (avalon_bridge_avalon_master_write),                 //                                          .write
+		.avalon_bridge_avalon_master_writedata           (avalon_bridge_avalon_master_writedata),             //                                          .writedata
+		.onchip_flash_csr_address                        (mm_interconnect_0_onchip_flash_csr_address),        //                          onchip_flash_csr.address
+		.onchip_flash_csr_write                          (mm_interconnect_0_onchip_flash_csr_write),          //                                          .write
+		.onchip_flash_csr_read                           (mm_interconnect_0_onchip_flash_csr_read),           //                                          .read
+		.onchip_flash_csr_readdata                       (mm_interconnect_0_onchip_flash_csr_readdata),       //                                          .readdata
+		.onchip_flash_csr_writedata                      (mm_interconnect_0_onchip_flash_csr_writedata),      //                                          .writedata
+		.onchip_flash_data_address                       (mm_interconnect_0_onchip_flash_data_address),       //                         onchip_flash_data.address
+		.onchip_flash_data_write                         (mm_interconnect_0_onchip_flash_data_write),         //                                          .write
+		.onchip_flash_data_read                          (mm_interconnect_0_onchip_flash_data_read),          //                                          .read
+		.onchip_flash_data_readdata                      (mm_interconnect_0_onchip_flash_data_readdata),      //                                          .readdata
+		.onchip_flash_data_writedata                     (mm_interconnect_0_onchip_flash_data_writedata),     //                                          .writedata
+		.onchip_flash_data_burstcount                    (mm_interconnect_0_onchip_flash_data_burstcount),    //                                          .burstcount
+		.onchip_flash_data_readdatavalid                 (mm_interconnect_0_onchip_flash_data_readdatavalid), //                                          .readdatavalid
+		.onchip_flash_data_waitrequest                   (mm_interconnect_0_onchip_flash_data_waitrequest)    //                                          .waitrequest
+	);
+
+	altera_reset_controller #(
+		.NUM_RESET_INPUTS          (1),
+		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
+		.SYNC_DEPTH                (2),
+		.RESET_REQUEST_PRESENT     (0),
+		.RESET_REQ_WAIT_TIME       (1),
+		.MIN_RST_ASSERTION_TIME    (3),
+		.RESET_REQ_EARLY_DSRT_TIME (1),
+		.USE_RESET_REQUEST_IN0     (0),
+		.USE_RESET_REQUEST_IN1     (0),
+		.USE_RESET_REQUEST_IN2     (0),
+		.USE_RESET_REQUEST_IN3     (0),
+		.USE_RESET_REQUEST_IN4     (0),
+		.USE_RESET_REQUEST_IN5     (0),
+		.USE_RESET_REQUEST_IN6     (0),
+		.USE_RESET_REQUEST_IN7     (0),
+		.USE_RESET_REQUEST_IN8     (0),
+		.USE_RESET_REQUEST_IN9     (0),
+		.USE_RESET_REQUEST_IN10    (0),
+		.USE_RESET_REQUEST_IN11    (0),
+		.USE_RESET_REQUEST_IN12    (0),
+		.USE_RESET_REQUEST_IN13    (0),
+		.USE_RESET_REQUEST_IN14    (0),
+		.USE_RESET_REQUEST_IN15    (0),
+		.ADAPT_RESET_REQUEST       (0)
+	) rst_controller (
+		.reset_in0      (~reset_reset_n),                 // reset_in0.reset
+		.clk            (clk_clk),                        //       clk.clk
+		.reset_out      (rst_controller_reset_out_reset), // reset_out.reset
+		.reset_req      (),                               // (terminated)
+		.reset_req_in0  (1'b0),                           // (terminated)
+		.reset_in1      (1'b0),                           // (terminated)
+		.reset_req_in1  (1'b0),                           // (terminated)
+		.reset_in2      (1'b0),                           // (terminated)
+		.reset_req_in2  (1'b0),                           // (terminated)
+		.reset_in3      (1'b0),                           // (terminated)
+		.reset_req_in3  (1'b0),                           // (terminated)
+		.reset_in4      (1'b0),                           // (terminated)
+		.reset_req_in4  (1'b0),                           // (terminated)
+		.reset_in5      (1'b0),                           // (terminated)
+		.reset_req_in5  (1'b0),                           // (terminated)
+		.reset_in6      (1'b0),                           // (terminated)
+		.reset_req_in6  (1'b0),                           // (terminated)
+		.reset_in7      (1'b0),                           // (terminated)
+		.reset_req_in7  (1'b0),                           // (terminated)
+		.reset_in8      (1'b0),                           // (terminated)
+		.reset_req_in8  (1'b0),                           // (terminated)
+		.reset_in9      (1'b0),                           // (terminated)
+		.reset_req_in9  (1'b0),                           // (terminated)
+		.reset_in10     (1'b0),                           // (terminated)
+		.reset_req_in10 (1'b0),                           // (terminated)
+		.reset_in11     (1'b0),                           // (terminated)
+		.reset_req_in11 (1'b0),                           // (terminated)
+		.reset_in12     (1'b0),                           // (terminated)
+		.reset_req_in12 (1'b0),                           // (terminated)
+		.reset_in13     (1'b0),                           // (terminated)
+		.reset_req_in13 (1'b0),                           // (terminated)
+		.reset_in14     (1'b0),                           // (terminated)
+		.reset_req_in14 (1'b0),                           // (terminated)
+		.reset_in15     (1'b0),                           // (terminated)
+		.reset_req_in15 (1'b0)                            // (terminated)
+	);
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/mentor/msim_setup.tcl b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/mentor/msim_setup.tcl
new file mode 100644
index 0000000..7f2779b
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/mentor/msim_setup.tcl
@@ -0,0 +1,320 @@
+
+# (C) 2001-2024 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     flash_interface_10M04SCU169C8G
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If flash_interface_10M04SCU169C8G is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 22.1 922 win32 2024.12.06.18:24:37
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "flash_interface_10M04SCU169C8G"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "C:/intelfpga_lite/22.1std/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
+  ensure_lib                  ./libraries/altera_ver/      
+  vmap       altera_ver       ./libraries/altera_ver/      
+  ensure_lib                  ./libraries/lpm_ver/         
+  vmap       lpm_ver          ./libraries/lpm_ver/         
+  ensure_lib                  ./libraries/sgate_ver/       
+  vmap       sgate_ver        ./libraries/sgate_ver/       
+  ensure_lib                  ./libraries/altera_mf_ver/   
+  vmap       altera_mf_ver    ./libraries/altera_mf_ver/   
+  ensure_lib                  ./libraries/altera_lnsim_ver/
+  vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver/
+  ensure_lib                  ./libraries/fiftyfivenm_ver/ 
+  vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver/ 
+}
+ensure_lib                                        ./libraries/error_adapter_0/                       
+vmap       error_adapter_0                        ./libraries/error_adapter_0/                       
+ensure_lib                                        ./libraries/avalon_st_adapter/                     
+vmap       avalon_st_adapter                      ./libraries/avalon_st_adapter/                     
+ensure_lib                                        ./libraries/rsp_mux/                               
+vmap       rsp_mux                                ./libraries/rsp_mux/                               
+ensure_lib                                        ./libraries/rsp_demux/                             
+vmap       rsp_demux                              ./libraries/rsp_demux/                             
+ensure_lib                                        ./libraries/cmd_mux/                               
+vmap       cmd_mux                                ./libraries/cmd_mux/                               
+ensure_lib                                        ./libraries/cmd_demux/                             
+vmap       cmd_demux                              ./libraries/cmd_demux/                             
+ensure_lib                                        ./libraries/router_001/                            
+vmap       router_001                             ./libraries/router_001/                            
+ensure_lib                                        ./libraries/router/                                
+vmap       router                                 ./libraries/router/                                
+ensure_lib                                        ./libraries/onchip_flash_csr_agent_rsp_fifo/       
+vmap       onchip_flash_csr_agent_rsp_fifo        ./libraries/onchip_flash_csr_agent_rsp_fifo/       
+ensure_lib                                        ./libraries/onchip_flash_csr_agent/                
+vmap       onchip_flash_csr_agent                 ./libraries/onchip_flash_csr_agent/                
+ensure_lib                                        ./libraries/avalon_bridge_avalon_master_agent/     
+vmap       avalon_bridge_avalon_master_agent      ./libraries/avalon_bridge_avalon_master_agent/     
+ensure_lib                                        ./libraries/onchip_flash_csr_translator/           
+vmap       onchip_flash_csr_translator            ./libraries/onchip_flash_csr_translator/           
+ensure_lib                                        ./libraries/avalon_bridge_avalon_master_translator/
+vmap       avalon_bridge_avalon_master_translator ./libraries/avalon_bridge_avalon_master_translator/
+ensure_lib                                        ./libraries/rst_controller/                        
+vmap       rst_controller                         ./libraries/rst_controller/                        
+ensure_lib                                        ./libraries/mm_interconnect_0/                     
+vmap       mm_interconnect_0                      ./libraries/mm_interconnect_0/                     
+ensure_lib                                        ./libraries/onchip_flash/                          
+vmap       onchip_flash                           ./libraries/onchip_flash/                          
+ensure_lib                                        ./libraries/avalon_bridge/                         
+vmap       avalon_bridge                          ./libraries/avalon_bridge/                         
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                       -work altera_mf_ver   
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                   -work altera_lnsim_ver
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"               -work fiftyfivenm_ver 
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -work error_adapter_0                       
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v"                  -work avalon_st_adapter                     
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv"                           -work rsp_mux                               
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_merlin_arbitrator.sv"                                                           -work rsp_mux                               
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv"                         -work rsp_demux                             
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv"                           -work cmd_mux                               
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_merlin_arbitrator.sv"                                                           -work cmd_mux                               
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv"                         -work cmd_demux                             
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv"                        -work router_001                            
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv"                            -work router                                
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/altera_avalon_sc_fifo.v"                                                               -work onchip_flash_csr_agent_rsp_fifo       
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_merlin_slave_agent.sv"                                                          -work onchip_flash_csr_agent                
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_merlin_burst_uncompressor.sv"                                                   -work onchip_flash_csr_agent                
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_merlin_master_agent.sv"                                                         -work avalon_bridge_avalon_master_agent     
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_merlin_slave_translator.sv"                                                     -work onchip_flash_csr_translator           
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/altera_merlin_master_translator.sv"                                                    -work avalon_bridge_avalon_master_translator
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/altera_reset_controller.v"                                                             -work rst_controller                        
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/altera_reset_synchronizer.v"                                                           -work rst_controller                        
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v"                                    -work mm_interconnect_0                     
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/altera_onchip_flash_util.v"                                                            -work onchip_flash                          
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/altera_onchip_flash.v"                                                                 -work onchip_flash                          
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/altera_onchip_flash_avmm_data_controller.v"                                            -work onchip_flash                          
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/altera_onchip_flash_avmm_csr_controller.v"                                             -work onchip_flash                          
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v"                                        -work avalon_bridge                         
+  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/flash_interface_10M04SCU169C8G.v"                                                                                                             
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L error_adapter_0 -L avalon_st_adapter -L rsp_mux -L rsp_demux -L cmd_mux -L cmd_demux -L router_001 -L router -L onchip_flash_csr_agent_rsp_fifo -L onchip_flash_csr_agent -L avalon_bridge_avalon_master_agent -L onchip_flash_csr_translator -L avalon_bridge_avalon_master_translator -L rst_controller -L mm_interconnect_0 -L onchip_flash -L avalon_bridge -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L error_adapter_0 -L avalon_st_adapter -L rsp_mux -L rsp_demux -L cmd_mux -L cmd_demux -L router_001 -L router -L onchip_flash_csr_agent_rsp_fifo -L onchip_flash_csr_agent -L avalon_bridge_avalon_master_agent -L onchip_flash_csr_translator -L avalon_bridge_avalon_master_translator -L rst_controller -L mm_interconnect_0 -L onchip_flash -L avalon_bridge -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_avalon_sc_fifo.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_avalon_sc_fifo.v
new file mode 100644
index 0000000..cf8576a
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_avalon_sc_fifo.v
@@ -0,0 +1,915 @@
+// -----------------------------------------------------------
+// Legal Notice: (C)2007 Altera Corporation. All rights reserved.  Your
+// use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any
+// output files any of the foregoing (including device programming or
+// simulation files), and any associated documentation or information are
+// expressly subject to the terms and conditions of the Altera Program
+// License Subscription Agreement or other applicable license agreement,
+// including, without limitation, that your use is for the sole purpose
+// of programming logic devices manufactured by Altera and sold by Altera
+// or its authorized distributors.  Please refer to the applicable
+// agreement for further details.
+//
+// Description: Single clock Avalon-ST FIFO.
+// -----------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+//altera message_off 10036
+module altera_avalon_sc_fifo
+#(
+    // --------------------------------------------------
+    // Parameters
+    // --------------------------------------------------
+    parameter SYMBOLS_PER_BEAT  = 1,
+    parameter BITS_PER_SYMBOL   = 8,
+    parameter FIFO_DEPTH        = 16,
+    parameter CHANNEL_WIDTH     = 0,
+    parameter ERROR_WIDTH       = 0,
+    parameter USE_PACKETS       = 0,
+    parameter USE_FILL_LEVEL    = 0,
+    parameter USE_STORE_FORWARD = 0,
+    parameter USE_ALMOST_FULL_IF = 0,
+    parameter USE_ALMOST_EMPTY_IF = 0,
+
+    // --------------------------------------------------
+    // Empty latency is defined as the number of cycles
+    // required for a write to deassert the empty flag.
+    // For example, a latency of 1 means that the empty
+    // flag is deasserted on the cycle after a write.
+    //
+    // Another way to think of it is the latency for a
+    // write to propagate to the output. 
+    // 
+    // An empty latency of 0 implies lookahead, which is
+    // only implemented for the register-based FIFO.
+    // --------------------------------------------------
+    parameter EMPTY_LATENCY     = 3,
+    parameter USE_MEMORY_BLOCKS = 1,
+
+    // --------------------------------------------------
+    // Internal Parameters
+    // --------------------------------------------------
+    parameter DATA_WIDTH  = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+    parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+    // --------------------------------------------------
+    // Ports
+    // --------------------------------------------------
+    input                       clk,
+    input                       reset,
+
+    input [DATA_WIDTH-1: 0]     in_data,
+    input                       in_valid,
+    input                       in_startofpacket,
+    input                       in_endofpacket,
+    input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]     in_empty,
+    input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]     in_error,
+    input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0]  in_channel,
+    output                      in_ready,
+
+    output [DATA_WIDTH-1 : 0]   out_data,
+    output reg                  out_valid,
+    output                      out_startofpacket,
+    output                      out_endofpacket,
+    output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0]    out_empty,
+    output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0]    out_error,
+    output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
+    input                       out_ready,
+
+    input [(USE_STORE_FORWARD ? 2 : 1) : 0]   csr_address,
+    input                       csr_write,
+    input                       csr_read,
+    input [31 : 0]              csr_writedata,
+    output reg [31 : 0]         csr_readdata,
+
+    output  wire                almost_full_data,
+    output  wire                almost_empty_data
+);
+
+    // --------------------------------------------------
+    // Local Parameters
+    // --------------------------------------------------
+    localparam ADDR_WIDTH   = log2ceil(FIFO_DEPTH);
+    localparam DEPTH        = FIFO_DEPTH;
+    localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
+    localparam PAYLOAD_WIDTH     = (USE_PACKETS == 1) ? 
+                   2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
+                   DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
+
+    // --------------------------------------------------
+    // Internal Signals
+    // --------------------------------------------------
+    genvar i;
+
+    reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
+    reg [ADDR_WIDTH-1 : 0]  wr_ptr;
+    reg [ADDR_WIDTH-1 : 0]  rd_ptr;
+    reg [DEPTH-1      : 0]  mem_used;
+
+    wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
+    wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
+
+    wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
+
+    wire read;
+    wire write;
+
+    reg empty;
+    reg next_empty;
+    reg full;
+    reg next_full;
+
+    wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
+    wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
+    wire [PAYLOAD_WIDTH-1 : 0] in_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
+    reg  [PAYLOAD_WIDTH-1 : 0] out_payload;
+
+    reg  internal_out_valid;
+    wire internal_out_ready;
+
+    reg  [ADDR_WIDTH : 0] fifo_fill_level;
+    reg  [ADDR_WIDTH : 0] fill_level;
+
+    reg  [ADDR_WIDTH-1 : 0]   sop_ptr = 0;
+    wire [ADDR_WIDTH-1 : 0]   curr_sop_ptr;
+    reg  [23:0]   almost_full_threshold;
+    reg  [23:0]   almost_empty_threshold;
+    reg  [23:0]   cut_through_threshold;
+    reg  [15:0]   pkt_cnt;
+    reg           drop_on_error_en;
+    reg           error_in_pkt;
+    reg           pkt_has_started;
+    reg           sop_has_left_fifo;
+    reg           fifo_too_small_r;
+    reg           pkt_cnt_eq_zero;
+    reg           pkt_cnt_eq_one;
+
+    wire          wait_for_threshold;
+    reg           pkt_mode;
+    wire          wait_for_pkt;
+    wire          ok_to_forward;
+    wire          in_pkt_eop_arrive;
+    wire          out_pkt_leave;
+    wire          in_pkt_start;
+    wire          in_pkt_error;
+    wire          drop_on_error;
+    wire          fifo_too_small;
+    wire          out_pkt_sop_leave;
+    wire [31:0]   max_fifo_size;
+    reg           fifo_fill_level_lt_cut_through_threshold;
+
+    // --------------------------------------------------
+    // Define Payload
+    //
+    // Icky part where we decide which signals form the
+    // payload to the FIFO with generate blocks.
+    // --------------------------------------------------
+    generate
+        if (EMPTY_WIDTH > 0) begin : gen_blk1
+            assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
+            assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
+        end 
+        else begin : gen_blk1_else
+            assign out_empty = in_error;
+            assign in_packet_signals = {in_startofpacket, in_endofpacket};
+            assign {out_startofpacket, out_endofpacket} = out_packet_signals;
+        end
+    endgenerate
+
+    generate
+        if (USE_PACKETS) begin : gen_blk2
+            if (ERROR_WIDTH > 0) begin : gen_blk3
+                if (CHANNEL_WIDTH > 0) begin : gen_blk4
+                    assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
+                    assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk4_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data, in_error};
+                    assign {out_packet_signals, out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk3_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk5
+                    assign in_payload = {in_packet_signals, in_data, in_channel};
+                    assign {out_packet_signals, out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk5_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_packet_signals, in_data};
+                    assign {out_packet_signals, out_data} = out_payload;
+                end
+            end
+        end
+        else begin : gen_blk2_else
+            assign out_packet_signals = 0;
+            if (ERROR_WIDTH > 0) begin : gen_blk6
+                if (CHANNEL_WIDTH > 0) begin : gen_blk7
+                    assign in_payload = {in_data, in_error, in_channel};
+                    assign {out_data, out_error, out_channel} = out_payload;
+                end
+                else begin : gen_blk7_else
+                    assign out_channel = in_channel;
+                    assign in_payload = {in_data, in_error};
+                    assign {out_data, out_error} = out_payload;
+                end
+            end
+            else begin : gen_blk6_else
+                assign out_error = in_error;
+                if (CHANNEL_WIDTH > 0) begin : gen_blk8
+                    assign in_payload = {in_data, in_channel};
+                    assign {out_data, out_channel} = out_payload;
+                end
+                else begin : gen_blk8_else
+                    assign out_channel = in_channel;
+                    assign in_payload = in_data;
+                    assign out_data = out_payload;
+                end
+            end
+        end
+    endgenerate
+
+    // --------------------------------------------------
+    // Memory-based FIFO storage
+    //
+    // To allow a ready latency of 0, the read index is 
+    // obtained from the next read pointer and memory 
+    // outputs are unregistered.
+    //
+    // If the empty latency is 1, we infer bypass logic
+    // around the memory so writes propagate to the
+    // outputs on the next cycle.
+    //
+    // Do not change the way this is coded: Quartus needs
+    // a perfect match to the template, and any attempt to 
+    // refactor the two always blocks into one will break
+    // memory inference.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin  : gen_blk9
+
+        if (EMPTY_LATENCY == 1) begin : gen_blk10
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] = in_payload;
+
+                internal_out_payload = mem[mem_rd_ptr];
+            end
+
+        end else begin : gen_blk10_else
+
+            always @(posedge clk) begin
+                if (in_valid && in_ready)
+                    mem[wr_ptr] <= in_payload;
+
+                internal_out_payload <= mem[mem_rd_ptr];
+            end
+
+        end
+
+        assign mem_rd_ptr = next_rd_ptr;
+    
+    end else begin : gen_blk9_else
+
+    // --------------------------------------------------
+    // Register-based FIFO storage
+    //
+    // Uses a shift register as the storage element. Each
+    // shift register slot has a bit which indicates if
+    // the slot is occupied (credit to Sam H for the idea).
+    // The occupancy bits are contiguous and start from the
+    // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
+    // FIFO.
+    // 
+    // Each slot is enabled during a read or when it
+    // is unoccupied. New data is always written to every
+    // going-to-be-empty slot (we keep track of which ones
+    // are actually useful with the occupancy bits). On a
+    // read we shift occupied slots.
+    // 
+    // The exception is the last slot, which always gets 
+    // new data when it is unoccupied.
+    // --------------------------------------------------
+        for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem[i] <= 0;
+                end 
+                else if (read || !mem_used[i]) begin
+                    if (!mem_used[i+1])
+                        mem[i] <= in_payload;
+                    else
+                        mem[i] <= mem[i+1];
+                end
+            end
+        end
+
+        always @(posedge clk, posedge reset) begin
+            if (reset) begin
+                mem[DEPTH-1] <= 0;
+            end 
+            else begin
+                if (DEPTH == 1) begin
+                    if (write)
+                        mem[DEPTH-1] <= in_payload;
+                end
+                else if (!mem_used[DEPTH-1])
+                    mem[DEPTH-1] <= in_payload;    
+            end
+        end
+
+    end
+    endgenerate
+
+    assign read  = internal_out_ready && internal_out_valid  && ok_to_forward;
+    assign write = in_ready && in_valid;
+
+    // --------------------------------------------------
+    // Pointer Management
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
+
+        assign incremented_wr_ptr = wr_ptr + 1'b1;
+        assign incremented_rd_ptr = rd_ptr + 1'b1;
+        assign next_wr_ptr =  drop_on_error ? curr_sop_ptr : write ?  incremented_wr_ptr : wr_ptr;
+        assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
+
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                wr_ptr <= 0;
+                rd_ptr <= 0;
+            end
+            else begin
+                wr_ptr <= next_wr_ptr;
+                rd_ptr <= next_rd_ptr;
+            end
+        end
+
+    end else begin : gen_blk11_else
+
+    // --------------------------------------------------
+    // Shift Register Occupancy Bits
+    //
+    // Consider a 4-deep FIFO with 2 entries: 0011
+    // On a read and write, do not modify the bits.
+    // On a write, left-shift the bits to get 0111.
+    // On a read, right-shift the bits to get 0001.
+    //
+    // Also, on a write we set bit0 (the head), while
+    // clearing the tail on a read.
+    // --------------------------------------------------
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                mem_used[0] <= 0;
+            end 
+            else begin
+                if (write ^ read) begin
+                    if (write)
+                        mem_used[0] <= 1;
+                    else if (read) begin
+                        if (DEPTH > 1)
+                            mem_used[0] <= mem_used[1];
+                        else
+                            mem_used[0] <= 0;
+                    end    
+                end
+            end
+        end
+
+        if (DEPTH > 1) begin : gen_blk12
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    mem_used[DEPTH-1] <= 0;
+                end
+                else begin 
+                    if (write ^ read) begin            
+                        mem_used[DEPTH-1] <= 0;
+                        if (write)
+                            mem_used[DEPTH-1] <= mem_used[DEPTH-2];
+                    end
+                end
+            end
+          end
+     
+        for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
+            always @(posedge clk, posedge reset) begin
+                if (reset) begin
+                    mem_used[i] <= 0;
+                end 
+                else begin
+                    if (write ^ read) begin
+                        if (write)
+                            mem_used[i] <= mem_used[i-1];
+                        else if (read)
+                            mem_used[i] <= mem_used[i+1];     
+                    end
+                end
+            end
+        end
+     
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Memory FIFO Status Management
+    //
+    // Generates the full and empty signals from the
+    // pointers. The FIFO is full when the next write 
+    // pointer will be equal to the read pointer after
+    // a write. Reading from a FIFO clears full.
+    //
+    // The FIFO is empty when the next read pointer will
+    // be equal to the write pointer after a read. Writing
+    // to a FIFO clears empty.
+    //
+    // A simultaneous read and write must not change any of 
+    // the empty or full flags unless there is a drop on error event.
+    // --------------------------------------------------
+    generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
+
+        always @* begin
+            next_full = full;
+            next_empty = empty;
+     
+            if (read && !write) begin
+                next_full = 1'b0;
+     
+                if (incremented_rd_ptr == wr_ptr)
+                    next_empty = 1'b1;
+            end
+            
+            if (write && !read) begin
+                if (!drop_on_error)
+                  next_empty = 1'b0;
+                else if (curr_sop_ptr == rd_ptr)   // drop on error and only 1 pkt in fifo
+                  next_empty = 1'b1;
+     
+                if (incremented_wr_ptr == rd_ptr && !drop_on_error)
+                    next_full = 1'b1;
+            end
+
+            if (write && read && drop_on_error) begin
+                if (curr_sop_ptr == next_rd_ptr)
+                  next_empty = 1'b1;
+            end
+        end
+     
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                empty <= 1;
+                full  <= 0;
+            end
+            else begin 
+                empty <= next_empty;
+                full  <= next_full;
+            end
+        end
+
+    end else begin : gen_blk13_else
+    // --------------------------------------------------
+    // Register FIFO Status Management
+    //
+    // Full when the tail occupancy bit is 1. Empty when
+    // the head occupancy bit is 0.
+    // --------------------------------------------------
+        always @* begin
+            full  = mem_used[DEPTH-1];
+            empty = !mem_used[0];
+
+            // ------------------------------------------
+            // For a single slot FIFO, reading clears the
+            // full status immediately.
+            // ------------------------------------------
+            if (DEPTH == 1)
+                full = mem_used[0] && !read;
+
+            internal_out_payload = mem[0];
+
+            // ------------------------------------------
+            // Writes clear empty immediately for lookahead modes.
+            // Note that we use in_valid instead of write to avoid
+            // combinational loops (in lookahead mode, qualifying
+            // with in_ready is meaningless).
+            //
+            // In a 1-deep FIFO, a possible combinational loop runs
+            // from write -> out_valid -> out_ready -> write
+            // ------------------------------------------
+            if (EMPTY_LATENCY == 0) begin
+                empty = !mem_used[0] && !in_valid;
+
+                if (!mem_used[0] && in_valid)
+                    internal_out_payload = in_payload;
+            end
+        end
+
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-ST Signals
+    //
+    // The in_ready signal is straightforward. 
+    //
+    // To match memory latency when empty latency > 1, 
+    // out_valid assertions must be delayed by one clock
+    // cycle.
+    //
+    // Note: out_valid deassertions must not be delayed or 
+    // the FIFO will underflow.
+    // --------------------------------------------------
+    assign in_ready = !full;
+    assign internal_out_ready = out_ready || !out_valid;
+
+    generate if (EMPTY_LATENCY > 1) begin : gen_blk14
+        always @(posedge clk or posedge reset) begin
+            if (reset)
+                internal_out_valid <= 0;
+            else begin
+                internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
+
+                if (read) begin
+                    if (incremented_rd_ptr == wr_ptr)
+                        internal_out_valid <= 1'b0;
+                end
+            end
+        end
+    end else begin : gen_blk14_else
+        always @* begin
+            internal_out_valid = !empty & ok_to_forward;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Single Output Pipeline Stage
+    //
+    // This output pipeline stage is enabled if the FIFO's 
+    // empty latency is set to 3 (default). It is disabled
+    // for all other allowed latencies.
+    //
+    // Reason: The memory outputs are unregistered, so we have to
+    // register the output or fmax will drop if combinatorial
+    // logic is present on the output datapath.
+    // 
+    // Q: The Avalon-ST spec says that I have to register my outputs
+    //    But isn't the memory counted as a register?
+    // A: The path from the address lookup to the memory output is
+    //    slow. Registering the memory outputs is a good idea. 
+    //
+    // The registers get packed into the memory by the fitter
+    // which means minimal resources are consumed (the result
+    // is a altsyncram with registered outputs, available on 
+    // all modern Altera devices). 
+    //
+    // This output stage acts as an extra slot in the FIFO, 
+    // and complicates the fill level.
+    // --------------------------------------------------
+    generate if (EMPTY_LATENCY == 3) begin : gen_blk15
+        always @(posedge clk or posedge reset) begin
+            if (reset) begin
+                out_valid   <= 0;
+                out_payload <= 0;
+            end
+            else begin
+                if (internal_out_ready) begin
+                    out_valid   <= internal_out_valid & ok_to_forward;
+                    out_payload <= internal_out_payload;
+                end
+            end
+        end
+    end
+    else begin : gen_blk15_else
+        always @* begin
+            out_valid   = internal_out_valid;
+            out_payload = internal_out_payload;
+        end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Fill Level
+    //
+    // The fill level is calculated from the next write
+    // and read pointers to avoid unnecessary latency
+    // and logic.
+    //
+    // However, if the store-and-forward mode of the FIFO
+    // is enabled, the fill level is an up-down counter
+    // for fmax optimization reasons.
+    //
+    // If the output pipeline is enabled, the fill level 
+    // must account for it, or we'll always be off by one.
+    // This may, or may not be important depending on the
+    // application.
+    //
+    // For now, we'll always calculate the exact fill level
+    // at the cost of an extra adder when the output stage
+    // is enabled.
+    // --------------------------------------------------
+    generate if (USE_FILL_LEVEL) begin : gen_blk16
+        wire [31:0] depth32;
+        assign depth32 = DEPTH;
+
+        if (USE_STORE_FORWARD) begin
+
+            reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
+            
+            // --------------------------------------------------
+            // We only drop on endofpacket. As long as we don't add to the fill
+            // level on the dropped endofpacket cycle, we can simply subtract
+            // (packet length - 1) from the fill level for dropped packets.
+            // --------------------------------------------------
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    curr_packet_len_less_one <= 0;
+                end else begin
+                    if (write) begin
+                        curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
+                        if (in_endofpacket)
+                            curr_packet_len_less_one <= 0;
+                    end
+                end
+            end
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) begin
+                    fifo_fill_level <= 0;
+                end else if (drop_on_error) begin
+                    fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
+                    if (read)
+                        fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
+                end else if (write && !read) begin
+                    fifo_fill_level <= fifo_fill_level + 1'b1;
+                end else if (read && !write) begin
+                    fifo_fill_level <= fifo_fill_level - 1'b1;
+                end
+            end
+
+        end else begin
+
+            always @(posedge clk or posedge reset) begin
+                if (reset) 
+                    fifo_fill_level <= 0;
+                else if (next_full & !drop_on_error)
+                    fifo_fill_level <= depth32[ADDR_WIDTH:0];
+                else begin
+                    fifo_fill_level[ADDR_WIDTH]     <= 1'b0;
+                    fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
+                end
+            end
+
+        end
+
+        always @* begin
+            fill_level = fifo_fill_level;
+
+            if (EMPTY_LATENCY == 3)
+                fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
+        end
+    end
+    else begin : gen_blk16_else
+        always @* begin
+            fill_level = 0;
+        end  
+    end
+    endgenerate
+
+    generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
+      assign almost_full_data = (fill_level >= almost_full_threshold);
+    end
+    else
+      assign almost_full_data = 0;
+    endgenerate
+
+    generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
+      assign almost_empty_data = (fill_level <= almost_empty_threshold);
+    end
+    else
+      assign almost_empty_data = 0;
+    endgenerate
+
+    // --------------------------------------------------
+    // Avalon-MM Status & Control Connection Point
+    //
+    // Register map:
+    //
+    // | Addr   | RW |     31 - 0      |
+    // |  0     | R  |   Fill level    |
+    //
+    // The registering of this connection point means
+    // that there is a cycle of latency between 
+    // reads/writes and the updating of the fill level.
+    // --------------------------------------------------
+    generate if (USE_STORE_FORWARD) begin : gen_blk19
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              cut_through_threshold  <= 0;
+              drop_on_error_en       <= 0;
+              csr_readdata           <= 0;
+              pkt_mode               <= 1'b1;
+          end
+          else begin
+              if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 5)
+                    csr_readdata <= {31'b0, drop_on_error_en};
+                else if (csr_address == 4)
+                    csr_readdata <= {8'b0, cut_through_threshold};
+                else if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b101)
+                   drop_on_error_en       <= csr_writedata[0];
+               else if(csr_address == 3'b100) begin
+                   cut_through_threshold  <= csr_writedata[23:0];
+                   pkt_mode <= (csr_writedata[23:0] == 0);
+               end
+               else if(csr_address == 3'b011)
+                    almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end     
+          end
+      end
+    end
+    else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
+    assign max_fifo_size = FIFO_DEPTH - 1;
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              almost_full_threshold  <= max_fifo_size[23 : 0];
+              almost_empty_threshold <= 0;
+              csr_readdata           <= 0;
+          end
+          else begin
+             if (csr_read) begin
+                csr_readdata <= 32'b0;
+                if (csr_address == 3)
+                    csr_readdata <= {8'b0, almost_empty_threshold};
+                else if (csr_address == 2)
+                    csr_readdata <= {8'b0, almost_full_threshold};
+                else if (csr_address == 0)
+                    csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+             end
+             else if (csr_write) begin
+               if(csr_address == 3'b011)
+                   almost_empty_threshold <= csr_writedata[23:0];
+               else if(csr_address == 3'b010)
+                  almost_full_threshold  <= csr_writedata[23:0];
+             end       
+          end
+      end
+    end
+    else begin : gen_blk19_else2
+      always @(posedge clk or posedge reset) begin
+          if (reset) begin
+              csr_readdata <= 0;
+          end
+          else if (csr_read) begin
+              csr_readdata <= 0;
+
+              if (csr_address == 0) 
+                  csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+          end
+      end
+    end
+    endgenerate
+
+    // --------------------------------------------------
+    // Store and forward logic
+    // --------------------------------------------------
+    // if the fifo gets full before the entire packet or the
+    // cut-threshold condition is met then start sending out
+    // data in order to avoid dead-lock situation
+
+    generate if (USE_STORE_FORWARD) begin : gen_blk20
+      assign wait_for_threshold   = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
+      assign wait_for_pkt         = pkt_cnt_eq_zero  | (pkt_cnt_eq_one  & out_pkt_leave);
+      assign ok_to_forward        = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : 
+                                     ~wait_for_threshold) | fifo_too_small_r;
+      assign in_pkt_eop_arrive    = in_valid & in_ready & in_endofpacket;
+      assign in_pkt_start         = in_valid & in_ready & in_startofpacket;
+      assign in_pkt_error         = in_valid & in_ready & |in_error;
+      assign out_pkt_sop_leave    = out_valid & out_ready & out_startofpacket;
+      assign out_pkt_leave        = out_valid & out_ready & out_endofpacket;
+      assign fifo_too_small       = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
+
+      // count packets coming and going into the fifo
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          pkt_cnt           <= 0;
+          pkt_has_started   <= 0;
+          sop_has_left_fifo <= 0;
+          fifo_too_small_r  <= 0;
+          pkt_cnt_eq_zero   <= 1'b1;
+          pkt_cnt_eq_one    <= 1'b0;
+          fifo_fill_level_lt_cut_through_threshold <= 1'b1;
+        end
+        else begin
+          fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
+          fifo_too_small_r <= fifo_too_small;
+
+          if( in_pkt_eop_arrive )
+            sop_has_left_fifo <= 1'b0;
+          else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
+            sop_has_left_fifo <= 1'b1;
+
+          if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
+            pkt_cnt <= pkt_cnt + 1'b1;
+            pkt_cnt_eq_zero <= 0;
+            if (pkt_cnt == 0)
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+          else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
+            pkt_cnt <= pkt_cnt - 1'b1;
+            if (pkt_cnt == 1) 
+              pkt_cnt_eq_zero <= 1'b1;
+            else
+              pkt_cnt_eq_zero <= 1'b0;
+            if (pkt_cnt == 2) 
+              pkt_cnt_eq_one <= 1'b1;
+            else
+              pkt_cnt_eq_one <= 1'b0;
+          end
+
+          if (in_pkt_start)
+            pkt_has_started <= 1'b1;
+          else if (in_pkt_eop_arrive)
+            pkt_has_started <= 1'b0;
+        end
+      end
+
+      // drop on error logic
+      always @(posedge clk or posedge reset) begin
+        if (reset) begin
+          sop_ptr <= 0;
+          error_in_pkt <= 0;
+        end
+        else begin
+          // save the location of the SOP
+          if ( in_pkt_start ) 
+            sop_ptr <= wr_ptr;
+
+          // remember if error in pkt
+          // log error only if packet has already started
+          if (in_pkt_eop_arrive)
+            error_in_pkt <= 1'b0;
+          else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
+            error_in_pkt <= 1'b1;
+        end
+      end
+
+      assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & 
+                            ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
+
+      assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
+
+    end
+    else begin : gen_blk20_else
+      assign ok_to_forward = 1'b1;
+      assign drop_on_error = 1'b0;
+      if (ADDR_WIDTH <= 1)
+        assign curr_sop_ptr = 1'b0;
+      else
+        assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
+    end
+    endgenerate
+
+
+    // --------------------------------------------------
+    // Calculates the log2ceil of the input value
+    // --------------------------------------------------
+    function integer log2ceil;
+        input integer val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_arbitrator.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_arbitrator.sv
new file mode 100644
index 0000000..b836a45
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_arbitrator.sv
@@ -0,0 +1,272 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
+// $Revision: #3 $
+// $Date: 2010/07/07 $
+// $Author: jyeap $
+
+/* -----------------------------------------------------------------------
+Round-robin/fixed arbitration implementation.
+
+Q: how do you find the least-significant set-bit in an n-bit binary number, X?
+
+A: M = X & (~X + 1)
+
+Example: X = 101000100
+ 101000100 & 
+ 010111011 + 1 =
+
+ 101000100 &
+ 010111100 =
+ -----------
+ 000000100
+
+The method can be generalized to find the first set-bit
+at a bit index no lower than bit-index N, simply by adding
+2**N rather than 1.
+
+
+Q: how does this relate to round-robin arbitration?
+A:
+Let X be the concatenation of all request signals.
+Let the number to be added to X (hereafter called the
+top_priority) initialize to 1, and be assigned from the
+concatenation of the previous saved-grant, left-rotated
+by one position, each time arbitration occurs.  The
+concatenation of grants is then M.
+
+Problem: consider this case:
+
+top_priority            = 010000
+request                 = 001001
+~request + top_priority = 000110
+next_grant              = 000000 <- no one is granted!
+
+There was no "set bit at a bit index no lower than bit-index 4", so 
+the result was 0.
+
+We need to propagate the carry out from (~request + top_priority) to the LSB, so
+that the sum becomes 000111, and next_grant is 000001.  This operation could be
+called a "circular add". 
+
+A bit of experimentation on the circular add reveals a significant amount of 
+delay in exiting and re-entering the carry chain - this will vary with device
+family.  Quartus also reports a combinational loop warning.  Finally, 
+Modelsim 6.3g has trouble with the expression, evaluating it to 'X'.  But 
+Modelsim _doesn't_ report a combinational loop!)
+
+An alternate solution: concatenate the request vector with itself, and OR
+corresponding bits from the top and bottom halves to determine next_grant.
+
+Example:
+
+top_priority                        =        010000
+{request, request}                  = 001001 001001
+{~request, ~request} + top_priority = 110111 000110
+result of & operation               = 000001 000000
+next_grant                          =        000001
+
+Notice that if request = 0, the sum operation will overflow, but we can ignore
+this; the next_grant result is 0 (no one granted), as you might expect.
+In the implementation, the last-granted value must be maintained as
+a non-zero value - best probably simply not to update it when no requests
+occur.
+
+----------------------------------------------------------------------- */ 
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_arbitrator
+#(
+    parameter NUM_REQUESTERS = 8,
+    // --------------------------------------
+    // Implemented schemes
+    // "round-robin"
+    // "fixed-priority"
+    // "no-arb"
+    // --------------------------------------
+    parameter SCHEME         = "round-robin",
+    parameter PIPELINE       = 0
+)
+(
+    input clk,
+    input reset,
+   
+    // --------------------------------------
+    // Requests
+    // --------------------------------------
+    input [NUM_REQUESTERS-1:0]  request,
+   
+    // --------------------------------------
+    // Grants
+    // --------------------------------------
+    output [NUM_REQUESTERS-1:0] grant,
+
+    // --------------------------------------
+    // Control Signals
+    // --------------------------------------
+    input                       increment_top_priority,
+    input                       save_top_priority
+);
+
+    // --------------------------------------
+    // Signals
+    // --------------------------------------
+    wire [NUM_REQUESTERS-1:0]   top_priority;
+    reg  [NUM_REQUESTERS-1:0]   top_priority_reg;
+    reg  [NUM_REQUESTERS-1:0]   last_grant;
+    wire [2*NUM_REQUESTERS-1:0] result;
+
+    // --------------------------------------
+    // Scheme Selection
+    // --------------------------------------
+    generate
+        if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
+            assign top_priority = top_priority_reg;
+        end
+        else begin
+            // Fixed arbitration (or single-requester corner case)
+            assign top_priority = 1'b1;
+        end
+    endgenerate
+
+    // --------------------------------------
+    // Decision Logic
+    // --------------------------------------
+    altera_merlin_arb_adder
+    #(
+        .WIDTH (2 * NUM_REQUESTERS)
+    ) 
+    adder
+    (
+        .a ({ ~request, ~request }),
+        .b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
+        .sum (result)
+    );
+
+  
+    generate if (SCHEME == "no-arb") begin
+
+        // --------------------------------------
+        // No arbitration: just wire request directly to grant
+        // --------------------------------------
+        assign grant = request;
+
+    end else begin
+        // Do the math in double-vector domain
+        wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
+        assign grant_double_vector = {request, request} & result;
+
+        // --------------------------------------
+        // Extract grant from the top and bottom halves
+        // of the double vector.
+        // --------------------------------------
+        assign grant =
+            grant_double_vector[NUM_REQUESTERS - 1 : 0] |
+            grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
+
+    end
+    endgenerate
+
+    // --------------------------------------
+    // Left-rotate the last grant vector to create top_priority.
+    // --------------------------------------
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            top_priority_reg <= 1'b1;
+        end
+        else begin
+            if (PIPELINE) begin
+                if (increment_top_priority) begin
+                    top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
+                        grant[NUM_REQUESTERS-1]} : top_priority_reg;
+                end
+            end else begin
+                if (increment_top_priority) begin
+                    if (|request)
+                        top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
+                            grant[NUM_REQUESTERS-1] };
+                    else
+                        top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
+                end
+                else if (save_top_priority) begin
+                    top_priority_reg <= grant; 
+                end
+            end
+        end
+    end
+
+endmodule
+
+// ----------------------------------------------
+// Adder for the standard arbitrator
+// ----------------------------------------------
+module altera_merlin_arb_adder
+#(
+    parameter WIDTH = 8
+)
+(
+    input [WIDTH-1:0] a,
+    input [WIDTH-1:0] b,
+
+    output [WIDTH-1:0] sum
+);
+
+    wire [WIDTH:0] sum_lint;
+    // ----------------------------------------------
+    // Benchmarks indicate that for small widths, the full
+    // adder has higher fmax because synthesis can merge
+    // it with the mux, allowing partial decisions to be 
+    // made early.
+    //
+    // The magic number is 4 requesters, which means an
+    // 8 bit adder.
+    // ----------------------------------------------
+    genvar i;
+    generate if (WIDTH <= 8) begin : full_adder
+
+        wire cout[WIDTH-1:0];
+
+        assign sum[0]  = (a[0] ^ b[0]);
+        assign cout[0] = (a[0] & b[0]);
+
+        for (i = 1; i < WIDTH; i = i+1) begin : arb
+
+            assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
+            assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
+
+        end
+
+    end else begin : carry_chain
+
+        assign sum_lint = a + b;
+        assign sum = sum_lint[WIDTH-1:0];
+
+    end
+    endgenerate
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_burst_uncompressor.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_burst_uncompressor.sv
new file mode 100644
index 0000000..c1a4863
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_burst_uncompressor.sv
@@ -0,0 +1,296 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2012 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Burst Uncompressor
+//
+// Compressed read bursts -> uncompressed
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_burst_uncompressor
+#(
+    parameter ADDR_W      = 16,
+    parameter BURSTWRAP_W = 3,
+    parameter BYTE_CNT_W  = 4,
+    parameter PKT_SYMBOLS = 4,
+    parameter BURST_SIZE_W = 3
+)
+(
+    input clk,
+    input reset,
+   
+    // sink ST signals
+    input sink_startofpacket,
+    input sink_endofpacket,
+    input sink_valid,
+    output sink_ready,
+   
+    // sink ST "data"
+    input [ADDR_W - 1: 0] sink_addr,
+    input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
+    input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
+    input sink_is_compressed,
+    input [BURST_SIZE_W-1 : 0] sink_burstsize,
+   
+    // source ST signals
+    output source_startofpacket,
+    output source_endofpacket,
+    output source_valid,
+    input source_ready,
+   
+    // source ST "data"
+    output [ADDR_W - 1: 0] source_addr,
+    output [BURSTWRAP_W - 1 : 0] source_burstwrap,
+    output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
+   
+    // Note: in the slave agent, the output should always be uncompressed.  In
+    // other applications, it may be required to leave-compressed or not. How to
+    // control?  Seems like a simple mux - pass-through if no uncompression is
+    // required.
+    output source_is_compressed,
+    output [BURST_SIZE_W-1 : 0] source_burstsize
+);
+
+//----------------------------------------------------
+// AXSIZE decoding
+//
+// Turns the axsize value into the actual number of bytes
+// being transferred.
+// ---------------------------------------------------
+function reg[63:0] bytes_in_transfer;
+    input [BURST_SIZE_W-1:0] axsize;
+    case (axsize)
+        4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+        4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
+        4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
+        4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
+        4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
+        4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
+        4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
+        4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
+        4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
+        4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
+        default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
+    endcase
+
+endfunction  
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+  
+   // def: Burst Compression.  In a merlin network, a compressed burst is one 
+   // which is transmitted in a single beat.  Example: read burst.  In 
+   // constrast, an uncompressed burst (example: write burst) is transmitted in
+   // one beat per writedata item.
+   //
+   // For compressed bursts which require response packets, burst
+   // uncompression is required.  Concrete example: a read burst of size 8
+   // occupies one response-fifo position.  When that fifo position reaches the
+   // front of the FIFO, the slave starts providing the required 8 readdatavalid
+   // pulses.  The 8 return response beats must be provided in a single packet,
+   // with incrementing address and decrementing byte_cnt fields.  Upon receipt
+   // of the final readdata item of the burst, the response FIFO item is
+   // retired.
+   // Burst uncompression logic provides:
+   //   a) 2-state FSM (idle, busy)
+   //     reset to idle state
+   //     transition to busy state for 2nd and subsequent rdv pulses
+   //     - a single-cycle burst (aka non-burst read) causes no transition to
+   //     busy state.
+   //   b) response startofpacket/endofpacket logic.  The response FIFO item 
+   //   will have sop asserted, and may have eop asserted. (In the case of
+   //   multiple read bursts transmit in the command fabric in a single packet,
+   //   the eop assertion will come in a later FIFO item.)  To support packet
+   //   conservation, and emit a well-formed packet on the response fabric,
+   //     i) response fabric startofpacket is asserted only for the first resp.
+   //     beat;
+   //     ii) response fabric endofpacket is asserted only for the last resp.
+   //     beat.
+   //   c) response address field.  The response address field contains an
+   //   incrementing sequence, such that each readdata item is associated with
+   //   its slave-map location.  N.b. a) computing the address correctly requires
+   //   knowledge of burstwrap behavior b) there may be no clients of the address
+   //   field, which makes this field a good target for optimization.  See
+   //   burst_uncompress_address_counter below.
+   //   d) response byte_cnt field.  The response byte_cnt field contains a
+   //   decrementing sequence, such that each beat of the response contains the
+   //   count of bytes to follow.  In the case of sub-bursts in a single packet,
+   //   the byte_cnt field may decrement down to num_symbols, then back up to
+   //   some value, multiple times in the packet.
+  
+   reg burst_uncompress_busy;
+   reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
+   wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
+   wire first_packet_beat;
+   wire last_packet_beat;
+
+   assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
+   assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
+
+   // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
+   // the output.
+   assign source_byte_cnt =
+     first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
+   assign source_valid = sink_valid;
+  
+   // Last packet beat is set throughout receipt of an uncompressed read burst
+   // from the response FIFO - this forces all the burst uncompression machinery
+   // idle.
+   assign last_packet_beat = ~sink_is_compressed |
+     (
+     burst_uncompress_busy ?
+       (sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
+         sink_valid & (sink_byte_cnt == num_symbols)
+     );
+  
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_busy <= '0;
+       burst_uncompress_byte_counter <= '0;
+     end
+     else begin
+       if (source_valid & source_ready & sink_valid) begin
+         // No matter what the current state, last_packet_beat leads to
+         // idle.
+         if (last_packet_beat) begin
+           burst_uncompress_busy <= '0;
+           burst_uncompress_byte_counter <= '0;
+         end
+         else begin
+           if (burst_uncompress_busy) begin
+             burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ? 
+               (burst_uncompress_byte_counter_lint - num_symbols) :
+               (sink_byte_cnt - num_symbols);
+           end
+           else begin // not busy, at least one more beat to go
+             burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
+             // To do: should busy go true for numsymbols-size compressed
+             // bursts?
+             burst_uncompress_busy <= 1'b1;
+           end
+         end
+       end
+     end
+   end
+  
+   reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
+   reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
+
+   wire [63:0] decoded_burstsize_wire;
+   wire [ADDR_W-1:0] decoded_burstsize;
+
+
+   localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
+   wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
+   // The input burstwrap value can be used as a mask against address values,
+   // but with one caveat: the address width may be (probably is) wider than 
+   // the burstwrap width.  The spec says: extend the msb of the burstwrap 
+   // value out over the entire address width (but only if the address width
+   // actually is wider than the burstwrap width; otherwise it's a 0-width or
+   // negative range and concatenation multiplier). 
+   generate
+      if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
+         // Sign-extend, just wires:
+            assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
+                {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
+            assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
+      end
+      else begin
+            assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
+      end
+   endgenerate
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_base <= '0;
+     end
+     else if (first_packet_beat & source_ready) begin
+       burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
+     end
+   end
+
+   assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize);  //expand it to 64 bits
+   assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0];      //then take the width that is needed
+
+   wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
+   (
+     (first_packet_beat ?
+       sink_addr :
+       burst_uncompress_address_offset) + decoded_burstsize
+    ) &
+    addr_width_burstwrap[ADDR_W-1:0];
+    wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
+
+   always @(posedge clk or posedge reset) begin
+     if (reset) begin
+       burst_uncompress_address_offset <= '0;
+     end
+     else begin
+       if (source_ready & source_valid) begin
+         burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
+         // if (first_packet_beat) begin
+         //   burst_uncompress_address_offset <=
+         //     (sink_addr + num_symbols) & addr_width_burstwrap;
+         // end
+         // else begin
+         //   burst_uncompress_address_offset <=
+         //     (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
+         // end
+       end
+     end
+   end
+  
+   // On the first packet beat, send the input address out unchanged, 
+   // while values are computed/registered for 2nd and subsequent beats.
+   assign source_addr = first_packet_beat ? sink_addr :
+       burst_uncompress_address_base | burst_uncompress_address_offset;
+   assign source_burstwrap = sink_burstwrap;
+   assign source_burstsize = sink_burstsize;
+  
+   //-------------------------------------------------------------------
+   // A single (compressed) read burst will have sop/eop in the same beat.
+   // A sequence of read sub-bursts emitted by a burst adapter in response to a
+   // single read burst will have sop on the first sub-burst, eop on the last.
+   // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve 
+   // packet conservation.
+   assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
+   assign source_endofpacket   = sink_endofpacket & last_packet_beat;
+   assign sink_ready = source_valid & source_ready & last_packet_beat;
+  
+   // This is correct for the slave agent usage, but won't always be true in the
+   // width adapter.  To do: add an "please uncompress" input, and use it to
+   // pass-through or modify, and set source_is_compressed accordingly.
+   assign source_is_compressed = 1'b0;
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_agent.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_agent.sv
new file mode 100644
index 0000000..1121663
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_agent.sv
@@ -0,0 +1,303 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Agent
+//
+// Converts Avalon-MM transactions into
+// Merlin network packets.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_agent
+#(
+   // -------------------
+   // Packet Format Parameters
+   // -------------------
+   parameter 
+   PKT_QOS_H                  = 109,
+   PKT_QOS_L                  = 106,
+   PKT_DATA_SIDEBAND_H        = 105,
+   PKT_DATA_SIDEBAND_L        = 98,
+   PKT_ADDR_SIDEBAND_H        = 97, 
+   PKT_ADDR_SIDEBAND_L        = 93,
+   PKT_CACHE_H                = 92,
+   PKT_CACHE_L                = 89,
+   PKT_THREAD_ID_H            = 88,
+   PKT_THREAD_ID_L            = 87,
+   PKT_BEGIN_BURST            = 81,
+   PKT_PROTECTION_H           = 80,
+   PKT_PROTECTION_L           = 80,
+   PKT_BURSTWRAP_H            = 79,
+   PKT_BURSTWRAP_L            = 77,
+   PKT_BYTE_CNT_H             = 76,
+   PKT_BYTE_CNT_L             = 74,
+   PKT_ADDR_H                 = 73,
+   PKT_ADDR_L                 = 42,
+   PKT_BURST_SIZE_H           = 86,
+   PKT_BURST_SIZE_L           = 84,
+   PKT_BURST_TYPE_H           = 94,
+   PKT_BURST_TYPE_L           = 93,
+   PKT_TRANS_EXCLUSIVE        = 83,
+   PKT_TRANS_LOCK             = 82,
+   PKT_TRANS_COMPRESSED_READ  = 41,
+   PKT_TRANS_POSTED           = 40,
+   PKT_TRANS_WRITE            = 39,
+   PKT_TRANS_READ             = 38,
+   PKT_DATA_H                 = 37,
+   PKT_DATA_L                 = 6,
+   PKT_BYTEEN_H               = 5,
+   PKT_BYTEEN_L               = 2,
+   PKT_SRC_ID_H               = 1,
+   PKT_SRC_ID_L               = 1,
+   PKT_DEST_ID_H              = 0,
+   PKT_DEST_ID_L              = 0,
+   PKT_RESPONSE_STATUS_L      = 110,
+   PKT_RESPONSE_STATUS_H      = 111,
+   PKT_ORI_BURST_SIZE_L       = 112,
+   PKT_ORI_BURST_SIZE_H       = 114,
+   ST_DATA_W                  = 115,
+   ST_CHANNEL_W               = 1,
+
+   // -------------------
+   // Agent Parameters
+   // -------------------
+   AV_BURSTCOUNT_W       = 3,
+   ID                    = 1,
+   SUPPRESS_0_BYTEEN_RSP = 1,
+   BURSTWRAP_VALUE       = 4,
+   CACHE_VALUE           = 0,
+   SECURE_ACCESS_BIT     = 1,
+   USE_READRESPONSE      = 0,
+   USE_WRITERESPONSE     = 0,
+
+   // -------------------
+   // Derived Parameters
+   // -------------------
+   PKT_BURSTWRAP_W   = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
+   PKT_BYTE_CNT_W    = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
+   PKT_PROTECTION_W  = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
+   PKT_ADDR_W        = PKT_ADDR_H - PKT_ADDR_L + 1,
+   PKT_DATA_W        = PKT_DATA_H - PKT_DATA_L + 1,
+   PKT_BYTEEN_W      = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   PKT_SRC_ID_W      = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
+   PKT_DEST_ID_W     = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
+   PKT_BURST_SIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
+) (
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input                         clk,
+   input                         reset,
+
+   // -------------------
+   // Avalon-MM Anti-Master
+   // -------------------
+   input [PKT_ADDR_W-1 : 0]      av_address,
+   input                         av_write,
+   input                         av_read,
+   input [PKT_DATA_W-1 : 0]      av_writedata,
+   output reg [PKT_DATA_W-1 : 0] av_readdata,
+   output reg                    av_waitrequest,
+   output reg                    av_readdatavalid,
+   input [PKT_BYTEEN_W-1 : 0]    av_byteenable,
+   input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
+   input                         av_debugaccess,
+   input                         av_lock,
+   output reg [1 : 0]            av_response,
+   output reg                    av_writeresponsevalid,
+
+   // -------------------
+   // Command Source
+   // -------------------
+   output reg                    cp_valid,
+   output reg [ST_DATA_W-1 : 0]  cp_data,
+   output wire                   cp_startofpacket,
+   output wire                   cp_endofpacket,
+   input                         cp_ready,
+
+   // -------------------
+   // Response Sink
+   // -------------------
+   input                         rp_valid,
+   input [ST_DATA_W-1 : 0]       rp_data,
+   input [ST_CHANNEL_W-1 : 0]    rp_channel,
+   input                         rp_startofpacket,
+   input                         rp_endofpacket,
+   output reg                    rp_ready
+);
+    // ------------------------------------------------------------
+    // Utility Functions
+    // ------------------------------------------------------------
+   function integer clogb2;
+      input [31 : 0] value;
+      begin
+         for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
+            value = value >> 1;
+         clogb2 = clogb2 - 1;
+      end
+   endfunction // clogb2
+
+   localparam MAX_BURST    = 1 << (AV_BURSTCOUNT_W - 1);
+   localparam NUMSYMBOLS   = PKT_BYTEEN_W; 
+   localparam BURSTING     = (MAX_BURST > NUMSYMBOLS);
+   localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
+   localparam BURST_SIZE   = clogb2(NUMSYMBOLS);
+
+   typedef enum bit  [1 : 0]
+   {
+      FIXED       = 2'b00,
+      INCR        = 2'b01,
+      WRAP        = 2'b10,
+      OTHER_WRAP  = 2'b11
+   } MerlinBurstType;
+
+   // --------------------------------------
+   // Potential optimization: compare in words to save bits?
+   // --------------------------------------
+   wire is_burst;
+   assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
+
+   wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
+   wire [31 : 0] id_int              = ID; 
+   wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
+   wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
+
+   // --------------------------------------
+   // Address alignment
+   //
+   // The packet format requires that addresses be aligned to
+   // the transaction size.
+   // --------------------------------------
+   wire [PKT_ADDR_W-1 : 0] av_address_aligned;
+   generate 
+      if (NUMSYMBOLS > 1) begin
+         assign av_address_aligned = 
+         {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
+      end
+      else begin
+         assign av_address_aligned = av_address;
+      end 
+   endgenerate
+
+   // --------------------------------------
+   // Command & Response Construction
+   // --------------------------------------
+   always_comb begin
+      cp_data                                              = '0;
+
+      cp_data[PKT_PROTECTION_L]                            = av_debugaccess;    
+      cp_data[PKT_PROTECTION_L+1]                          = SECURE_ACCESS_BIT[0];  // secure cache bit
+      cp_data[PKT_PROTECTION_L+2]                          = 1'b0;                  // instruction/data cache bit
+      cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]           = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
+      cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]             = av_burstcount;
+      cp_data[PKT_ADDR_H : PKT_ADDR_L]                     = av_address_aligned;
+      cp_data[PKT_TRANS_EXCLUSIVE]                         = 1'b0;
+      cp_data[PKT_TRANS_LOCK]                              = av_lock;
+      cp_data[PKT_TRANS_COMPRESSED_READ]                   = av_read & is_burst;
+      cp_data[PKT_TRANS_READ]                              = av_read;
+      cp_data[PKT_TRANS_WRITE]                             = av_write;
+      cp_data[PKT_TRANS_POSTED]                            = av_write & !USE_WRITERESPONSE;
+      cp_data[PKT_DATA_H : PKT_DATA_L]                     = av_writedata;
+      cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L]                 = av_byteenable;
+      cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L]         = burstsize_sig;
+      cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
+      cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]         = bursttype_value;
+      cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L]                 = id_int[PKT_SRC_ID_W-1 : 0];
+      cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L]           = '0;
+      cp_data[PKT_CACHE_H : PKT_CACHE_L]                   = CACHE_VALUE[3 : 0];
+      cp_data[PKT_QOS_H : PKT_QOS_L]                       = '0;        
+      cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L]   = '0;
+      cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L]   = '0;
+
+      av_readdata                                          = rp_data[PKT_DATA_H : PKT_DATA_L];
+      if (USE_WRITERESPONSE || USE_READRESPONSE)
+         av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
+      else
+         av_response = '0;
+      end
+
+   // --------------------------------------
+   // Command Control
+   // --------------------------------------
+   reg hold_waitrequest;
+
+   always @ (posedge clk, posedge reset) begin
+      if (reset)
+         hold_waitrequest <= 1'b1;
+      else
+         hold_waitrequest <= 1'b0;
+   end  
+   
+   always_comb begin
+      cp_valid = 0;
+
+      if ((av_write || av_read) && ~hold_waitrequest)
+         cp_valid = 1;
+   end
+
+   generate if (BURSTING) begin
+      reg sop_enable;
+
+      always @(posedge clk, posedge reset) begin
+         if (reset) begin
+            sop_enable <= 1'b1;
+         end
+         else begin
+            if (cp_valid && cp_ready) begin
+               sop_enable <= 1'b0;
+               if (cp_endofpacket)
+                  sop_enable <= 1'b1;
+            end
+         end
+      end
+
+      assign cp_startofpacket = sop_enable;
+      assign cp_endofpacket   = (av_read) | (av_burstcount == NUMSYMBOLS);
+
+   end 
+   else begin
+
+      assign cp_startofpacket = 1'b1;
+      assign cp_endofpacket   = 1'b1;
+
+   end
+   endgenerate
+
+   // --------------------------------------
+   // Backpressure & Readdatavalid
+   // --------------------------------------
+   always_comb begin
+      rp_ready              = 1;
+      av_readdatavalid      = 0;
+      av_writeresponsevalid = 0;
+      av_waitrequest = hold_waitrequest | !cp_ready;
+
+      if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
+         av_writeresponsevalid = rp_valid;
+      else
+         av_readdatavalid      = rp_valid;
+
+      if (SUPPRESS_0_BYTEEN_RSP) begin
+         if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
+            av_readdatavalid = 0;
+      end
+   end
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_translator.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_translator.sv
new file mode 100644
index 0000000..07bd565
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_master_translator.sv
@@ -0,0 +1,556 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Merlin Master Translator
+//
+// Converts an Avalon-MM master interface into an 
+// Avalon-MM "universal" master interface.
+//
+// The universal interface is defined as the superset of ports
+// and parameters that can represent any legal Avalon 
+// interface.
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_master_translator #(
+   parameter
+      // widths
+      AV_ADDRESS_W                = 32,
+      AV_DATA_W                   = 32,
+      AV_BURSTCOUNT_W             = 4,
+      AV_BYTEENABLE_W             = 4,
+
+      UAV_ADDRESS_W               = 38,
+      UAV_BURSTCOUNT_W            = 10,
+  
+      // optional ports
+      USE_BURSTCOUNT              = 1,
+      USE_BEGINBURSTTRANSFER      = 0,
+      USE_BEGINTRANSFER           = 0,
+      USE_CHIPSELECT              = 0,
+      USE_READ                    = 1,
+      USE_READDATAVALID           = 1,
+      USE_WRITE                   = 1,
+      USE_WAITREQUEST             = 1,
+      USE_WRITERESPONSE           = 0,
+      USE_READRESPONSE            = 0,
+   
+      AV_REGISTERINCOMINGSIGNALS  = 0,
+      AV_SYMBOLS_PER_WORD         = 4,
+      AV_ADDRESS_SYMBOLS          = 0,
+      // must be enabled for a bursting master
+      AV_CONSTANT_BURST_BEHAVIOR  = 1,
+      UAV_CONSTANT_BURST_BEHAVIOR = 0,
+      AV_BURSTCOUNT_SYMBOLS       = 0,
+      AV_LINEWRAPBURSTS           = 0
+)(
+   input wire                           clk,
+   input wire                           reset,
+
+   // Universal Avalon Master
+   output reg                           uav_write,
+   output reg                           uav_read,
+   output reg [UAV_ADDRESS_W -1 : 0]    uav_address,
+   output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount,
+   output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable,
+   output wire [AV_DATA_W -1 : 0]       uav_writedata,
+   output wire                          uav_lock,
+   output wire                          uav_debugaccess,
+   output wire                          uav_clken,
+
+   input wire [AV_DATA_W -1 : 0]        uav_readdata,
+   input wire                           uav_readdatavalid,
+   input wire                           uav_waitrequest,
+   input wire [1 : 0]                   uav_response,
+   input wire                           uav_writeresponsevalid,
+
+   // Avalon-MM Anti-master (slave)
+   input reg                            av_write,
+   input reg                            av_read,
+   input wire [AV_ADDRESS_W -1 : 0]     av_address,
+   input wire [AV_BYTEENABLE_W -1 : 0]  av_byteenable,
+   input wire [AV_BURSTCOUNT_W -1 : 0]  av_burstcount,
+   input wire [AV_DATA_W -1 : 0]        av_writedata,
+   input wire                           av_begintransfer,
+   input wire                           av_beginbursttransfer,
+   input wire                           av_lock,
+   input wire                           av_chipselect,
+   input wire                           av_debugaccess,
+   input wire                           av_clken,
+
+   output wire [AV_DATA_W -1 : 0]       av_readdata,
+   output wire                          av_readdatavalid,
+   output reg                           av_waitrequest,
+   output reg [1 : 0]                   av_response,
+   output reg                           av_writeresponsevalid
+);
+
+   localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD);
+   localparam AV_MAX_SYMBOL_BURST = flog2(pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : AV_SYMBOLS_PER_WORD));
+   localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0;
+   localparam UAV_BURSTCOUNT_H_OR_31 = (UAV_BURSTCOUNT_W > 32) ? 31 : UAV_BURSTCOUNT_W - 1;
+   localparam UAV_ADDRESS_H_OR_31 = (UAV_ADDRESS_W > 32) ? 31 : UAV_ADDRESS_W - 1;
+
+   localparam BITS_PER_WORD_BURSTCOUNT = (UAV_BURSTCOUNT_W == 1) ? 0 : BITS_PER_WORD;
+   localparam BITS_PER_WORD_ADDRESS    = (UAV_ADDRESS_W == 1) ? 0 : BITS_PER_WORD;
+
+   localparam ADDRESS_LOW     = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS;
+   localparam BURSTCOUNT_LOW  = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT;
+
+   localparam ADDRESS_HIGH    = (UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW) ? AV_ADDRESS_W : (UAV_ADDRESS_W - ADDRESS_LOW);
+   localparam BURSTCOUNT_HIGH = (UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW) ? AV_BURSTCOUNT_W : (UAV_BURSTCOUNT_W - BURSTCOUNT_LOW);
+
+   function integer flog2;
+      input [31:0]  depth;
+      integer       i;
+      begin
+         i = depth;
+         if ( i <= 0 ) flog2 = 0;
+         else begin
+            for (flog2 = -1; i > 0; flog2 = flog2 + 1)
+               i = i >> 1;
+         end
+      end
+   endfunction // flog2
+
+    // ------------------------------------------------------------
+    // Calculates the ceil(log2()) of the input val.
+    //
+    // Limited to a positive 32-bit input value.
+    // ------------------------------------------------------------
+    function integer clog2;
+        input[31:0] val;
+        reg[31:0] i;
+
+        begin
+            i = 1;
+            clog2 = 0;
+
+            while (i < val) begin
+                clog2 = clog2 + 1;
+                i = i[30:0] << 1;
+            end
+        end
+    endfunction
+
+   function integer pow2;
+      input [31:0] toShift;
+      begin
+         pow2 = 1;
+         pow2 = pow2 << toShift;
+      end
+   endfunction // pow2
+
+   // -------------------------------------------------
+   // Assign some constants to appropriately-sized signals to
+   // avoid synthesis warnings. This also helps some simulators
+   // with their inferred sensitivity lists.
+   //
+   // The symbols per word calculation here rounds non-power of two
+   // symbols to the next highest power of two, which is what we want
+   // when calculating the decrementing byte count.
+   // -------------------------------------------------
+   wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_H_OR_31 : 0]));
+   wire [UAV_BURSTCOUNT_H_OR_31 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_H_OR_31 : 0];
+
+   reg                            internal_beginbursttransfer;
+   reg                            internal_begintransfer;
+   reg [UAV_ADDRESS_W -1 : 0]     uav_address_pre;
+   reg [UAV_BURSTCOUNT_W -1 : 0]  uav_burstcount_pre;
+
+   reg uav_read_pre;
+   reg uav_write_pre;
+   reg read_accepted;
+
+   // -------------------------------------------------
+   // Pass through signals that we don't touch
+   // -------------------------------------------------
+   assign uav_writedata    = av_writedata;
+   assign uav_byteenable   = av_byteenable;
+   assign uav_lock         = av_lock;
+   assign uav_debugaccess  = av_debugaccess;
+   assign uav_clken        = av_clken;
+
+   assign av_readdata      = uav_readdata;
+   assign av_readdatavalid = uav_readdatavalid;
+
+   // -------------------------------------------------
+   // Response signals
+   // -------------------------------------------------
+   always_comb begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE)
+         av_response = '0;
+      else
+         av_response = uav_response;
+
+      if (USE_WRITERESPONSE) begin
+         av_writeresponsevalid = uav_writeresponsevalid;
+      end else begin
+         av_writeresponsevalid = '0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert byte and word addresses into byte addresses
+   // -------------------------------------------------
+   always_comb begin
+      uav_address_pre = {UAV_ADDRESS_W{1'b0}};
+
+      if (AV_ADDRESS_SYMBOLS)
+         uav_address_pre[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      else begin
+         uav_address_pre[ADDRESS_LOW + ADDRESS_HIGH - 1 : ADDRESS_LOW] = av_address[(ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0];
+      end
+   end
+
+   // -------------------------------------------------
+   // Convert burstcount into symbol units
+   // -------------------------------------------------
+   always_comb begin
+      uav_burstcount_pre = symbols_per_word;  // default to a single transfer
+
+      if (USE_BURSTCOUNT) begin
+         uav_burstcount_pre = {UAV_BURSTCOUNT_W{1'b0}};
+         if (AV_BURSTCOUNT_SYMBOLS)
+            uav_burstcount_pre[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) :0] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         else begin
+            uav_burstcount_pre[UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[(BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0) : 0];
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // This is where we perform the per-transfer address and burstcount 
+   // calculations that are required by downstream modules.
+   // -------------------------------------------------
+   reg [UAV_ADDRESS_W -1 : 0] address_register;
+   wire [UAV_BURSTCOUNT_W -1 : 0] burstcount_register;
+   reg [UAV_BURSTCOUNT_W : 0] burstcount_register_lint;
+
+   assign burstcount_register = burstcount_register_lint[UAV_BURSTCOUNT_W -1 : 0];
+
+   always_comb begin
+      uav_address = uav_address_pre;
+      uav_burstcount = uav_burstcount_pre;
+
+      if (AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin
+         uav_address = address_register;
+         uav_burstcount = burstcount_register;
+      end
+   end
+
+   reg first_burst_stalled;
+   reg burst_stalled;
+
+   wire [UAV_ADDRESS_W -1 : 0] combi_burst_addr_reg;
+   wire [UAV_ADDRESS_W -1 : 0] combi_addr_reg;
+
+   generate
+      if (AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST != 0) begin
+         if (AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] };
+         end
+         else begin
+            assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+            assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] };
+         end
+      end
+      else begin
+         assign combi_burst_addr_reg = uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+         assign combi_addr_reg = address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_H_OR_31:0];
+      end
+   endgenerate
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         address_register <= '0;
+         burstcount_register_lint <= '0;
+      end else begin
+         address_register <= address_register;
+         burstcount_register_lint <= burstcount_register_lint;
+
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               address_register <= uav_address_pre;
+               burstcount_register_lint[UAV_BURSTCOUNT_W - 1 : 0] <= uav_burstcount_pre;
+            end else begin
+               address_register <= combi_burst_addr_reg;
+               burstcount_register_lint <= uav_burstcount_pre - symbols_per_word;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               address_register <= combi_addr_reg;
+               burstcount_register_lint <= burstcount_register - symbols_per_word;
+            end
+         end
+      end
+   end
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         first_burst_stalled <= 1'b0;
+         burst_stalled <= 1'b0;
+      end else begin
+         if (internal_beginbursttransfer || first_burst_stalled) begin
+            if (av_waitrequest) begin
+               first_burst_stalled <= 1'b1;
+            end else begin
+               first_burst_stalled <= 1'b0;
+            end
+         end else if (internal_begintransfer || burst_stalled) begin
+            if (~av_waitrequest) begin
+               burst_stalled <= 1'b0;
+            end else begin
+               burst_stalled <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------------------------------------
+   // Waitrequest translation
+   // -------------------------------------------------
+   always @(posedge clk, posedge reset) begin
+      if (reset)
+         read_accepted <= 1'b0;
+      else begin
+         read_accepted <= read_accepted;
+         if (read_accepted == 0)
+            read_accepted <= av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0;
+         else if (read_accepted == 1 && uav_readdatavalid == 1)  // reset acceptance only when rdv arrives
+            read_accepted <= 1'b0;
+      end
+
+   end
+
+   reg write_accepted = 0;
+   generate if (AV_REGISTERINCOMINGSIGNALS) begin
+      always @(posedge clk, posedge reset) begin
+         if (reset)
+            write_accepted <= 1'b0;
+         else begin
+            write_accepted <=
+            ~av_waitrequest ? 1'b0 :
+            uav_write & ~uav_waitrequest? 1'b1 :
+            write_accepted;
+         end
+      end
+   end endgenerate
+
+   always_comb begin
+      av_waitrequest = uav_waitrequest;
+
+      if (USE_READDATAVALID == 0) begin
+         av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest;
+      end
+
+      if (AV_REGISTERINCOMINGSIGNALS) begin
+         av_waitrequest =
+            uav_read_pre ? ~uav_readdatavalid :
+            uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted :
+            1'b1;
+      end
+
+      if (USE_WAITREQUEST == 0) begin
+         av_waitrequest = 0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Determine the output read and write signals from 
+   // the read/write/chipselect input signals.
+   // -------------------------------------------------
+   always_comb begin
+      uav_write      =  1'b0;
+      uav_write_pre  =  1'b0;
+      uav_read       =  1'b0;
+      uav_read_pre   =  1'b0;
+
+      if (!USE_CHIPSELECT) begin
+         if (USE_READ) begin
+            uav_read_pre = av_read;
+         end
+     
+         if (USE_WRITE) begin
+            uav_write_pre = av_write;
+         end
+      end else begin
+         if (!USE_WRITE && USE_READ) begin
+            uav_write_pre = av_chipselect & ~av_read;
+            uav_read_pre = av_read;
+         end else if (!USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_chipselect & ~av_write;
+         end else if (USE_READ && USE_WRITE) begin
+            uav_write_pre = av_write;
+            uav_read_pre = av_read;
+         end
+      end
+
+      if (USE_READDATAVALID == 0)
+         uav_read = uav_read_pre & ~read_accepted;
+      else
+         uav_read = uav_read_pre;
+
+      if (AV_REGISTERINCOMINGSIGNALS == 0)
+         uav_write = uav_write_pre;
+      else
+         uav_write = uav_write_pre & ~write_accepted;
+   end
+
+   // -------------------------------------------------
+   // Begintransfer assignment
+   // -------------------------------------------------
+   reg end_begintransfer;
+
+   always_comb begin
+      if (USE_BEGINTRANSFER) begin
+         internal_begintransfer = av_begintransfer;
+      end else begin
+         internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if (internal_begintransfer == 1 && uav_waitrequest)
+            end_begintransfer <= 1'b1;
+         else if (uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------------------------------------
+   // Beginbursttransfer assignment
+   // -------------------------------------------------
+   reg   end_beginbursttransfer;
+   wire  last_burst_transfer_pre;
+   wire  last_burst_transfer_reg;
+   wire  last_burst_transfer;
+
+   // compare values before the mux to shorten critical path; benchmark before changing
+   assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word);
+   assign last_burst_transfer_reg = (burstcount_register == symbols_per_word);
+   assign last_burst_transfer     = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg;
+
+   always_comb begin
+      if (USE_BEGINBURSTTRANSFER) begin
+         internal_beginbursttransfer = av_beginbursttransfer;
+      end else begin
+         internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer;
+      end
+   end
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         end_beginbursttransfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= end_beginbursttransfer;
+         if (last_burst_transfer && internal_begintransfer || uav_read) begin
+            end_beginbursttransfer <= 1'b0;
+         end
+         else if (uav_write && internal_begintransfer) begin
+            end_beginbursttransfer <= 1'b1;
+         end
+      end
+   end
+
+   // synthesis translate_off
+
+   // ------------------------------------------------
+   // check_1   : for waitrequest signal violation
+   //             Ensure that when waitreqeust is asserted, the master is not allowed to change its controls
+   // Exception : begintransfer / beginbursttransfer
+   //           : previously not in any transaction (idle)
+   // Note : Not checking clken which is not exactly part of Avalon controls/inputs
+   //      : Not using system verilog assertions (seq/prop) since it is not supported if using Modelsim_SE
+   // ------------------------------------------------
+
+   reg av_waitrequest_r;
+   reg av_write_r, av_read_r, av_lock_r, av_chipselect_r, av_debugaccess_r;
+   reg [AV_ADDRESS_W-1:0]    av_address_r;
+   reg [AV_BYTEENABLE_W-1:0] av_byteenable_r;
+   reg [AV_BURSTCOUNT_W-1:0] av_burstcount_r;
+   reg [AV_DATA_W-1:0]       av_writedata_r;
+
+   always @(posedge clk or posedge reset) begin
+      if (reset) begin
+         av_waitrequest_r           <= '0;
+         av_write_r                 <= '0;
+         av_read_r                  <= '0;
+         av_lock_r                  <= '0;
+         av_chipselect_r            <= '0;
+         av_debugaccess_r           <= '0;
+         av_address_r               <= '0;
+         av_byteenable_r            <= '0;
+         av_burstcount_r            <= '0;
+         av_writedata_r             <= '0;
+      end else begin
+         av_waitrequest_r           <= av_waitrequest;
+         av_write_r                 <= av_write;
+         av_read_r                  <= av_read;
+         av_lock_r                  <= av_lock;
+         av_chipselect_r            <= av_chipselect;
+         av_debugaccess_r           <= av_debugaccess;
+         av_address_r               <= av_address;
+         av_byteenable_r            <= av_byteenable;
+         av_burstcount_r            <= av_burstcount;
+         av_writedata_r             <= av_writedata;
+   
+         if (
+            av_waitrequest_r && // When waitrequest is asserted
+            (
+               (av_write                  != av_write_r) ||   // Checks that : Input controls/data does not change
+               (av_read                   != av_read_r)  ||
+               (av_lock                   != av_lock_r)  ||
+               (av_debugaccess            != av_debugaccess_r) ||
+               (av_address                != av_address_r) ||
+               (av_byteenable             != av_byteenable_r) ||
+               (av_burstcount             != av_burstcount_r)
+            )  &&
+            (av_write_r | av_read_r) &&         // Check only when : previously initiated a write/read
+            (!USE_CHIPSELECT | av_chipselect_r) //                   and chipselect was asserted (or unused)
+         ) begin
+            $display( "%t: %m: Error: Input controls/data changed while av_waitrequest is asserted.", $time());
+            $display("av_address                %x --> %x", av_address_r               , av_address               );
+            $display("av_byteenable             %x --> %x", av_byteenable_r            , av_byteenable            );
+            $display("av_burstcount             %x --> %x", av_burstcount_r            , av_burstcount            );
+            $display("av_writedata              %x --> %x", av_writedata_r             , av_writedata             );
+            $display("av_write                  %x --> %x", av_write_r                 , av_write                 );
+            $display("av_read                   %x --> %x", av_read_r                  , av_read                  );
+            $display("av_lock                   %x --> %x", av_lock_r                  , av_lock                  );
+            $display("av_chipselect             %x --> %x", av_chipselect_r            , av_chipselect            );
+            $display("av_debugaccess            %x --> %x", av_debugaccess_r           , av_debugaccess           );
+         end
+      end
+   
+   // end check_1
+   
+   end
+
+  // synthesis translate_on
+
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_agent.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_agent.sv
new file mode 100644
index 0000000..c9b12f9
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_agent.sv
@@ -0,0 +1,622 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2011 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_agent
+#(
+   // Packet parameters
+   parameter PKT_BEGIN_BURST           = 81,
+   parameter PKT_DATA_H                = 31,
+   parameter PKT_DATA_L                = 0,
+   parameter PKT_SYMBOL_W              = 8,
+   parameter PKT_BYTEEN_H              = 71,
+   parameter PKT_BYTEEN_L              = 68,
+   parameter PKT_ADDR_H                = 63,
+   parameter PKT_ADDR_L                = 32,
+   parameter PKT_TRANS_LOCK            = 87,
+   parameter PKT_TRANS_COMPRESSED_READ = 67,
+   parameter PKT_TRANS_POSTED          = 66, 
+   parameter PKT_TRANS_WRITE           = 65,
+   parameter PKT_TRANS_READ            = 64,
+   parameter PKT_SRC_ID_H              = 74,
+   parameter PKT_SRC_ID_L              = 72,
+   parameter PKT_DEST_ID_H             = 77,
+   parameter PKT_DEST_ID_L             = 75,
+   parameter PKT_BURSTWRAP_H           = 85,
+   parameter PKT_BURSTWRAP_L           = 82,
+   parameter PKT_BYTE_CNT_H            = 81,
+   parameter PKT_BYTE_CNT_L            = 78,
+   parameter PKT_PROTECTION_H          = 86,
+   parameter PKT_PROTECTION_L          = 86,
+   parameter PKT_RESPONSE_STATUS_H     = 89,
+   parameter PKT_RESPONSE_STATUS_L     = 88,
+   parameter PKT_BURST_SIZE_H          = 92,
+   parameter PKT_BURST_SIZE_L          = 90,
+   parameter PKT_ORI_BURST_SIZE_L      = 93,
+   parameter PKT_ORI_BURST_SIZE_H      = 95,
+   parameter ST_DATA_W                 = 96,
+   parameter ST_CHANNEL_W              = 32,
+
+   // Slave parameters
+   parameter ADDR_W           = PKT_ADDR_H - PKT_ADDR_L + 1,
+   parameter AVS_DATA_W       = PKT_DATA_H - PKT_DATA_L + 1,
+   parameter AVS_BURSTCOUNT_W = 4,
+   parameter PKT_SYMBOLS      = AVS_DATA_W / PKT_SYMBOL_W,
+
+   // Slave agent parameters
+   parameter PREVENT_FIFO_OVERFLOW = 0,
+   parameter SUPPRESS_0_BYTEEN_CMD = 1,
+   parameter USE_READRESPONSE      = 0,
+   parameter USE_WRITERESPONSE     = 0,
+
+   // Derived slave parameters
+   parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
+   parameter BURST_SIZE_W = 3,
+
+   // Derived FIFO width
+   parameter FIFO_DATA_W = ST_DATA_W + 1,
+   
+   // ECC parameter
+   parameter ECC_ENABLE = 0
+) (
+   input                         clk,
+   input                         reset,
+
+   // Universal-Avalon anti-slave
+   output [ADDR_W-1:0]           m0_address,
+   output [AVS_BURSTCOUNT_W-1:0] m0_burstcount,
+   output [AVS_BE_W-1:0]         m0_byteenable,
+   output                        m0_read,
+   input [AVS_DATA_W-1:0]        m0_readdata,
+   input                         m0_waitrequest,
+   output                        m0_write,
+   output [AVS_DATA_W-1:0]       m0_writedata,
+   input                         m0_readdatavalid,
+   output                        m0_debugaccess,
+   output                        m0_lock,
+   input [1:0]                   m0_response,
+   input                         m0_writeresponsevalid,
+
+   // Avalon-ST FIFO interfaces.
+   // Note: there's no need to include the "data" field here, at least for
+   // reads, since readdata is filled in from slave info.  To keep life
+   // simple, have a data field, but fill it with 0s.
+   // Av-st response fifo source interface
+   output reg [FIFO_DATA_W-1:0]  rf_source_data,
+   output                        rf_source_valid,
+   output                        rf_source_startofpacket,
+   output                        rf_source_endofpacket,
+   input                         rf_source_ready,
+
+   // Av-st response fifo sink interface
+   input [FIFO_DATA_W-1:0]       rf_sink_data,
+   input                         rf_sink_valid,
+   input                         rf_sink_startofpacket,
+   input                         rf_sink_endofpacket,
+   output                        rf_sink_ready,
+
+   // Av-st readdata fifo src interface, data and response
+   // extra 2 bits for storing RESPONSE STATUS
+   output [AVS_DATA_W+1:0]       rdata_fifo_src_data,
+   output                        rdata_fifo_src_valid,
+   input                         rdata_fifo_src_ready,
+
+   // Av-st readdata fifo sink interface
+   input [AVS_DATA_W+1:0]        rdata_fifo_sink_data,
+   input                         rdata_fifo_sink_valid,
+   output                        rdata_fifo_sink_ready,
+   input                         rdata_fifo_sink_error,
+
+   // Av-st sink command packet interface
+   output                        cp_ready,
+   input                         cp_valid,
+   input [ST_DATA_W-1:0]         cp_data,
+   input [ST_CHANNEL_W-1:0]      cp_channel,
+   input                         cp_startofpacket,
+   input                         cp_endofpacket,
+
+   // Av-st source response packet interface
+   input                         rp_ready,
+   output reg                    rp_valid,
+   output reg [ST_DATA_W-1:0]    rp_data,
+   output                        rp_startofpacket,
+   output                        rp_endofpacket
+);
+
+   // --------------------------------------------------
+   // Ceil(log2()) function log2ceil of 4 = 2
+   // --------------------------------------------------
+   function integer log2ceil;
+      input reg[63:0] val;
+      reg [63:0] i;
+   
+      begin
+         i = 1;
+         log2ceil = 0;
+
+         while (i < val) begin
+            log2ceil = log2ceil + 1;
+            i = i << 1;
+         end
+      end
+   endfunction     
+
+   // ------------------------------------------------
+   // Local Parameters
+   // ------------------------------------------------
+   localparam DATA_W       = PKT_DATA_H - PKT_DATA_L + 1;
+   localparam BE_W         = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+   localparam MID_W        = PKT_SRC_ID_H - PKT_SRC_ID_L + 1;
+   localparam SID_W        = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+   localparam BYTE_CNT_W   = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
+   localparam BURSTWRAP_W  = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1;
+   localparam BURSTSIZE_W  = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1;
+   localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS);
+   localparam MAX_BURST    = 1 << (AVS_BURSTCOUNT_W - 1);
+   localparam BURSTING     = (MAX_BURST > PKT_SYMBOLS);
+
+   // ------------------------------------------------
+   // Signals
+   // ------------------------------------------------
+   wire [DATA_W-1:0]      cmd_data;
+   wire [BE_W-1:0]        cmd_byteen;
+   wire [ADDR_W-1:0]      cmd_addr;
+   wire [MID_W-1:0]       cmd_mid;
+   wire [SID_W-1:0]       cmd_sid;
+   wire                   cmd_read;
+   wire                   cmd_write;
+   wire                   cmd_compressed;
+   wire                   cmd_posted;
+   wire [BYTE_CNT_W-1:0]  cmd_byte_cnt;
+   wire [BURSTWRAP_W-1:0] cmd_burstwrap;
+   wire [BURSTSIZE_W-1:0] cmd_burstsize;
+   wire                   cmd_debugaccess;
+
+   wire                   suppress_cmd;
+   wire                   byteen_asserted;
+   wire                   suppress_read;
+   wire                   suppress_write;
+   wire                   needs_response_synthesis;
+   wire                   generate_response;
+
+   // Assign command fields
+   assign cmd_data         = cp_data[PKT_DATA_H  :PKT_DATA_L  ];
+   assign cmd_byteen       = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L];
+   assign cmd_addr         = cp_data[PKT_ADDR_H  :PKT_ADDR_L  ];
+   assign cmd_compressed   = cp_data[PKT_TRANS_COMPRESSED_READ];
+   assign cmd_posted       = cp_data[PKT_TRANS_POSTED];
+   assign cmd_write        = cp_data[PKT_TRANS_WRITE];
+   assign cmd_read         = cp_data[PKT_TRANS_READ];
+   assign cmd_mid          = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L];
+   assign cmd_sid          = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
+   assign cmd_byte_cnt     = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   assign cmd_burstwrap    = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   assign cmd_burstsize    = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   assign cmd_debugaccess  = cp_data[PKT_PROTECTION_L];
+
+   // Local "ready_for_command" signal: deasserted when the agent is unable to accept
+   // another command, e.g. rdv FIFO is full, (local readdata storage is full &&
+   // ~rp_ready), ...
+   // Say, this could depend on the type of command, for example, even if the
+   // rdv FIFO is full, a write request can be accepted.  For later.
+   wire ready_for_command;
+
+   wire local_lock  = cp_valid & cp_data[PKT_TRANS_LOCK];
+   wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE];
+   wire local_read  = cp_valid & cp_data[PKT_TRANS_READ];
+   wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ];
+   wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket;
+
+   // num_symbols is PKT_SYMBOLS, appropriately sized.
+   wire [31:0] int_num_symbols = PKT_SYMBOLS;
+   wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
+
+   generate
+      if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow_block
+         // ---------------------------------------------------
+         // Backpressure if the slave says to, or if FIFO overflow may occur.
+         // 
+         // All commands are backpressured once the FIFO is full
+         // even if they don't need storage. This breaks a long
+         // combinatorial path from the master read/write through
+         // this logic and back to the master via the backpressure
+         // path.
+         //
+         // To avoid a loss of throughput the FIFO will be parameterized 
+         // one slot deeper. The extra slot should never be used in normal
+         // operation, but should a slave misbehave and accept one more
+         // read than it should then backpressure will kick in.
+         //
+         // An example: assume a slave with MPRT = 2. It can accept a
+         // command sequence RRWW without backpressuring. If the FIFO is
+         // only 2 deep, we'd backpressure the writes leading to loss of
+         // throughput. If the FIFO is 3 deep, we'll only backpressure when
+         // RRR... which is an illegal condition anyway.
+         // ---------------------------------------------------
+
+         assign ready_for_command = rf_source_ready;
+         assign cp_ready = (~m0_waitrequest | suppress_cmd) && ready_for_command;
+
+      end else begin : no_prevent_fifo_overflow_block
+
+         // Do not suppress the command or the slave will
+         // not be able to waitrequest
+         assign ready_for_command = 1'b1;
+         // Backpressure only if the slave says to.
+         assign cp_ready = ~m0_waitrequest | suppress_cmd;
+
+      end
+   endgenerate
+
+   generate if (SUPPRESS_0_BYTEEN_CMD && !BURSTING) begin : suppress_0_byteen_cmd_non_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = ~byteen_asserted;
+      assign suppress_cmd     = ~byteen_asserted;
+   end else if (SUPPRESS_0_BYTEEN_CMD && BURSTING) begin: suppress_0_byteen_cmd_bursting
+      assign byteen_asserted  = |cmd_byteen;
+      assign suppress_read    = ~byteen_asserted;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = ~byteen_asserted && cmd_read;
+   end else begin : no_suppress_0_byteen_cmd
+      assign suppress_read    = 1'b0;
+      assign suppress_write   = 1'b0;
+      assign suppress_cmd     = 1'b0;
+   end
+   endgenerate
+
+   // -------------------------------------------------------------------
+   // Extract avalon signals from command packet.
+   // -------------------------------------------------------------------
+   // Mask off the lower bits of address.
+   // The burst adapter before this component will break narrow sized packets
+   // into sub-bursts of length 1. However, the packet addresses are preserved,
+   // which means this component may see size-aligned addresses.
+   //
+   // Masking ensures that the addresses seen by an Avalon slave are aligned to 
+   // the full data width instead of the size.
+   //
+   // Example:
+   // output from burst adapter (datawidth=4, size=2 bytes):
+   // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6
+   // expected output from slave agent:
+   // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4
+   generate 
+      if (BITS_TO_MASK > 0) begin : mask_address
+
+         assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} };
+
+      end else begin : no_mask_address
+
+         assign m0_address = cmd_addr;
+
+      end
+   endgenerate
+
+   assign m0_byteenable = cmd_byteen;
+   assign m0_writedata  = cmd_data;
+
+   // Note: no Avalon-MM slave in existence accepts uncompressed read bursts -
+   // this sort of burst exists only in merlin fabric ST packets. What to do
+   // if we see such a burst? All beats in that burst need to be transmitted
+   // to the slave so we have enough space-time for byteenable expression.
+   //
+   // There can be multiple bursts in a packet, but only one beat per burst
+   // in <most> cases. The exception is when we've decided not to insert a
+   // burst adapter for efficiency reasons, in which case this agent is also
+   // responsible for driving burstcount to 1 on each beat of an uncompressed
+   // read burst.
+
+   assign m0_read = ready_for_command & !suppress_read & (local_compressed_read | local_read);
+
+   generate 
+       // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal.  Assign m0_burstcount
+       // from a sub-range, or 0-pad, as appropriate.
+       if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin : m0_burstcount_zero_pad
+          wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}};
+          assign m0_burstcount = (local_read & ~local_compressed_read) ?
+             {zero_pad, num_symbols} :
+             {zero_pad, cmd_byte_cnt};
+       end
+       else begin : m0_burstcount_no_pad
+          assign m0_burstcount = (local_read & ~local_compressed_read) ? 
+          num_symbols[AVS_BURSTCOUNT_W-1:0] : 
+          cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0];
+       end
+   endgenerate
+
+   assign m0_write = ready_for_command & local_write & !suppress_write;
+   assign m0_lock  = ready_for_command & local_lock & (m0_read | m0_write);
+   assign m0_debugaccess  = cmd_debugaccess;
+
+   // -------------------------------------------------------------------
+   // Indirection layer for response packet values.  Some may always wire
+   // directly from the slave translator; others will no doubt emerge from
+   // various FIFOs.
+   // What to put in resp_data when a write occured? Answer: it does not
+   // matter, because only response status is needed for non-posted writes,
+   // and the packet already has a field for that.
+   //
+   // We use the rdata_fifo to store write responses as well. This allows us
+   // to handle backpressure on the response path, and allows write response
+   // merging.
+   assign rdata_fifo_src_valid = m0_readdatavalid | m0_writeresponsevalid;
+   assign rdata_fifo_src_data  = {m0_response, m0_readdata};
+
+   // ------------------------------------------------------------------
+   // Generate a token when read commands are suppressed. The token
+   // is stored in the response FIFO, and will be used to synthesize 
+   // a read response. The same token is used for non-posted write
+   // response synthesis.
+   //
+   // Note: this token is not generated for suppressed uncompressed read cycles;
+   // the burst uncompression logic at the read side of the response FIFO
+   // generates the correct number of responses.
+   //
+   // When the slave can return the response, let it do its job. Don't 
+   // synthesize a response in that case, unless we've suppressed the
+   // the last transfer in a write sub-burst.
+   // ------------------------------------------------------------------
+   wire write_end_of_subburst;
+   assign needs_response_synthesis = ((local_read | local_compressed_read) & suppress_read) || 
+                                        (!USE_WRITERESPONSE && nonposted_write_endofpacket) ||
+                                        (USE_WRITERESPONSE && write_end_of_subburst && suppress_write);
+
+   // Avalon-ST interfaces to external response FIFO.
+   //
+   // For efficiency, when synthesizing a write response we only store a non-posted write 
+   // transaction at its endofpacket, even if it was split into multiple sub-bursts.
+   //
+   // When not synthesizing write responses, we store each sub-burst in the FIFO.
+   // Each sub-burst to the slave will return a response, which corresponds to one 
+   // entry in the FIFO. We merge all the sub-burst responses on the final
+   // sub-burst and send it on the response channel.
+
+   wire internal_cp_endofburst;
+   wire [31:0] minimum_bytecount_wire = PKT_SYMBOLS; // to solve qis warning
+   wire [AVS_BURSTCOUNT_W-1:0] minimum_bytecount;
+
+   assign minimum_bytecount = minimum_bytecount_wire[AVS_BURSTCOUNT_W-1:0];
+   assign internal_cp_endofburst = (cmd_byte_cnt == minimum_bytecount);
+   assign write_end_of_subburst = local_write & internal_cp_endofburst;
+
+   assign rf_source_valid = (local_read | local_compressed_read | (nonposted_write_endofpacket && !USE_WRITERESPONSE) | (USE_WRITERESPONSE && internal_cp_endofburst && local_write))
+                             & ready_for_command & cp_ready;
+   assign rf_source_startofpacket = cp_startofpacket;
+   assign rf_source_endofpacket   = cp_endofpacket;
+   always @* begin
+      // default: assign every command packet field to the response FIFO...
+      rf_source_data                                  = {1'b0, cp_data};
+
+      // ... and override select fields as needed.
+      rf_source_data[FIFO_DATA_W-1]                      = needs_response_synthesis;
+      rf_source_data[PKT_DATA_H   :PKT_DATA_L]           = {DATA_W {1'b0}};
+      rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L]         = cmd_byteen;
+      rf_source_data[PKT_ADDR_H   :PKT_ADDR_L]           = cmd_addr;
+      rf_source_data[PKT_TRANS_COMPRESSED_READ]          = cmd_compressed;
+      rf_source_data[PKT_TRANS_POSTED]                   = cmd_posted;
+      rf_source_data[PKT_TRANS_WRITE]                    = cmd_write;
+      rf_source_data[PKT_TRANS_READ]                     = cmd_read;
+      rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L]         = cmd_mid;
+      rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L]        = cmd_sid;
+      rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]      = cmd_byte_cnt;
+      rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]    = cmd_burstwrap;
+      rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]  = cmd_burstsize;
+      rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L]  = '0;
+      rf_source_data[PKT_PROTECTION_L]                   = cmd_debugaccess;
+   end
+
+   wire uncompressor_source_valid;
+   wire [BURSTSIZE_W-1:0] uncompressor_burstsize;
+   wire last_write_response;
+
+   // last_write_response indicates the last response of the broken-up write burst (sub-bursts).
+   // At this time, the final merged response is sent, and rp_valid is only asserted
+   // once for the whole burst.
+   generate
+      if (USE_WRITERESPONSE) begin
+         assign last_write_response = rf_sink_data[PKT_TRANS_WRITE] & rf_sink_endofpacket;
+         always @* begin
+            if (rf_sink_data[PKT_TRANS_WRITE] == 1) 
+               rp_valid = (rdata_fifo_sink_valid | generate_response) & last_write_response & !rf_sink_data[PKT_TRANS_POSTED];
+            else
+               rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end else begin
+         assign last_write_response = 1'b0;
+         always @* begin
+            rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid;
+         end
+      end
+   endgenerate
+
+   // ------------------------------------------------------------------
+   // Response merging
+   // ------------------------------------------------------------------
+   reg [1:0] current_response;
+   reg [1:0] response_merged;
+   generate
+     if (USE_WRITERESPONSE) begin : response_merging_all
+        reg first_write_response;
+        reg reset_merged_output;
+        reg [1:0] previous_response_in;
+        reg [1:0]  previous_response;
+
+        always_ff @(posedge clk, posedge reset) begin
+           if (reset) begin
+              first_write_response  <= 1'b1;
+           end 
+           else begin // Merging work for write response, for read: previous_response_in = current_response
+              if (rf_sink_valid & (rdata_fifo_sink_valid | generate_response) & rf_sink_data[PKT_TRANS_WRITE]) begin
+                 first_write_response <= 1'b0;
+                 if (rf_sink_endofpacket)
+                    first_write_response <= 1'b1;
+              end
+           end
+        end
+
+        always_comb begin
+           current_response = generate_response ? 2'b00 : rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | {2{rdata_fifo_sink_error}};
+           reset_merged_output = first_write_response && (rdata_fifo_sink_valid || generate_response);
+           previous_response_in = reset_merged_output ? current_response : previous_response;
+           response_merged = current_response >= previous_response ? current_response: previous_response_in;
+        end
+
+        always_ff @(posedge clk or posedge reset) begin
+           if (reset) begin 
+              previous_response <= 2'b00;
+           end
+           else begin
+              if (rf_sink_valid & (rdata_fifo_sink_valid || generate_response)) begin
+                 previous_response <= response_merged;
+              end
+           end
+        end
+     end else begin : response_merging_read_only
+        always @* begin
+           current_response = generate_response ? 2'b00: rdata_fifo_sink_data[AVS_DATA_W+1:AVS_DATA_W] | 
+                                                         {2{rdata_fifo_sink_error}};
+           response_merged = current_response;
+        end
+     end
+   endgenerate
+
+   assign generate_response = rf_sink_data[FIFO_DATA_W-1];
+
+   wire [BYTE_CNT_W-1:0]  rf_sink_byte_cnt   = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L];
+   wire                   rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+   wire [BURSTWRAP_W-1:0] rf_sink_burstwrap  = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L];
+   wire [BURSTSIZE_W-1:0] rf_sink_burstsize  = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L];
+   wire [ADDR_W-1:0]      rf_sink_addr       = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L];
+   // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo
+   wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket;    
+
+   wire [BYTE_CNT_W-1:0]   burst_byte_cnt;
+   wire [BURSTWRAP_W-1:0]  rp_burstwrap;
+   wire [ADDR_W-1:0]       rp_address;
+   wire                    rp_is_compressed;
+   wire                    ready_for_response;
+
+   // ------------------------------------------------------------------
+   // We're typically ready for a response if the network is ready. There
+   // is one exception:
+   //
+   // If the slave issues write responses, we only issue a merged response on 
+   // the final sub-burst. As a result, we only care about response channel 
+   // availability on the final burst when we send out the merged response.
+   // ------------------------------------------------------------------
+   assign ready_for_response = (USE_WRITERESPONSE) ? 
+                            rp_ready || (rf_sink_data[PKT_TRANS_WRITE] && !last_write_response) || rf_sink_data[PKT_TRANS_POSTED]: 
+                            rp_ready;
+
+   // ------------------------------------------------------------------
+   // Backpressure the readdata fifo if we're supposed to synthesize a response.
+   // This may be a read response (for suppressed reads) or a write response
+   // (for non-posted writes).
+   // ------------------------------------------------------------------
+   assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & ready_for_response & ~(rf_sink_valid & generate_response);
+
+   always @* begin
+      // By default, return all fields...
+      rp_data                                               = rf_sink_data[ST_DATA_W - 1 : 0];
+
+      // ... and override specific fields.
+      rp_data[PKT_DATA_H   :PKT_DATA_L]                     = rdata_fifo_sink_data[AVS_DATA_W-1:0];
+      // Assignments directly from the response fifo.
+      rp_data[PKT_TRANS_POSTED]                             = rf_sink_data[PKT_TRANS_POSTED];
+      rp_data[PKT_TRANS_WRITE]                              = rf_sink_data[PKT_TRANS_WRITE];
+      rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]                   = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+      rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]                  = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
+      rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L]                   = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L];
+      rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L]            = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L];
+
+      // Burst uncompressor assignments
+      rp_data[PKT_ADDR_H   :PKT_ADDR_L]                     = rp_address;
+      rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]              = rp_burstwrap;
+      rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]                = burst_byte_cnt;
+      rp_data[PKT_TRANS_READ]                               = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ];
+      rp_data[PKT_TRANS_COMPRESSED_READ]                    = rp_is_compressed;
+
+      rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L]  = response_merged;
+      rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]            = uncompressor_burstsize;
+      // bounce the original size back to the master untouched
+      rp_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L]    = rf_sink_data[PKT_ORI_BURST_SIZE_H:PKT_ORI_BURST_SIZE_L];
+   end
+
+   // ------------------------------------------------------------------
+   // Note: the burst uncompressor may be asked to generate responses for
+   // write packets; these are treated the same as single-cycle uncompressed 
+   // reads.
+   // ------------------------------------------------------------------
+   altera_merlin_burst_uncompressor #(
+      .ADDR_W               (ADDR_W),
+      .BURSTWRAP_W          (BURSTWRAP_W),
+      .BYTE_CNT_W           (BYTE_CNT_W),
+      .PKT_SYMBOLS          (PKT_SYMBOLS),
+      .BURST_SIZE_W         (BURSTSIZE_W)
+   ) uncompressor (
+      .clk                  (clk),
+      .reset                (reset),
+      .sink_startofpacket   (rf_sink_startofpacket_wire),
+      .sink_endofpacket     (rf_sink_endofpacket),
+      .sink_valid           (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)),
+      .sink_ready           (rf_sink_ready),
+      .sink_addr            (rf_sink_addr),
+      .sink_burstwrap       (rf_sink_burstwrap),
+      .sink_byte_cnt        (rf_sink_byte_cnt),
+      .sink_is_compressed   (rf_sink_compressed),
+      .sink_burstsize       (rf_sink_burstsize),
+
+      .source_startofpacket (rp_startofpacket),
+      .source_endofpacket   (rp_endofpacket),
+      .source_valid         (uncompressor_source_valid),
+      .source_ready         (ready_for_response),
+      .source_addr          (rp_address),
+      .source_burstwrap     (rp_burstwrap),
+      .source_byte_cnt      (burst_byte_cnt),
+      .source_is_compressed (rp_is_compressed),
+      .source_burstsize     (uncompressor_burstsize)
+   );
+
+   //--------------------------------------
+   // Assertion: In case slave support response. The slave needs return response in order
+   // Ex: non-posted write followed by a read: write response must complete before read data 
+   //--------------------------------------
+   // synthesis translate_off      
+   ERROR_write_response_and_read_response_cannot_happen_same_time:
+   assert property ( @(posedge clk)
+      disable iff (reset) !(m0_writeresponsevalid  && m0_readdatavalid)
+   );    
+
+   // synthesis translate_on
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_translator.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_translator.sv
new file mode 100644
index 0000000..454ac33
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_merlin_slave_translator.sv
@@ -0,0 +1,482 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Slave Translator
+//
+// Translates Universal Avalon  MM Slave
+// to any Avalon MM Slave
+// -------------------------------------
+//
+//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
+//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
+//The key feature here is that no same cycle turnaround data is processed through the fabric.
+
+//import avalon_utilities_pkg::*;
+
+`timescale 1 ns / 1 ns
+
+module altera_merlin_slave_translator #(
+   parameter
+   //Widths
+   AV_ADDRESS_W           = 32,
+   AV_DATA_W              = 32,
+   AV_BURSTCOUNT_W        = 4,
+   AV_BYTEENABLE_W        = 4,
+   UAV_BYTEENABLE_W       = 4,
+
+   //Read Latency
+   AV_READLATENCY          = 1,
+
+   //Timing
+   AV_READ_WAIT_CYCLES     = 0,
+   AV_WRITE_WAIT_CYCLES    = 0,
+   AV_SETUP_WAIT_CYCLES    = 0,
+   AV_DATA_HOLD_CYCLES     = 0,
+
+   //Optional Port Declarations
+   USE_READDATAVALID       = 1,
+   USE_WAITREQUEST         = 1,
+   USE_READRESPONSE        = 0,
+   USE_WRITERESPONSE       = 0,
+
+   //Variable Addressing
+   AV_SYMBOLS_PER_WORD     = 4,
+   AV_ADDRESS_SYMBOLS      = 0,
+   AV_BURSTCOUNT_SYMBOLS   = 0,
+   BITS_PER_WORD           = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
+   UAV_ADDRESS_W           = 38,
+   UAV_BURSTCOUNT_W        = 10,
+   UAV_DATA_W              = 32,
+
+   AV_CONSTANT_BURST_BEHAVIOR       = 0,
+   UAV_CONSTANT_BURST_BEHAVIOR      = 0,
+   CHIPSELECT_THROUGH_READLATENCY   = 0,
+
+   // Tightly-Coupled Options
+   USE_UAV_CLKEN           = 0,
+   AV_REQUIRE_UNALIGNED_ADDRESSES = 0
+) (
+
+   // -------------------
+   // Clock & Reset
+   // -------------------
+   input wire                             clk,
+   input wire                             reset,
+
+   // -------------------
+   // Universal Avalon Slave
+   // -------------------
+
+   input wire [UAV_ADDRESS_W - 1 : 0]     uav_address,
+   input wire [UAV_DATA_W - 1 : 0]        uav_writedata,
+   input wire                             uav_write,
+   input wire                             uav_read,
+   input wire [UAV_BURSTCOUNT_W - 1 : 0]  uav_burstcount,
+   input wire [UAV_BYTEENABLE_W - 1 : 0]  uav_byteenable,
+   input wire                             uav_lock,
+   input wire                             uav_debugaccess,
+   input wire                             uav_clken,
+
+   output logic                           uav_readdatavalid,
+   output logic                           uav_waitrequest,
+   output logic [UAV_DATA_W - 1 : 0]      uav_readdata,
+   output logic [1:0]                     uav_response,
+   // input wire                             uav_writeresponserequest,
+   output logic                           uav_writeresponsevalid,
+
+   // -------------------
+   // Customizable Avalon Master
+   // -------------------
+   output logic [AV_ADDRESS_W - 1 : 0]    av_address,
+   output logic [AV_DATA_W - 1 : 0]       av_writedata,
+   output logic                           av_write,
+   output logic                           av_read,
+   output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
+   output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
+   output logic                           av_begintransfer,
+   output wire                            av_chipselect,
+   output logic                           av_beginbursttransfer,
+   output logic                           av_lock,
+   output wire                            av_clken,
+   output wire                            av_debugaccess,
+   output wire                            av_outputenable,
+
+   input logic [AV_DATA_W - 1 : 0]        av_readdata,
+   input logic                            av_readdatavalid,
+   input logic                            av_waitrequest,
+
+   input logic [1:0]                      av_response,
+   // output logic                           av_writeresponserequest,
+   input wire                             av_writeresponsevalid
+
+);
+
+   function integer clog2_plusone;
+      input [31:0] Depth;
+      integer i;
+      begin
+         i = Depth;
+         for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
+            i = i >> 1;
+      end
+   endfunction
+
+   function integer max;
+      //returns the larger of two passed arguments
+      input [31:0] one;
+      input [31:0] two;
+      if(one > two)
+         max=one;
+      else
+         max=two;
+   endfunction // int
+
+   localparam AV_READ_WAIT_INDEXED      = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
+   localparam AV_WRITE_WAIT_INDEXED     = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
+   localparam AV_DATA_HOLD_INDEXED      = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
+   localparam LOG2_OF_LATENCY_SUM       = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
+   localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_SHIFT_SELECTOR    = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
+   localparam ADDRESS_HIGH              = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
+                                          AV_ADDRESS_W :
+                                          UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
+   localparam BURSTCOUNT_HIGH           = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
+                                          AV_BURSTCOUNT_W :
+                                          UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
+   localparam BYTEENABLE_ADDRESS_BITS   = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
+
+
+   // Calculate the symbols per word as the power of 2 extended symbols per word
+   wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
+   wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
+
+   // +--------------------------------
+   // |Backwards Compatibility Signals
+   // +--------------------------------
+   assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
+   assign av_debugaccess = uav_debugaccess;
+
+   // +-------------------
+   // |Passthru Signals
+   // +-------------------
+
+   reg [1 : 0] av_response_delayed;
+
+   always @(posedge clk, posedge reset) begin
+      if (reset) begin
+         av_response_delayed <= 2'b0;
+      end else begin
+         av_response_delayed <= av_response;
+      end
+   end
+
+   always_comb
+   begin
+      if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
+         uav_response = '0;
+      end else begin
+         if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
+            uav_response = av_response;
+         end else begin
+            uav_response = av_response_delayed;
+         end
+      end
+   end
+   // assign av_writeresponserequest = uav_writeresponserequest;
+   assign uav_writeresponsevalid = av_writeresponsevalid;
+
+   //-------------------------
+   //Writedata and Byteenable
+   //-------------------------
+
+   always@* begin
+      av_byteenable = '0;
+      av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   always@* begin
+      av_writedata = '0;
+      av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
+   end
+
+   // +-------------------
+   // |Calculated Signals
+   // +-------------------
+
+   logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
+
+   function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
+      input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
+
+      for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
+         if(byteenable[i] == 1) begin
+            return i;
+         end
+      end
+
+      return '0;
+
+   endfunction
+
+   reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
+   reg [AV_ADDRESS_W    - 1 : 0] address_reg;
+   always@(posedge clk, posedge reset) begin
+      if(reset) begin
+         burstcount_reg <= '0;
+         address_reg    <= '0;
+      end else begin
+         burstcount_reg <= burstcount_reg;
+         address_reg    <= address_reg;
+         if(av_beginbursttransfer) begin
+            burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+            address_reg    <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+         end
+      end
+   end
+
+   logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
+
+   always@* begin
+      if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
+         temp_wire = decode_byteenable(uav_byteenable);
+         real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
+      end else begin
+         real_uav_address = uav_address;
+      end
+
+      av_address = real_uav_address[ADDRESS_HIGH - 1  + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_address = address_reg;
+   end
+
+   always@* begin
+      av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
+      if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
+         av_burstcount = burstcount_reg;
+   end
+
+   always@* begin
+      av_lock = uav_lock;
+   end
+
+   // -------------------
+   // Writebyteenable Assignment
+   // -------------------
+   always@* begin
+      av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
+   end
+
+   // -------------------
+   // Waitrequest Assignment
+   // -------------------
+
+   reg av_waitrequest_generated;
+   reg av_waitrequest_generated_read;
+   reg av_waitrequest_generated_write;
+   reg waitrequest_reset_override;
+   reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         wait_latency_counter <= '0;
+         waitrequest_reset_override <= 1'h1;
+      end else begin
+         waitrequest_reset_override <= 1'h0;
+         wait_latency_counter <= '0;
+         if( ~uav_waitrequest | waitrequest_reset_override )
+            wait_latency_counter <= '0;
+         else if( uav_read | uav_write )
+            wait_latency_counter <= wait_latency_counter + 1'h1;
+      end
+   end
+
+
+   always @* begin
+
+      av_read  = uav_read;
+      av_write = uav_write;
+      av_waitrequest_generated         = 1'h1;
+      av_waitrequest_generated_read    = 1'h1;
+      av_waitrequest_generated_write   = 1'h1;
+
+      if(LOG2_OF_LATENCY_SUM == 1)
+         av_waitrequest_generated = 0;
+
+      if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
+         av_read  = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
+         av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
+         av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
+         av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
+
+         if(uav_write)
+            av_waitrequest_generated = av_waitrequest_generated_write;
+         else
+            av_waitrequest_generated = av_waitrequest_generated_read;
+
+      end
+
+      if(USE_WAITREQUEST) begin
+         uav_waitrequest = av_waitrequest;
+      end else begin
+         uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
+      end
+
+   end
+
+   // --------------
+   // Readdata Assignment
+   // --------------
+
+   reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
+
+   always@(posedge clk, posedge reset) begin
+      if(reset)
+         av_readdata_pre <= 'b0;
+      else
+         av_readdata_pre <= av_readdata;
+   end
+
+   always@* begin
+      uav_readdata = {UAV_DATA_W{1'b0}};
+      if( AV_READLATENCY != 0  || USE_READDATAVALID ) begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata;
+      end else begin
+         uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
+      end
+   end
+   
+   // -------------------
+   // Readdatavalid Assigment
+   // -------------------
+   reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
+   reg top_read_latency_shift_reg;
+
+   always@* begin
+      uav_readdatavalid=top_read_latency_shift_reg;
+      if(USE_READDATAVALID) begin
+         uav_readdatavalid = av_readdatavalid;
+      end
+   end
+
+   always@* begin
+      top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
+      if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
+         top_read_latency_shift_reg=read_latency_shift_reg;
+      end
+      if (AV_READLATENCY > 1) begin
+         top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
+      end
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if (reset) begin
+         read_latency_shift_reg <= '0;
+      end else if (av_clken) begin
+         read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
+         for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
+            read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
+         end
+      end
+   end
+
+   // ------------
+   // Chipselect and OutputEnable
+   // ------------
+   reg av_chipselect_pre;
+   wire cs_extension;
+   reg av_outputenable_pre;
+   
+   assign av_chipselect  = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
+   assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
+   assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
+
+   always@(posedge reset, posedge clk) begin
+      if(reset)
+         av_outputenable_pre <= 1'b0;
+      else if( AV_READLATENCY == 0  && AV_READ_WAIT_INDEXED != 0 )
+         av_outputenable_pre <= 0;
+      else
+         av_outputenable_pre <= cs_extension | uav_read;
+   end
+
+   always@(posedge reset, posedge clk) begin
+      if(reset) begin
+         av_chipselect_pre  <= 1'b0;
+      end else begin
+         av_chipselect_pre  <= 1'b0;
+         if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
+            //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
+            //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
+            if(uav_read) begin
+               av_chipselect_pre <= 1'b1;
+            end else if(cs_extension == 1) begin
+               av_chipselect_pre <= 1'b1;
+            end
+         end
+      end
+   end
+
+   // -------------------
+   // Begintransfer Assigment
+   // -------------------
+   reg end_begintransfer;
+
+   always@* begin
+      av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_begintransfer <= 1'b0;
+      end else begin
+         if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
+            end_begintransfer <= 1'b1;
+         else if(uav_waitrequest)
+            end_begintransfer <= end_begintransfer;
+         else
+            end_begintransfer <= 1'b0;
+      end
+   end
+
+   // -------------------
+   // Beginbursttransfer Assigment
+   // -------------------
+   reg end_beginbursttransfer;
+   reg in_transfer;
+
+   always@* begin
+      av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
+   end
+
+   always@ ( posedge clk or posedge reset ) begin
+      if(reset) begin
+         end_beginbursttransfer <= 1'b0;
+         in_transfer <= 1'b0;
+      end else begin
+         end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
+         if(uav_write && uav_burstcount == symbols_per_word)
+            in_transfer <=1'b0;
+         else if(uav_write)
+            in_transfer <=1'b1;
+      end
+   end
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash.v
new file mode 100644
index 0000000..659d825
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash.v
@@ -0,0 +1,324 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//   ALTERA_ONCHIP_FLASH
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module  altera_onchip_flash ( 
+	// To/From System
+	clock,
+	reset_n,
+	
+	// To/From Avalon_MM data slave interface
+	avmm_data_read,
+	avmm_data_write,
+	avmm_data_addr,
+	avmm_data_writedata,
+	avmm_data_burstcount,
+	avmm_data_waitrequest,
+	avmm_data_readdatavalid,
+	avmm_data_readdata,
+	
+	// To/From Avalon_MM csr slave interface
+	avmm_csr_read,
+	avmm_csr_write,
+	avmm_csr_addr,
+	avmm_csr_writedata,
+	avmm_csr_readdata
+);
+	parameter DEVICE_FAMILY = "MAX 10";
+	parameter PART_NAME = "Unknown";
+	parameter IS_DUAL_BOOT = "False";
+	parameter IS_ERAM_SKIP = "False";
+	parameter IS_COMPRESSED_IMAGE = "False";
+	parameter INIT_FILENAME = "";
+
+	// simulation only start
+	parameter DEVICE_ID = "08";
+	parameter INIT_FILENAME_SIM = "";
+	// simulation only end
+
+	parameter PARALLEL_MODE = 0;
+	parameter READ_AND_WRITE_MODE = 0;
+	parameter WRAPPING_BURST_MODE = 0;
+	
+	parameter AVMM_CSR_DATA_WIDTH = 32;
+	parameter AVMM_DATA_DATA_WIDTH = 32;
+	parameter AVMM_DATA_ADDR_WIDTH = 20;
+	parameter AVMM_DATA_BURSTCOUNT_WIDTH = 13;
+	parameter FLASH_DATA_WIDTH = 32;
+	parameter FLASH_ADDR_WIDTH = 23;
+	parameter FLASH_SEQ_READ_DATA_COUNT = 2;	//number of 32-bit data per sequential read. only need in parallel mode.
+	parameter FLASH_READ_CYCLE_MAX_INDEX = 3;	//period to for each sequential read. only need in parallel mode.
+	parameter FLASH_ADDR_ALIGNMENT_BITS = 1; 	//number of last addr bits for alignment. only need in parallel mode.
+	parameter FLASH_RESET_CYCLE_MAX_INDEX = 28;	//period that required by flash before back to idle for erase and program operation
+	parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (960ns)
+	parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
+	parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
+	parameter MIN_VALID_ADDR = 1;
+	parameter MAX_VALID_ADDR = 1;
+	parameter MIN_UFM_VALID_ADDR = 1;
+	parameter MAX_UFM_VALID_ADDR = 1;
+	parameter SECTOR1_START_ADDR = 1;
+	parameter SECTOR1_END_ADDR = 1;
+	parameter SECTOR2_START_ADDR = 1;
+	parameter SECTOR2_END_ADDR = 1;
+	parameter SECTOR3_START_ADDR = 1;
+	parameter SECTOR3_END_ADDR = 1;
+	parameter SECTOR4_START_ADDR = 1;
+	parameter SECTOR4_END_ADDR = 1;
+	parameter SECTOR5_START_ADDR = 1;
+	parameter SECTOR5_END_ADDR = 1;
+	parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
+	parameter SECTOR1_MAP = 1;
+	parameter SECTOR2_MAP = 1;
+	parameter SECTOR3_MAP = 1;
+	parameter SECTOR4_MAP = 1;
+	parameter SECTOR5_MAP = 1;
+	parameter ADDR_RANGE1_END_ADDR = 1;
+	parameter ADDR_RANGE2_END_ADDR = 1;
+	parameter ADDR_RANGE1_OFFSET = 1;
+	parameter ADDR_RANGE2_OFFSET = 1;
+	parameter ADDR_RANGE3_OFFSET = 1;
+	// To/From System
+	input clock;
+	input reset_n;
+
+	// To/From Avalon_MM data slave interface
+	input avmm_data_read;
+	input avmm_data_write;
+	input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_data_addr;
+	input [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_writedata;
+	input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_data_burstcount;
+	output avmm_data_waitrequest;
+	output avmm_data_readdatavalid;
+	output [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata;
+
+	// To/From Avalon_MM csr slave interface
+	input avmm_csr_read;
+	input avmm_csr_write;
+	input avmm_csr_addr;
+	input [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_writedata;
+	output [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata;
+
+	wire [AVMM_DATA_DATA_WIDTH-1:0] avmm_data_readdata_wire;
+	wire [AVMM_CSR_DATA_WIDTH-1:0] avmm_csr_readdata_wire;
+	wire [31:0] csr_control_wire;
+	wire [9:0] csr_status_wire;
+	wire [FLASH_ADDR_WIDTH-1:0] flash_ardin_wire;
+	wire [FLASH_DATA_WIDTH-1:0] flash_drdout_wire;
+	wire flash_busy;
+	wire flash_se_pass;
+	wire flash_sp_pass;
+	wire flash_osc;
+	wire flash_xe_ye;
+	wire flash_se;
+	wire flash_arclk;
+	wire flash_arshft;
+	wire flash_drclk;
+	wire flash_drshft;
+	wire flash_drdin;
+	wire flash_nprogram;
+	wire flash_nerase;
+	wire flash_par_en;
+	wire flash_xe_ye_wire;
+	wire flash_se_wire;
+	
+	assign avmm_data_readdata = avmm_data_readdata_wire;
+
+	generate
+		if (READ_AND_WRITE_MODE == 0) begin
+			assign avmm_csr_readdata = 32'hffffffff;
+			assign csr_control_wire = 32'h3fffffff;
+		end
+		else begin
+			assign avmm_csr_readdata = avmm_csr_readdata_wire;
+		end
+	endgenerate
+
+	generate
+		if (DEVICE_ID == "02" || DEVICE_ID == "01") begin
+			// Set all to 0 for simulation model
+			assign flash_par_en = 1'b0;
+			assign flash_xe_ye = 1'b0;
+			assign flash_se = 1'b0;
+		end
+		else begin
+			assign flash_par_en = PARALLEL_MODE[0];
+			assign flash_xe_ye = flash_xe_ye_wire;
+			assign flash_se = flash_se_wire;
+		end
+	endgenerate
+	
+	generate
+		if (READ_AND_WRITE_MODE) begin
+			// -------------------------------------------------------------------
+			// Instantiate a Avalon_MM csr slave controller
+			// -------------------------------------------------------------------	
+			altera_onchip_flash_avmm_csr_controller avmm_csr_controller ( 
+				// To/From System
+				.clock(clock),
+				.reset_n(reset_n),
+
+				// To/From Avalon_MM csr slave interface
+				.avmm_read(avmm_csr_read),
+				.avmm_write(avmm_csr_write),
+				.avmm_addr(avmm_csr_addr),
+				.avmm_writedata(avmm_csr_writedata),
+				.avmm_readdata(avmm_csr_readdata_wire),
+		
+				// To/From Avalon_MM data slave interface
+				.csr_control(csr_control_wire),
+				.csr_status(csr_status_wire)
+			);
+		end
+	endgenerate
+
+	// -------------------------------------------------------------------
+	// Instantiate a Avalon_MM data slave controller
+	// -------------------------------------------------------------------	
+	altera_onchip_flash_avmm_data_controller # (
+
+		.READ_AND_WRITE_MODE (READ_AND_WRITE_MODE),
+		.WRAPPING_BURST_MODE (WRAPPING_BURST_MODE),
+		.AVMM_DATA_ADDR_WIDTH (AVMM_DATA_ADDR_WIDTH),
+		.AVMM_DATA_BURSTCOUNT_WIDTH (AVMM_DATA_BURSTCOUNT_WIDTH),
+		.FLASH_SEQ_READ_DATA_COUNT (FLASH_SEQ_READ_DATA_COUNT),
+		.FLASH_READ_CYCLE_MAX_INDEX (FLASH_READ_CYCLE_MAX_INDEX),
+		.FLASH_ADDR_ALIGNMENT_BITS (FLASH_ADDR_ALIGNMENT_BITS),
+		.FLASH_RESET_CYCLE_MAX_INDEX (FLASH_RESET_CYCLE_MAX_INDEX),
+		.FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX (FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX),
+		.FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX),
+		.FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX (FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX),
+		.MIN_VALID_ADDR (MIN_VALID_ADDR),
+		.MAX_VALID_ADDR (MAX_VALID_ADDR),
+		.SECTOR1_START_ADDR (SECTOR1_START_ADDR),
+		.SECTOR1_END_ADDR (SECTOR1_END_ADDR),
+		.SECTOR2_START_ADDR (SECTOR2_START_ADDR),
+		.SECTOR2_END_ADDR (SECTOR2_END_ADDR),
+		.SECTOR3_START_ADDR (SECTOR3_START_ADDR),
+		.SECTOR3_END_ADDR (SECTOR3_END_ADDR),
+		.SECTOR4_START_ADDR (SECTOR4_START_ADDR),
+		.SECTOR4_END_ADDR (SECTOR4_END_ADDR),
+		.SECTOR5_START_ADDR (SECTOR5_START_ADDR),
+		.SECTOR5_END_ADDR (SECTOR5_END_ADDR),
+		.SECTOR_READ_PROTECTION_MODE (SECTOR_READ_PROTECTION_MODE),
+		.SECTOR1_MAP (SECTOR1_MAP),
+		.SECTOR2_MAP (SECTOR2_MAP),
+		.SECTOR3_MAP (SECTOR3_MAP),
+		.SECTOR4_MAP (SECTOR4_MAP),
+		.SECTOR5_MAP (SECTOR5_MAP),
+		.ADDR_RANGE1_END_ADDR (ADDR_RANGE1_END_ADDR),
+		.ADDR_RANGE2_END_ADDR (ADDR_RANGE2_END_ADDR),
+		.ADDR_RANGE1_OFFSET (ADDR_RANGE1_OFFSET),
+		.ADDR_RANGE2_OFFSET (ADDR_RANGE2_OFFSET),
+		.ADDR_RANGE3_OFFSET (ADDR_RANGE3_OFFSET)
+
+	) avmm_data_controller ( 
+		// To/From System
+		.clock(clock),
+		.reset_n(reset_n),
+		
+		// To/From Flash IP interface
+		.flash_busy(flash_busy),
+		.flash_se_pass(flash_se_pass),
+		.flash_sp_pass(flash_sp_pass),
+		.flash_osc(flash_osc),
+		.flash_drdout(flash_drdout_wire),
+		.flash_xe_ye(flash_xe_ye_wire),
+		.flash_se(flash_se_wire),
+		.flash_arclk(flash_arclk),
+		.flash_arshft(flash_arshft),
+		.flash_drclk(flash_drclk),
+		.flash_drshft(flash_drshft),
+		.flash_drdin(flash_drdin),
+		.flash_nprogram(flash_nprogram),
+		.flash_nerase(flash_nerase),
+		.flash_ardin(flash_ardin_wire),
+
+		// To/From Avalon_MM data slave interface
+		.avmm_read(avmm_data_read),
+		.avmm_write(avmm_data_write),
+		.avmm_addr(avmm_data_addr),
+		.avmm_writedata(avmm_data_writedata),
+		.avmm_burstcount(avmm_data_burstcount),
+		.avmm_waitrequest(avmm_data_waitrequest),
+		.avmm_readdatavalid(avmm_data_readdatavalid),
+		.avmm_readdata(avmm_data_readdata_wire),
+
+		// To/From Avalon_MM csr slave interface
+		.csr_control(csr_control_wire),
+		.csr_status(csr_status_wire)
+	);
+	
+	// -------------------------------------------------------------------
+	// Instantiate wysiwyg for onchip flash block
+	// -------------------------------------------------------------------
+	fiftyfivenm_unvm # (
+
+		// simulation only start
+		.device_id (DEVICE_ID),
+		.init_filename_sim (INIT_FILENAME_SIM),
+		.min_ufm_valid_addr (MIN_UFM_VALID_ADDR),
+		.max_ufm_valid_addr (MAX_UFM_VALID_ADDR),
+		.addr_range1_end_addr (ADDR_RANGE1_END_ADDR),
+        .addr_range2_end_addr (ADDR_RANGE2_END_ADDR),
+		.addr_range1_offset (ADDR_RANGE1_OFFSET),
+		.addr_range2_offset (ADDR_RANGE2_OFFSET),
+        .addr_range3_offset (ADDR_RANGE3_OFFSET)
+		// simulation only end
+
+	) altera_onchip_flash_block (
+		.xe_ye(flash_xe_ye),
+		.se(flash_se),
+		.arclk(flash_arclk),
+		.arshft(flash_arshft),
+		.ardin(flash_ardin_wire),
+		.drclk(flash_drclk),
+		.drshft(flash_drshft),
+		.drdin(flash_drdin),
+		.nprogram(flash_nprogram),
+		.nerase(flash_nerase),
+		.nosc_ena(1'b0),
+		.par_en(flash_par_en),
+		.drdout(flash_drdout_wire),
+		.busy(flash_busy),
+		.se_pass(flash_se_pass),
+		.sp_pass(flash_sp_pass),
+		.osc(flash_osc)
+	);
+	
+	
+endmodule //altera_onchip_flash
+//VALID FILE
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_csr_controller.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_csr_controller.v
new file mode 100644
index 0000000..574aded
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_csr_controller.v
@@ -0,0 +1,182 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//  ALTERA_ONCHIP_FLASH_AVMM_CSR_CONTROLLER
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module altera_onchip_flash_avmm_csr_controller (
+	// To/From System
+	clock,
+	reset_n,
+
+	// To/From Avalon_MM csr slave interface
+	avmm_read,
+	avmm_write,
+	avmm_addr,
+	avmm_writedata,
+	avmm_readdata,
+	
+	// To/From Avalon_MM data slave interface
+	csr_status,
+	csr_control
+);
+
+	parameter AVMM_CSR_DATA_WIDTH = 32;
+
+	localparam [1:0]	ERASE_ST_IDLE = 0,
+						ERASE_ST_PENDING = 1,
+						ERASE_ST_BUSY = 2;
+
+	localparam [1:0]	STATUS_IDLE = 0,
+						STATUS_BUSY_ERASE = 1,
+						STATUS_BUSY_WRITE = 2,
+						STATUS_BUSY_READ = 3;
+
+	// To/From System
+	input clock;
+	input reset_n;
+
+	// To/From Avalon_MM csr slave interface
+	input avmm_read;
+	input avmm_write;
+	input avmm_addr;
+	input [AVMM_CSR_DATA_WIDTH-1:0] avmm_writedata;
+	output [AVMM_CSR_DATA_WIDTH-1:0] avmm_readdata;
+	
+	// To/From Avalon_MM data slave interface
+	input [9:0] csr_status;
+	output [31:0] csr_control;
+	
+	reg [22:0] csr_sector_page_erase_addr_reg;
+	reg [4:0] csr_wp_mode;
+	reg [1:0] csr_erase_state;
+	reg csr_control_access;
+	reg reset_n_reg1;
+	reg reset_n_reg2;
+
+	wire reset_n_w;
+	wire is_idle;
+	wire is_erase_busy;
+	wire valid_csr_erase_addr;
+	wire valid_csr_write;
+	wire [31:0] csr_control_signal;
+	wire [22:0] csr_erase_addr;
+
+	assign is_idle = (csr_status[1:0] == STATUS_IDLE);
+	assign is_erase_busy = (csr_status[1:0] == STATUS_BUSY_ERASE);
+	assign csr_erase_addr = avmm_writedata[22:0];
+	assign valid_csr_erase_addr = (csr_erase_addr != {(23){1'b1}});
+	assign valid_csr_write = (avmm_write & avmm_addr);		
+	assign csr_control_signal = { csr_erase_state, {(2){1'b1}}, csr_wp_mode, csr_sector_page_erase_addr_reg };
+	assign csr_control = csr_control_signal;
+	assign avmm_readdata = (csr_control_access) ? csr_control_signal : { {(22){1'b1}}, csr_status[9:0] };
+
+	// avoid async reset removal issue 
+	assign reset_n_w = reset_n_reg2;
+	
+	// Initiate register value for simulation. The initiate value can't be xx
+	initial begin
+		csr_sector_page_erase_addr_reg <= {(23){1'b1}};
+		csr_wp_mode = {(5){1'b1}};
+		csr_erase_state = ERASE_ST_IDLE;
+		csr_control_access = 1'b0;
+		reset_n_reg1 = 1'b0;
+		reset_n_reg2 = 1'b0;
+	end
+
+	// -------------------------------------------------------------------
+	// Avoid async reset removal issue 
+	// -------------------------------------------------------------------
+	always @ (negedge reset_n or posedge clock) begin
+		if (~reset_n) begin
+			{reset_n_reg2, reset_n_reg1} <= 2'b0;
+		end
+		else begin
+			{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
+		end
+	end
+	
+	// -------------------------------------------------------------------
+	// Avalon_MM read/write
+	// -------------------------------------------------------------------		
+	always @ (posedge clock) begin
+		
+		// synchronous reset
+		if (~reset_n_w) begin
+
+			// reset all register
+			csr_sector_page_erase_addr_reg <= {(23){1'b1}};
+			csr_wp_mode <= {(5){1'b1}};
+			csr_erase_state <= ERASE_ST_IDLE;
+			csr_control_access <= 1'b0;
+
+		end
+		else begin
+
+			// store read address
+			if (avmm_read) begin
+				csr_control_access <= avmm_addr;
+			end
+		
+			// write control register
+			if (valid_csr_write) begin
+				csr_wp_mode <= avmm_writedata[27:23];
+				if (is_idle) begin 
+					csr_sector_page_erase_addr_reg <= avmm_writedata[22:0]; 
+				end
+			end
+		
+			// erase control fsm
+			case (csr_erase_state)
+				ERASE_ST_IDLE:
+					if (is_idle && valid_csr_write && valid_csr_erase_addr) begin 
+						csr_erase_state <= ERASE_ST_PENDING;
+					end
+				ERASE_ST_PENDING:
+					if (is_erase_busy) begin 
+						csr_erase_state <= ERASE_ST_BUSY; 
+					end
+				ERASE_ST_BUSY:
+					if (is_idle) begin
+						csr_erase_state <= ERASE_ST_IDLE; 
+					end
+				default: begin
+					csr_erase_state <= ERASE_ST_IDLE;
+				end
+			endcase
+		end
+		
+	end
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_data_controller.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_data_controller.v
new file mode 100644
index 0000000..6bfe641
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_avmm_data_controller.v
@@ -0,0 +1,1271 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//  ALTERA_ONCHIP_FLASH_AVMM_DATA_CONTROLLER (PARALLEL-to-PARALLEL MODE)
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module altera_onchip_flash_avmm_data_controller (
+    // To/From System
+    clock,
+    reset_n,
+    
+    // To/From Flash IP interface
+    flash_busy,
+    flash_se_pass,
+    flash_sp_pass,
+    flash_osc,
+    flash_drdout,
+    flash_xe_ye,
+    flash_se,
+    flash_arclk,
+    flash_arshft,
+    flash_drclk,
+    flash_drshft,
+    flash_drdin,
+    flash_nprogram,
+    flash_nerase,
+    flash_ardin,
+        
+    // To/From Avalon_MM data slave interface
+    avmm_read,
+    avmm_write,
+    avmm_addr,
+    avmm_writedata,
+    avmm_burstcount,
+    avmm_waitrequest,
+    avmm_readdatavalid,
+    avmm_readdata,
+        
+    // To/From Avalon_MM csr slave interface
+    csr_control,
+    csr_status
+);
+
+    parameter READ_AND_WRITE_MODE = 0;
+    parameter WRAPPING_BURST_MODE = 0;
+    parameter DATA_WIDTH = 32;
+    parameter AVMM_DATA_ADDR_WIDTH = 20;
+    parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
+    parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
+    parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
+    parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
+    parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
+    parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
+    parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
+    parameter MIN_VALID_ADDR = 1;
+    parameter MAX_VALID_ADDR = 1;
+    parameter SECTOR1_START_ADDR = 1;
+    parameter SECTOR1_END_ADDR = 1;
+    parameter SECTOR2_START_ADDR = 1;
+    parameter SECTOR2_END_ADDR = 1;
+    parameter SECTOR3_START_ADDR = 1;
+    parameter SECTOR3_END_ADDR = 1;
+    parameter SECTOR4_START_ADDR = 1;
+    parameter SECTOR4_END_ADDR = 1;
+    parameter SECTOR5_START_ADDR = 1;
+    parameter SECTOR5_END_ADDR = 1;
+    parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
+    parameter SECTOR1_MAP = 1;
+    parameter SECTOR2_MAP = 1;
+    parameter SECTOR3_MAP = 1;
+    parameter SECTOR4_MAP = 1;
+    parameter SECTOR5_MAP = 1;
+    parameter ADDR_RANGE1_END_ADDR = 1;
+    parameter ADDR_RANGE2_END_ADDR = 1;
+    parameter ADDR_RANGE1_OFFSET = 1;
+    parameter ADDR_RANGE2_OFFSET = 1;
+    parameter ADDR_RANGE3_OFFSET = 1;
+
+    localparam [1:0]    ERASE_ST_IDLE = 0,
+                        ERASE_ST_PENDING = 1,
+                        ERASE_ST_BUSY = 2;
+
+    localparam [1:0]    STATUS_IDLE = 0,
+                        STATUS_BUSY_ERASE = 1,
+                        STATUS_BUSY_WRITE = 2,
+                        STATUS_BUSY_READ = 3;
+
+    localparam [2:0]    WRITE_STATE_IDLE = 0,
+                        WRITE_STATE_ADDR = 1,
+                        WRITE_STATE_WRITE = 2,
+                        WRITE_STATE_WAIT_BUSY = 3,
+                        WRITE_STATE_WAIT_DONE = 4,
+                        WRITE_STATE_RESET = 5,
+                        WRITE_STATE_ERROR = 6;
+
+    localparam [2:0]    ERASE_STATE_IDLE = 0,
+                        ERASE_STATE_ADDR = 1,
+                        ERASE_STATE_WAIT_BUSY = 2,
+                        ERASE_STATE_WAIT_DONE = 3,
+                        ERASE_STATE_RESET = 4,
+                        ERASE_STATE_ERROR = 5;
+
+    localparam [2:0]    READ_STATE_IDLE = 0,
+                        READ_STATE_ADDR = 1,
+                        READ_STATE_READ = 2,
+                        READ_STATE_SETUP = 2,
+                        READ_STATE_DUMMY = 3,
+                        READ_STATE_READY = 4,
+                        READ_STATE_FINAL = 5,
+                        READ_STATE_CLEAR = 6,
+                        READ_STATE_PULSE_SE = 7;
+
+    localparam [0:0]    READ_SETUP = 0,
+                        READ_RECV_DATA = 1;
+
+    localparam [1:0]    READ_VALID_IDLE = 0,
+                        READ_VALID_READING = 1,
+                        READ_VALID_PRE_READING = 2;
+
+    // To/From System
+    input clock;
+    input reset_n;
+    
+    // To/From Flash IP interface
+    input flash_busy;
+    input flash_se_pass;
+    input flash_sp_pass;
+    input flash_osc;
+    input [DATA_WIDTH-1:0] flash_drdout;
+    output flash_xe_ye;
+    output flash_se;
+    output flash_arclk;
+    output flash_arshft;
+    output flash_drclk;
+    output flash_drshft;
+    output flash_drdin;
+    output flash_nprogram;
+    output flash_nerase;
+    output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
+        
+    // To/From Avalon_MM data slave interface
+    input avmm_read;
+    input avmm_write;
+    input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
+    input [DATA_WIDTH-1:0] avmm_writedata;
+    input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
+    output avmm_waitrequest;
+    output avmm_readdatavalid;
+    output reg [DATA_WIDTH-1:0] avmm_readdata;
+        
+    // To/From Avalon_MM csr slave interface
+    input [31:0] csr_control;
+    output [9:0] csr_status;
+
+    reg reset_n_reg1;
+    reg reset_n_reg2;
+    reg [1:0] csr_status_busy;
+    reg csr_status_e_pass;
+    reg csr_status_w_pass;
+    reg csr_status_r_pass;
+    reg [2:0] erase_state;
+    reg [2:0] write_state;
+    reg [2:0] read_state;
+    reg avmm_read_state;
+    reg [1:0] avmm_read_valid_state;
+    reg avmm_readdatavalid_reg;
+    reg avmm_readdata_ready;
+    reg [2:0] flash_sector_addr;
+    reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
+    reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
+    reg [FLASH_ADDR_WIDTH-1:0] flash_addr_wire_neg_reg;
+    reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
+    reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
+    reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
+    reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
+    reg write_drclk_en;
+    reg read_drclk_en;
+    reg enable_arclk_sync_reg;
+    reg enable_arclk_neg_reg;
+    reg enable_arclk_neg_pos_reg;
+    reg enable_drclk_neg_reg;
+    reg enable_drclk_neg_pos_reg;
+    reg enable_drclk_neg_pos_write_reg;
+    reg flash_drdin_neg_reg;
+    reg [15:0] write_count;
+    reg [25:0] erase_count;
+    reg [2:0] read_ctrl_count;
+    reg [2:0] data_count;
+    reg write_timeout;
+    reg write_wait;
+    reg write_wait_neg;
+    reg erase_timeout;
+    reg read_wait;
+    reg read_wait_neg;
+    reg flash_drshft_reg;
+    reg flash_drshft_neg_reg;
+    reg flash_se_neg_reg;
+    reg flash_se_pass_reg;
+    reg flash_sp_pass_reg;
+    reg flash_busy_reg;
+    reg flash_busy_clear_reg;
+    reg erase_busy_scan;
+    reg write_busy_scan;
+    reg is_sector1_writable_reg;
+    reg is_sector2_writable_reg;
+    reg is_sector3_writable_reg;
+    reg is_sector4_writable_reg;
+    reg is_sector5_writable_reg;
+
+    wire reset_n_w;
+    wire is_addr_within_valid_range;
+    wire is_addr_writable;
+    wire is_sector_writable;
+    wire is_erase_addr_writable;
+    wire [2:0] cur_e_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
+    wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
+    wire [2:0] flash_sector_wire;
+    wire is_valid_write_burst_count;
+    wire is_erase_busy;
+    wire is_write_busy;
+    wire is_read_busy;
+    wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
+    wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
+    wire [19:0] csr_page_erase_addr;
+    wire [2:0] csr_sector_erase_addr;
+    wire valid_csr_sector_erase_addr;
+    wire [1:0] csr_erase_state;
+    wire [4:0] csr_write_protection_mode;
+    wire valid_csr_erase;
+    wire valid_command;
+    wire flash_drdin_w;
+    wire flash_arclk_arshft_en_w;
+    wire flash_se_w;
+    wire is_busy;
+    wire write_wait_w;
+    wire read_wait_w;
+    wire flash_busy_sync;
+    wire flash_busy_clear_sync;
+
+    generate // generate combi based on read and write mode
+        if (READ_AND_WRITE_MODE == 1) begin
+            assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
+            assign is_write_busy = (write_state != WRITE_STATE_IDLE);
+            assign is_read_busy = (read_state != READ_STATE_IDLE);
+            assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
+            assign flash_drdin = flash_drdin_neg_reg;
+            assign write_wait_w = (write_wait || write_wait_neg);
+            assign is_erase_addr_writable =
+                (valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
+            assign csr_write_protection_mode = csr_control[27:23];
+            assign is_valid_write_burst_count = (avmm_burstcount == 1);
+            always @ (negedge clock) begin
+                if (~reset_n_w) begin
+                    flash_addr_wire_neg_reg <= 0;
+                end
+                else if (valid_csr_erase && valid_csr_sector_erase_addr) begin
+                    flash_addr_wire_neg_reg <=  { flash_sector_addr, 1'b0, {(19){1'b1}}};
+                end
+                else begin
+                    flash_addr_wire_neg_reg <= flash_page_addr;
+                end
+            end
+            
+        end
+        else begin
+            assign is_erase_busy = 1'b0;
+            assign is_write_busy = 1'b0;
+            assign is_read_busy = (read_state != READ_STATE_IDLE);
+            assign is_busy = is_read_busy;
+            assign flash_drdin = 1'b1;
+            assign write_wait_w = 1'b0;
+             always @ (negedge clock) begin
+                if (~reset_n_w) begin
+                    flash_addr_wire_neg_reg <= 0;
+                end
+                else begin
+                    flash_addr_wire_neg_reg <= flash_page_addr;
+                end
+            end
+        end
+    endgenerate    
+    
+    assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
+    assign csr_page_erase_addr = csr_control[19:0];
+    assign csr_sector_erase_addr = csr_control[22:20];
+    assign csr_erase_state = csr_control[31:30];
+    assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
+    assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
+    assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1);
+
+    assign cur_read_addr = avmm_addr;
+    assign read_wait_w = (read_wait || read_wait_neg);
+    
+    generate // generate combi based on read burst mode
+        if (WRAPPING_BURST_MODE == 0) begin
+            // incrementing read
+            assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
+            assign cur_e_addr = csr_sector_erase_addr;
+            assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
+            assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
+            assign flash_se_w = (read_state == READ_STATE_SETUP);
+            assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
+            assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
+        end
+        else begin
+            // wrapping read
+            assign cur_e_addr = csr_sector_erase_addr;
+            assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
+            assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
+            assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
+            assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
+        end
+    endgenerate
+    
+    assign flash_arshft = 1'b1;
+    assign flash_drshft = flash_drshft_neg_reg;
+    assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
+    assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
+    assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
+    assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
+    assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
+    assign flash_se = flash_se_neg_reg;
+    assign flash_ardin = flash_addr_wire_neg_reg;
+
+    assign avmm_readdatavalid = avmm_readdatavalid_reg;    
+    always @(posedge clock) begin
+        if (~reset_n_w | ~csr_status_r_pass) begin
+            avmm_readdata <= 32'hffffffff;
+         end
+         else begin
+            avmm_readdata <= flash_drdout;
+         end
+    end
+
+    // avoid async reset removal issue 
+    assign reset_n_w = reset_n_reg2;
+
+    // initial register
+    initial begin
+        csr_status_busy = STATUS_IDLE;
+        csr_status_e_pass = 0;
+        csr_status_w_pass = 0;
+        csr_status_r_pass = 0;
+        avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
+        avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
+        erase_state = ERASE_STATE_IDLE;
+        write_state = WRITE_STATE_IDLE;
+        read_state = READ_STATE_IDLE;
+        avmm_read_state = READ_SETUP;
+        avmm_read_valid_state = READ_VALID_IDLE;
+        avmm_readdatavalid_reg = 0;
+        avmm_readdata_ready = 0;
+        flash_sector_addr = 0;
+        flash_page_addr = 0;
+        flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
+        flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
+        write_drclk_en = 0;
+        read_drclk_en = 0;
+        flash_drshft_reg = 1;
+        flash_drshft_neg_reg = 1;
+        flash_busy_reg = 0;
+        flash_busy_clear_reg = 0;
+        flash_se_neg_reg = 0;
+        flash_se_pass_reg = 0;
+        flash_sp_pass_reg = 0;
+        erase_busy_scan = 0;
+        write_busy_scan = 0;
+        flash_seq_read_ardin = 0;
+        enable_arclk_neg_reg = 0;
+        enable_arclk_neg_pos_reg = 0;
+        enable_drclk_neg_reg = 0;
+        enable_drclk_neg_pos_reg = 0;
+        enable_drclk_neg_pos_write_reg = 0;
+        flash_drdin_neg_reg = 0;
+        write_count = 0;
+        erase_count = 0;
+        read_ctrl_count = 0;        
+        data_count = 0;
+        write_timeout = 0;
+        erase_timeout = 0;
+        write_wait = 0;
+        write_wait_neg = 0;
+        reset_n_reg1 = 0;
+        reset_n_reg2 = 0;
+        read_wait = 0;
+        read_wait_neg = 0;
+        is_sector1_writable_reg = 0;
+        is_sector2_writable_reg = 0;
+        is_sector3_writable_reg = 0;
+        is_sector4_writable_reg = 0;
+        is_sector5_writable_reg = 0;
+    end
+    
+    // -------------------------------------------------------------------
+    // Avoid async reset removal issue 
+    // -------------------------------------------------------------------
+    always @ (negedge reset_n or posedge clock) begin
+        if (~reset_n) begin
+            {reset_n_reg2, reset_n_reg1} <= 2'b0;
+        end
+        else begin
+            {reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
+        end
+    end
+
+    // -------------------------------------------------------------------
+    // Sync combinational output before feeding into flash
+    // -------------------------------------------------------------------
+    always @ (posedge clock) begin
+        if (~reset_n_w) begin
+            enable_arclk_sync_reg <= 0;
+        end
+        else begin
+            enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
+        end
+    end
+    
+    // -------------------------------------------------------------------
+    // Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
+    // -------------------------------------------------------------------
+    always @ (negedge clock) begin
+        if (~reset_n_w) begin
+            enable_arclk_neg_reg <= 0;
+            enable_drclk_neg_reg <= 0;
+            flash_drshft_neg_reg <= 1;
+            flash_se_neg_reg <= 0;
+            write_wait_neg <= 0;
+            read_wait_neg <= 0;
+        end
+        else begin
+            enable_arclk_neg_reg <= enable_arclk_sync_reg;
+            enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
+            flash_drshft_neg_reg <= flash_drshft_reg;
+            flash_se_neg_reg <= flash_se_w;
+            write_wait_neg <= write_wait;
+            read_wait_neg <= read_wait;
+        end
+    end
+
+    // -------------------------------------------------------------------
+    // Get rid of glitch for pos clock
+    // -------------------------------------------------------------------
+    always @ (posedge clock) begin
+        if (~reset_n_w) begin
+            enable_arclk_neg_pos_reg <= 0;
+        end
+        else begin
+            enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
+        end
+    end
+
+    // -------------------------------------------------------------------
+    // Pine line page address path
+    // -------------------------------------------------------------------
+    always @ (posedge clock) begin
+        if (~reset_n_w) begin
+            flash_page_addr <= 0;
+        end
+        else begin
+            flash_page_addr <= flash_page_addr_wire;
+        end
+    end
+
+    generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
+        if (READ_AND_WRITE_MODE == 1) begin
+            // -------------------------------------------------------------------
+            // Pine line sector address path
+            // -------------------------------------------------------------------
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    flash_sector_addr <= 0;
+                end
+                else begin
+                    flash_sector_addr <= flash_sector_wire;
+                end
+            end
+
+            // -------------------------------------------------------------------
+            // Minitor flash pass signal and update CSR busy status
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    flash_se_pass_reg <= 0;
+                    flash_sp_pass_reg <= 0;
+                    csr_status_busy <= STATUS_IDLE;
+                end
+                else begin
+                    flash_se_pass_reg <= flash_se_pass;
+                    flash_sp_pass_reg <= flash_sp_pass;
+                    
+                    if (is_erase_busy) begin
+                        csr_status_busy <= STATUS_BUSY_ERASE;
+                    end
+                    else if (is_write_busy) begin
+                        csr_status_busy <= STATUS_BUSY_WRITE;
+                    end
+                    else if (is_read_busy) begin
+                        csr_status_busy <= STATUS_BUSY_READ;
+                    end
+                    else begin
+                        csr_status_busy <= STATUS_IDLE;
+                    end
+                end
+            end
+
+            // -------------------------------------------------------------------
+            // Monitor and store flash busy signal, it may faster then the clock
+            // -------------------------------------------------------------------
+            wire busy_scan;
+            assign busy_scan = (erase_busy_scan || write_busy_scan);
+            always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
+                if (~reset_n || ~busy_scan) begin
+                    flash_busy_reg <= 0;
+                    flash_busy_clear_reg <= 0;
+                end
+                else if (flash_busy_reg) begin
+                    flash_busy_reg <= flash_busy_reg;
+                    flash_busy_clear_reg <= ~flash_busy;
+                end
+                else begin
+                    flash_busy_reg <= flash_busy;
+                    flash_busy_clear_reg <= 0;
+                end
+            end
+
+            altera_std_synchronizer #(
+                .depth (2)
+            ) stdsync_busy ( 
+                .clk(clock), // clock
+                .din(flash_busy_reg), // busy signal
+                .dout(flash_busy_sync), // busy signal which reg to clock
+                .reset_n(reset_n) // active low reset
+            );
+
+            altera_std_synchronizer #(
+                .depth (2)
+            ) stdsync_busy_clear ( 
+                .clk(clock), // clock
+                .din(flash_busy_clear_reg), // busy signal
+                .dout(flash_busy_clear_sync), // busy signal which reg to clock
+                .reset_n(reset_n) // active low reset
+            );
+            
+            // -------------------------------------------------------------------
+            // Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
+            // -------------------------------------------------------------------
+            always @ (negedge clock) begin
+                if (~reset_n_w) begin
+                    flash_drdin_neg_reg <= 1;
+                end
+                else begin
+                    flash_drdin_neg_reg <= flash_drdin_w;
+                end
+            end
+
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    write_state <= WRITE_STATE_IDLE;
+                    write_wait <= 0;
+                    csr_status_w_pass <= 1'b0;
+                end
+                else begin
+                    case (write_state)
+                        WRITE_STATE_IDLE: begin
+                            // reset all register
+                            write_count <= 0;
+                            write_timeout <= 1'b0;
+                            write_busy_scan <= 1'b0;
+                            enable_drclk_neg_pos_write_reg <= 0;
+                            
+                            // check command
+                            if (avmm_write) begin
+                                if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
+                                    write_state <= WRITE_STATE_ADDR;
+                                    write_wait <= 1;
+                                    csr_status_w_pass <= 1'b0;
+                                end
+                            end
+                        end
+                        
+                        WRITE_STATE_ADDR: begin
+                            if (is_addr_writable && is_valid_write_burst_count) begin
+                                write_count <= DATA_WIDTH[5:0];
+                                write_state <= WRITE_STATE_WRITE;
+                            end
+                            else begin
+                                write_wait <= 0;
+                                write_count <= 2;
+                                write_state <= WRITE_STATE_ERROR;
+                            end
+                        end
+
+                        WRITE_STATE_WRITE: begin
+                            if (write_count != 0) begin
+                                write_drclk_en <= 1;
+                                write_count <= write_count - 16'd1;
+                            end
+                            else begin
+                                enable_drclk_neg_pos_write_reg <= 1;
+                                write_drclk_en <= 0;
+                                write_busy_scan <= 1'b1;
+                                write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
+                                write_state <= WRITE_STATE_WAIT_BUSY;
+                            end
+                        end                
+
+                        WRITE_STATE_WAIT_BUSY: begin
+                            if (flash_busy_sync) begin
+                                write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
+                                write_state <= WRITE_STATE_WAIT_DONE;
+                            end
+                            else begin
+                                if (write_count != 0)
+                                    write_count <= write_count - 16'd1;
+                                else begin
+                                    write_timeout <= 1'b1;
+                                    write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
+                                    write_state <= WRITE_STATE_RESET;
+                                end
+                            end
+                        end
+                        
+                        WRITE_STATE_WAIT_DONE: begin
+                            if (flash_busy_clear_sync) begin
+                                write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
+                                write_state <= WRITE_STATE_RESET;
+                            end
+                            else begin
+                                if (write_count != 0) begin
+                                    write_count <= write_count - 16'd1;
+                                end
+                                else begin
+                                    write_timeout <= 1'b1;
+                                    write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
+                                    write_state <= WRITE_STATE_RESET;
+                                end
+                            end
+                        end
+
+                        WRITE_STATE_RESET: begin
+                            write_busy_scan <= 1'b0;
+                            if (write_timeout) begin
+                                csr_status_w_pass <= 1'b0;
+                            end
+                            else begin
+                                csr_status_w_pass <= flash_sp_pass_reg;
+                            end
+                            if (write_count == 1) begin
+                                write_wait <= 0;
+                            end
+                            if (write_count != 0) begin
+                                write_count <= write_count - 16'd1;
+                            end
+                            else begin
+                                write_state <= WRITE_STATE_IDLE;
+                            end
+                        end
+                        
+                        WRITE_STATE_ERROR: begin
+                            csr_status_w_pass <= 1'b0;
+                            if (write_count == 1) begin
+                                write_wait <= 0;
+                            end
+                            if (write_count != 0) begin
+                                write_count <= write_count - 16'd1;
+                            end
+                            else begin
+                                write_state <= WRITE_STATE_IDLE;
+                            end
+                        end
+                        
+                        default: begin
+                            write_state <= WRITE_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end    
+
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    erase_state <= ERASE_STATE_IDLE;
+                    csr_status_e_pass <= 1'b0;
+                end
+                else begin
+                    case (erase_state)
+
+                        ERASE_STATE_IDLE: begin
+                            // reset all register
+                            erase_count <= 0;
+                            erase_timeout <= 1'b0;
+                            erase_busy_scan <= 1'b0;
+                            
+                            // check command
+                            if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
+                                erase_state <= ERASE_STATE_ADDR;
+                                csr_status_e_pass <= 1'b0;
+                            end
+                        end
+
+                        ERASE_STATE_ADDR: begin
+                            if (is_erase_addr_writable) begin
+                                erase_busy_scan <= 1'b1;
+                                erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
+                                erase_state <= ERASE_STATE_WAIT_BUSY;
+                            end
+                            else begin
+                                erase_count <= 2;
+                                erase_state <= ERASE_STATE_ERROR;
+                            end
+                        end
+                        
+                        ERASE_STATE_WAIT_BUSY: begin
+                            if (flash_busy_sync) begin
+                                erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
+                                erase_state <= ERASE_STATE_WAIT_DONE;
+                            end
+                            else begin
+                                if (erase_count != 0)
+                                    erase_count <= erase_count - 26'd1;
+                                else begin
+                                    erase_timeout <= 1'b1;
+                                    erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
+                                    erase_state <= ERASE_STATE_RESET;
+                                end
+                            end
+                        end
+
+                        ERASE_STATE_WAIT_DONE: begin
+                            if (flash_busy_clear_sync) begin
+                                erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
+                                erase_state <= ERASE_STATE_RESET;
+                            end
+                            else begin
+                                if (erase_count != 0) begin
+                                    erase_count <= erase_count - 26'd1;
+                                end
+                                else begin
+                                    erase_timeout <= 1'b1;
+                                    erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
+                                    erase_state <= ERASE_STATE_RESET;
+                                end
+                            end
+                        end
+
+                        ERASE_STATE_RESET: begin
+                            erase_busy_scan <= 1'b0;
+                            if (erase_timeout) begin
+                                csr_status_e_pass <= 1'b0;
+                            end
+                            else begin
+                                csr_status_e_pass <= flash_se_pass_reg;
+                            end
+                            if (erase_count != 0) begin
+                                erase_count <= erase_count - 26'd1;
+                            end
+                            else begin
+                                erase_state <= ERASE_STATE_IDLE;
+                            end
+                        end
+
+                        ERASE_STATE_ERROR: begin
+                            csr_status_e_pass <= 1'b0;
+                            if (erase_count != 0) begin
+                                erase_count <= erase_count - 26'd1;
+                            end
+                            else begin
+                                erase_state <= ERASE_STATE_IDLE;
+                            end
+                        end
+                        
+                        default: begin
+                            erase_state <= ERASE_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end
+        end
+    endgenerate
+    
+    generate // generate always block for read operation based on read burst mode.
+        if (WRAPPING_BURST_MODE == 0) begin
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    read_state <= READ_STATE_IDLE;
+                    read_wait <= 0;
+                    csr_status_r_pass <= 0;
+                end
+                else begin
+                    case (read_state)
+
+                        READ_STATE_IDLE: begin
+                            // reset all register
+                            avmm_read_state <= READ_SETUP;
+                            avmm_readdata_ready <= 0;
+                            flash_ardin_align_reg <= 0;
+                            read_ctrl_count <= 0;
+                            avmm_burstcount_input_reg <= 0;
+                            enable_drclk_neg_pos_reg <= 0;
+                            read_drclk_en <= 0;
+                            flash_drshft_reg <= 1;
+                            
+                            // check command
+                            if (avmm_read) begin
+                                if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
+                                    read_wait <= 1;
+                                    read_state <= READ_STATE_ADDR;
+                                    flash_seq_read_ardin <= avmm_addr;
+                                    avmm_burstcount_input_reg <= avmm_burstcount;
+                                    csr_status_r_pass <= 0;
+                                end
+                            end
+                        end
+
+                        READ_STATE_ADDR: begin
+                            if (is_addr_within_valid_range) begin
+                                csr_status_r_pass <= 1;
+                            end
+                            else begin
+                                csr_status_r_pass <= 0;
+                            end
+                        
+                            read_wait <= 0;
+                            read_state <= READ_STATE_PULSE_SE;
+                        end
+                        READ_STATE_PULSE_SE: begin
+                             read_wait <= 1;
+              		     read_state <= READ_STATE_SETUP;
+                        end
+
+                        // incrementing read
+                        READ_STATE_SETUP: begin
+                            if (next_flash_read_ardin > MAX_VALID_ADDR) begin
+                                flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
+                            end
+                            else begin
+                                flash_seq_read_ardin <= next_flash_read_ardin;
+                            end
+                            flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
+                            if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
+                                read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
+                                read_state <= READ_STATE_DUMMY;
+                            end
+                            else begin
+                                read_state <= READ_STATE_READY;
+                            end
+                        end
+
+                        READ_STATE_DUMMY: begin
+                            if (read_ctrl_count > 1) begin
+                                read_ctrl_count <= read_ctrl_count - 3'd1;
+                            end
+                            else begin
+                                read_state <= READ_STATE_READY;
+                            end
+                        end
+
+                        READ_STATE_READY: begin
+                            if (avmm_read_state == READ_SETUP) begin
+                                avmm_readdata_ready <= 1;
+                            end
+                            read_drclk_en <= 1;
+                            flash_drshft_reg <= 0;
+                            read_state <= READ_STATE_FINAL;
+                        end
+                        
+                        READ_STATE_FINAL: begin
+                            flash_drshft_reg <= 1;
+                            avmm_readdata_ready <= 0;
+                            avmm_read_state <= READ_RECV_DATA;
+
+                            if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
+                                read_state <= READ_STATE_CLEAR;
+                                read_drclk_en <= 0;
+                                enable_drclk_neg_pos_reg <= 1;
+                            end
+                            else begin
+                                read_state <= READ_STATE_PULSE_SE;
+                            end
+                        end
+
+                        // Dummy state to clear arclk glitch
+                        READ_STATE_CLEAR: begin
+                            read_wait <= 0;
+                            read_state <= READ_STATE_IDLE;
+                        end
+
+                        default: begin
+                            read_state <= READ_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end    
+        end
+        else begin
+            // -------------------------------------------------------------------
+            // Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
+            // -------------------------------------------------------------------        
+            
+            reg [2:0] read_count;
+            
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    read_state <= READ_STATE_IDLE;
+                    read_wait <= 0;
+                    read_count <= 3'd0;
+                end
+                else begin
+                    case (read_state)
+
+                        READ_STATE_IDLE: begin
+                            // reset all register
+                            avmm_readdata_ready <= 0;
+                            flash_ardin_align_reg <= 0;
+                            read_ctrl_count <= 0;
+                            enable_drclk_neg_pos_reg <= 0;
+                            flash_drshft_reg <= 1;
+                            read_drclk_en <= 0;
+                            avmm_burstcount_input_reg <= 0;
+                            
+                            // check command
+                            if (avmm_read) begin
+                                if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
+                                    read_wait <= 1;
+                                    read_state <= READ_STATE_ADDR;
+                                    avmm_burstcount_input_reg <= avmm_burstcount;
+                                    
+                                end
+                            end
+                        end
+
+                        READ_STATE_ADDR: begin
+                              read_wait <= 0;
+                            if (is_addr_within_valid_range) begin
+                                csr_status_r_pass <= 1;
+                            end
+                            else begin
+                                csr_status_r_pass <= 0;
+                            end
+                        
+                            read_state <= READ_STATE_PULSE_SE;
+                            read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
+                        end
+                        READ_STATE_PULSE_SE: begin
+                             read_wait <= 1;
+              		     read_state <= READ_STATE_READ;
+                        end
+                        
+                        // wrapping read
+                        READ_STATE_READ: begin
+                            
+                            // read control signal
+                            if (read_ctrl_count > 0) begin
+                                read_ctrl_count <= read_ctrl_count - 3'd1;
+                            end
+                            if (read_ctrl_count == 2) begin
+                                avmm_readdata_ready <= 1;
+                                read_drclk_en <= 1;
+                                flash_drshft_reg <= 0;
+                            end
+                            else begin
+                                flash_drshft_reg <= 1;
+                            end
+                            if (avmm_read && ~read_wait) begin
+                                read_wait <= 1;
+                            end
+                            if (avmm_readdata_ready || read_ctrl_count == 0) begin
+                                avmm_readdata_ready <= 0;
+                                if (avmm_read) begin
+                                    avmm_burstcount_input_reg <= avmm_burstcount;
+                                    read_state <= READ_STATE_ADDR;
+                                end
+                            end
+                            
+                            // read data signal
+                            if (read_count > 0) begin
+                                read_count <= read_count - 3'd1;
+                            end
+                            else begin
+                                if (avmm_readdata_ready) begin
+                                    read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
+                                end
+                            end
+                            
+                            // back to idle if both control and read cycle are finished
+                            if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
+                                read_state <= READ_STATE_IDLE;
+                                read_drclk_en <= 0;
+                                read_wait <= 0;
+                                enable_drclk_neg_pos_reg <= 1;
+                            end
+                            
+                        end
+
+                        default: begin
+                            read_state <= READ_STATE_IDLE;
+                        end
+                        
+                    endcase
+                end
+            end
+        end
+    endgenerate
+
+    generate // generate readdatavalid control signal always block based on read burst mode.
+        if (WRAPPING_BURST_MODE == 0) begin
+            // -------------------------------------------------------------------
+            // Control readdatavalid signal - incrementing read
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    avmm_read_valid_state <= READ_VALID_IDLE;
+                    avmm_burstcount_reg <= 0;
+                    avmm_readdatavalid_reg <= 0;
+                    flash_ardin_align_backup_reg <= 0;
+                    data_count <= 0;
+                end
+                else begin
+                    case (avmm_read_valid_state)
+                        READ_VALID_IDLE: begin
+                            if (avmm_readdata_ready) begin
+                                data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
+                                avmm_read_valid_state <= READ_VALID_PRE_READING;
+                                avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
+                                flash_ardin_align_backup_reg <= flash_ardin_align_reg;
+                            end
+                        end
+                        READ_VALID_PRE_READING: begin
+                            avmm_readdatavalid_reg <= 1;
+                            avmm_read_valid_state <= READ_VALID_READING;
+                        end
+                        READ_VALID_READING: begin
+
+                            if (avmm_burstcount_reg == 0) begin
+                                avmm_read_valid_state <= READ_VALID_IDLE;
+                                avmm_readdatavalid_reg <= 0;
+                            end
+                            else begin
+                                if (data_count > 0) begin
+                                    if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
+                                        avmm_readdatavalid_reg <= 1;
+                                        avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
+                                    end
+                                    else begin
+                                        avmm_readdatavalid_reg <= 0;
+                                    end
+                                    data_count <= data_count - 3'd1;
+                                end
+                                else begin
+                                    flash_ardin_align_backup_reg <= 0;
+                                    data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
+                                    avmm_read_valid_state <= READ_VALID_PRE_READING;
+                                    avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
+                                end
+                            end
+                        end
+                        
+                        default: begin
+                            avmm_read_valid_state <= READ_VALID_IDLE;
+                            avmm_burstcount_reg <= 0;
+                            avmm_readdatavalid_reg <= 0;
+                            flash_ardin_align_backup_reg <= 0;
+                            data_count <= 0;
+                        end
+                    endcase
+                end
+            end
+        end
+        else begin
+            // -------------------------------------------------------------------
+            // Control readdatavalid signal - wrapping read with fixed burst count
+            //     Burst count
+            //         1~2 - ZB8
+            //         1~4 - all other devices
+            // -------------------------------------------------------------------        
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    avmm_read_valid_state <= READ_VALID_IDLE;
+                    avmm_readdatavalid_reg <= 0;
+                end
+                else begin
+                    case (avmm_read_valid_state)
+                        READ_VALID_IDLE: begin
+                            data_count <= 0;
+                            if (avmm_readdata_ready) begin
+                                data_count <= avmm_burstcount_input_reg - 3'd1;
+                                avmm_read_valid_state <= READ_VALID_PRE_READING;
+                            end
+                        end
+                        READ_VALID_PRE_READING: begin
+                            avmm_readdatavalid_reg <= 1;
+                            avmm_read_valid_state <= READ_VALID_READING;
+                        end
+                        
+                        READ_VALID_READING: begin
+                            if (data_count > 0) begin
+                                data_count <= data_count - 3'd1;
+                            end
+                            else begin
+                                if (avmm_readdata_ready) begin
+                                    data_count <= avmm_burstcount_input_reg - 3'd1;
+                                end
+                                else begin
+                                    avmm_read_valid_state <= READ_VALID_IDLE;
+                                    avmm_readdatavalid_reg <= 0;
+                                end
+                            end
+                        end
+                        
+                        default: begin
+                            avmm_read_valid_state <= READ_VALID_IDLE;
+                        end
+                    endcase
+                end
+            end
+        end
+    endgenerate
+
+    generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
+        if (READ_AND_WRITE_MODE == 1) begin
+            // -------------------------------------------------------------------
+            // Instantiate a shift register to send the data to UFM serially (load parallel)
+            // -------------------------------------------------------------------
+            lpm_shiftreg # (
+                .lpm_type ("LPM_SHIFTREG"),
+                .lpm_width (DATA_WIDTH),
+                .lpm_direction ("LEFT")
+            ) ufm_data_shiftreg (
+                .data(avmm_writedata),
+                .clock(clock),
+                .enable(write_state == WRITE_STATE_WRITE),
+                .load(write_count == DATA_WIDTH),
+                .shiftout(flash_drdin_w),
+                .aclr(write_state == WRITE_STATE_IDLE)
+            );
+        end
+    endgenerate
+
+    altera_onchip_flash_address_range_check    # (
+        .MIN_VALID_ADDR(MIN_VALID_ADDR),
+        .MAX_VALID_ADDR(MAX_VALID_ADDR)
+    ) address_range_checker (
+        .address(cur_read_addr),
+        .is_addr_within_valid_range(is_addr_within_valid_range)
+    );
+
+    altera_onchip_flash_convert_address # (
+        .ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
+        .ADDR_RANGE2_END_ADDR(ADDR_RANGE2_END_ADDR),
+        .ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
+        .ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET),
+        .ADDR_RANGE3_OFFSET(ADDR_RANGE3_OFFSET)
+    ) address_convertor (
+        .address(cur_a_addr),
+        .flash_addr(flash_page_addr_wire)
+    );
+
+    generate // sector address convertsion is unnecessary in read only mode
+        if (READ_AND_WRITE_MODE == 1) begin
+        
+            // pipe line addr legality check logic
+            always @ (posedge clock) begin
+                if (~reset_n_w) begin
+                    is_sector1_writable_reg <= 1'b0;
+                    is_sector2_writable_reg <= 1'b0;
+                    is_sector3_writable_reg <= 1'b0;
+                    is_sector4_writable_reg <= 1'b0;
+                    is_sector5_writable_reg <= 1'b0;
+                end
+                else begin
+                    is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
+                    is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
+                    is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
+                    is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
+                    is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
+                end
+            end
+
+            altera_onchip_flash_a_address_write_protection_check # (
+                .SECTOR1_START_ADDR(SECTOR1_START_ADDR),
+                .SECTOR1_END_ADDR(SECTOR1_END_ADDR),
+                .SECTOR2_START_ADDR(SECTOR2_START_ADDR),
+                .SECTOR2_END_ADDR(SECTOR2_END_ADDR),
+                .SECTOR3_START_ADDR(SECTOR3_START_ADDR),
+                .SECTOR3_END_ADDR(SECTOR3_END_ADDR),
+                .SECTOR4_START_ADDR(SECTOR4_START_ADDR),
+                .SECTOR4_END_ADDR(SECTOR4_END_ADDR),
+                .SECTOR5_START_ADDR(SECTOR5_START_ADDR),
+                .SECTOR5_END_ADDR(SECTOR5_END_ADDR)
+            ) access_address_write_protection_checker (
+                .address(cur_a_addr),
+                .is_sector1_writable(is_sector1_writable_reg),
+                .is_sector2_writable(is_sector2_writable_reg),
+                .is_sector3_writable(is_sector3_writable_reg),
+                .is_sector4_writable(is_sector4_writable_reg),
+                .is_sector5_writable(is_sector5_writable_reg),
+                .is_addr_writable(is_addr_writable)
+            );
+        
+            altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
+                .address(cur_e_addr[2:0]),
+                .is_sector1_writable(is_sector1_writable_reg),
+                .is_sector2_writable(is_sector2_writable_reg),
+                .is_sector3_writable(is_sector3_writable_reg),
+                .is_sector4_writable(is_sector4_writable_reg),
+                .is_sector5_writable(is_sector5_writable_reg),
+                .is_addr_writable(is_sector_writable)
+            );
+            
+            altera_onchip_flash_convert_sector # (
+                .SECTOR1_MAP(SECTOR1_MAP),
+                .SECTOR2_MAP(SECTOR2_MAP),
+                .SECTOR3_MAP(SECTOR3_MAP),
+                .SECTOR4_MAP(SECTOR4_MAP),
+                .SECTOR5_MAP(SECTOR5_MAP)
+            ) sector_convertor (
+                .sector(cur_e_addr[2:0]),
+                .flash_sector(flash_sector_wire)
+            );
+        end
+    endgenerate
+
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_util.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_util.v
new file mode 100644
index 0000000..8e73ae0
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_onchip_flash_util.v
@@ -0,0 +1,270 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+////////////////////////////////////////////////////////////////////
+//
+//  ALTERA_ONCHIP_FLASH_UTIL
+//
+//  Copyright (C) 1991-2013 Altera Corporation
+//  Your use of Altera Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Altera Program License 
+//  Subscription Agreement, Altera MegaCore Function License 
+//  Agreement, or other applicable license agreement, including, 
+//  without limitation, that your use is for the sole purpose of 
+//  programming logic devices manufactured by Altera and sold by 
+//  Altera or its authorized distributors.  Please refer to the 
+//  applicable agreement for further details.
+//
+////////////////////////////////////////////////////////////////////
+
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+
+`timescale 1 ps / 1 ps
+
+module altera_onchip_flash_address_range_check (
+    address,
+    is_addr_within_valid_range
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter MIN_VALID_ADDR = 1;
+    parameter MAX_VALID_ADDR = 1;
+
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    output is_addr_within_valid_range;
+    
+    assign is_addr_within_valid_range = (address >= MIN_VALID_ADDR) && (address <= MAX_VALID_ADDR);
+
+endmodule
+
+
+module altera_onchip_flash_address_write_protection_check (
+    use_sector_addr,
+    address,
+    write_protection_mode,
+    is_addr_writable
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter SECTOR1_START_ADDR = 1;
+    parameter SECTOR1_END_ADDR = 1;
+    parameter SECTOR2_START_ADDR = 1;
+    parameter SECTOR2_END_ADDR = 1;
+    parameter SECTOR3_START_ADDR = 1;
+    parameter SECTOR3_END_ADDR = 1;
+    parameter SECTOR4_START_ADDR = 1;
+    parameter SECTOR4_END_ADDR = 1;
+    parameter SECTOR5_START_ADDR = 1;
+    parameter SECTOR5_END_ADDR = 1;
+    parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
+
+    input use_sector_addr;
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    input [4:0] write_protection_mode;
+    output is_addr_writable;
+
+    wire is_sector1_addr;
+    wire is_sector2_addr;
+    wire is_sector3_addr;
+    wire is_sector4_addr;
+    wire is_sector5_addr;    
+    wire is_sector1_writable;
+    wire is_sector2_writable;
+    wire is_sector3_writable;
+    wire is_sector4_writable;
+    wire is_sector5_writable;
+    
+    assign is_sector1_addr = (use_sector_addr) ? (address == 1) : ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
+    assign is_sector2_addr = (use_sector_addr) ? (address == 2) : ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
+    assign is_sector3_addr = (use_sector_addr) ? (address == 3) : ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
+    assign is_sector4_addr = (use_sector_addr) ? (address == 4) : ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
+    assign is_sector5_addr = (use_sector_addr) ? (address == 5) : ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
+    assign is_sector1_writable = ~(write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
+    assign is_sector2_writable = ~(write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
+    assign is_sector3_writable = ~(write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
+    assign is_sector4_writable = ~(write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
+    assign is_sector5_writable = ~(write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
+    assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
+                               (is_sector2_writable && is_sector2_addr) ||
+                               (is_sector3_writable && is_sector3_addr) ||
+                               (is_sector4_writable && is_sector4_addr) ||
+                               (is_sector5_writable && is_sector5_addr));
+
+endmodule
+
+module altera_onchip_flash_s_address_write_protection_check (
+    address,
+    is_sector1_writable,
+    is_sector2_writable,
+    is_sector3_writable,
+    is_sector4_writable,
+    is_sector5_writable,
+    is_addr_writable
+);
+
+    input [2:0] address;
+    input is_sector1_writable;
+    input is_sector2_writable;
+    input is_sector3_writable;
+    input is_sector4_writable;
+    input is_sector5_writable;
+    output is_addr_writable;
+
+    wire is_sector1_addr;
+    wire is_sector2_addr;
+    wire is_sector3_addr;
+    wire is_sector4_addr;
+    wire is_sector5_addr;
+
+    assign is_sector1_addr = (address == 1);
+    assign is_sector2_addr = (address == 2);
+    assign is_sector3_addr = (address == 3);
+    assign is_sector4_addr = (address == 4);
+    assign is_sector5_addr = (address == 5);
+
+    assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
+                               (is_sector2_writable && is_sector2_addr) ||
+                               (is_sector3_writable && is_sector3_addr) ||
+                               (is_sector4_writable && is_sector4_addr) ||
+                               (is_sector5_writable && is_sector5_addr));
+
+endmodule
+
+module altera_onchip_flash_a_address_write_protection_check (
+    address,
+    is_sector1_writable,
+    is_sector2_writable,
+    is_sector3_writable,
+    is_sector4_writable,
+    is_sector5_writable,
+    is_addr_writable
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter SECTOR1_START_ADDR = 1;
+    parameter SECTOR1_END_ADDR = 1;
+    parameter SECTOR2_START_ADDR = 1;
+    parameter SECTOR2_END_ADDR = 1;
+    parameter SECTOR3_START_ADDR = 1;
+    parameter SECTOR3_END_ADDR = 1;
+    parameter SECTOR4_START_ADDR = 1;
+    parameter SECTOR4_END_ADDR = 1;
+    parameter SECTOR5_START_ADDR = 1;
+    parameter SECTOR5_END_ADDR = 1;
+
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    input is_sector1_writable;
+    input is_sector2_writable;
+    input is_sector3_writable;
+    input is_sector4_writable;
+    input is_sector5_writable;
+    output is_addr_writable;
+
+    wire is_sector1_addr;
+    wire is_sector2_addr;
+    wire is_sector3_addr;
+    wire is_sector4_addr;
+    wire is_sector5_addr;
+
+    assign is_sector1_addr = ((address >= SECTOR1_START_ADDR) && (address <= SECTOR1_END_ADDR));
+    assign is_sector2_addr = ((address >= SECTOR2_START_ADDR) && (address <= SECTOR2_END_ADDR));
+    assign is_sector3_addr = ((address >= SECTOR3_START_ADDR) && (address <= SECTOR3_END_ADDR));
+    assign is_sector4_addr = ((address >= SECTOR4_START_ADDR) && (address <= SECTOR4_END_ADDR));
+    assign is_sector5_addr = ((address >= SECTOR5_START_ADDR) && (address <= SECTOR5_END_ADDR));
+
+    assign is_addr_writable = ((is_sector1_writable && is_sector1_addr) ||
+                               (is_sector2_writable && is_sector2_addr) ||
+                               (is_sector3_writable && is_sector3_addr) ||
+                               (is_sector4_writable && is_sector4_addr) ||
+                               (is_sector5_writable && is_sector5_addr));
+
+endmodule
+
+module altera_onchip_flash_convert_address (
+    address,
+    flash_addr
+);
+
+    parameter FLASH_ADDR_WIDTH = 23;
+    parameter ADDR_RANGE1_END_ADDR = 1;
+    parameter ADDR_RANGE2_END_ADDR = 1;
+    parameter ADDR_RANGE1_OFFSET = 1;
+    parameter ADDR_RANGE2_OFFSET = 1;
+    parameter ADDR_RANGE3_OFFSET = 1;
+
+    input [FLASH_ADDR_WIDTH-1:0] address;
+    output [FLASH_ADDR_WIDTH-1:0] flash_addr;
+
+    assign flash_addr = (address <= ADDR_RANGE1_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE1_OFFSET[FLASH_ADDR_WIDTH-1:0]) : 
+                        (address <= ADDR_RANGE2_END_ADDR[FLASH_ADDR_WIDTH-1:0]) ? (address + ADDR_RANGE2_OFFSET[FLASH_ADDR_WIDTH-1:0]) :
+                        (address + ADDR_RANGE3_OFFSET[FLASH_ADDR_WIDTH-1:0]);
+    
+endmodule
+
+
+module altera_onchip_flash_convert_sector (
+    sector,
+    flash_sector
+);
+
+    parameter SECTOR1_MAP = 1;
+    parameter SECTOR2_MAP = 1;
+    parameter SECTOR3_MAP = 1;
+    parameter SECTOR4_MAP = 1;
+    parameter SECTOR5_MAP = 1;
+
+    input [2:0] sector;
+    output [2:0] flash_sector;
+
+    assign flash_sector = 
+        (sector == 1) ? SECTOR1_MAP[2:0] :
+        (sector == 2) ? SECTOR2_MAP[2:0] :
+        (sector == 3) ? SECTOR3_MAP[2:0] :
+        (sector == 4) ? SECTOR4_MAP[2:0] :
+        (sector == 5) ? SECTOR5_MAP[2:0] :
+        3'd0; // Set to 0 for invalid sector ID
+
+endmodule
+
+
+module altera_onchip_flash_counter (
+    clock,
+    reset,
+    count
+);
+    input clock;
+    input reset;
+    output [4:0] count;
+    
+    reg [4:0] count_reg;
+    
+    assign count = count_reg;
+
+    initial begin
+        count_reg = 0;
+    end
+    
+    always @ (posedge reset or posedge clock) begin
+        if (reset) begin
+            count_reg <= 0;
+        end
+        else begin
+            count_reg <= count_reg + 5'd1;
+        end
+    end
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.sdc b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.sdc
new file mode 100644
index 0000000..6763133
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.sdc
@@ -0,0 +1,30 @@
+# (C) 2001-2023 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License Subscription 
+# Agreement, Intel FPGA IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Intel and sold by 
+# Intel or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+# +---------------------------------------------------
+# | Cut the async clear paths
+# +---------------------------------------------------
+set aclr_counter 0
+set clrn_counter 0
+set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+set aclr_counter [get_collection_size $aclr_collection]
+set clrn_counter [get_collection_size $clrn_collection]
+
+if {$aclr_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
+}
+
+if {$clrn_counter > 0} {
+    set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
+}
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.v
new file mode 100644
index 0000000..0047212
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_controller.v
@@ -0,0 +1,319 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// --------------------------------------
+// Reset controller
+//
+// Combines all the input resets and synchronizes
+// the result to the clk.
+// ACDS13.1 - Added reset request as part of reset sequencing
+// --------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module altera_reset_controller
+#(
+    parameter NUM_RESET_INPUTS              = 6,
+    parameter USE_RESET_REQUEST_IN0 = 0,
+    parameter USE_RESET_REQUEST_IN1 = 0,
+    parameter USE_RESET_REQUEST_IN2 = 0,
+    parameter USE_RESET_REQUEST_IN3 = 0,
+    parameter USE_RESET_REQUEST_IN4 = 0,
+    parameter USE_RESET_REQUEST_IN5 = 0,
+    parameter USE_RESET_REQUEST_IN6 = 0,
+    parameter USE_RESET_REQUEST_IN7 = 0,
+    parameter USE_RESET_REQUEST_IN8 = 0,
+    parameter USE_RESET_REQUEST_IN9 = 0,
+    parameter USE_RESET_REQUEST_IN10 = 0,
+    parameter USE_RESET_REQUEST_IN11 = 0,
+    parameter USE_RESET_REQUEST_IN12 = 0,
+    parameter USE_RESET_REQUEST_IN13 = 0,
+    parameter USE_RESET_REQUEST_IN14 = 0,
+    parameter USE_RESET_REQUEST_IN15 = 0,
+    parameter OUTPUT_RESET_SYNC_EDGES       = "deassert",
+    parameter SYNC_DEPTH                    = 2,
+    parameter RESET_REQUEST_PRESENT         = 0,
+    parameter RESET_REQ_WAIT_TIME           = 3,
+    parameter MIN_RST_ASSERTION_TIME        = 11,
+    parameter RESET_REQ_EARLY_DSRT_TIME     = 4,
+    parameter ADAPT_RESET_REQUEST          = 0
+)
+(
+    // --------------------------------------
+    // We support up to 16 reset inputs, for now
+    // --------------------------------------
+    input reset_in0,
+    input reset_in1,
+    input reset_in2,
+    input reset_in3,
+    input reset_in4,
+    input reset_in5,
+    input reset_in6,
+    input reset_in7,
+    input reset_in8,
+    input reset_in9,
+    input reset_in10,
+    input reset_in11,
+    input reset_in12,
+    input reset_in13,
+    input reset_in14,
+    input reset_in15,
+    input reset_req_in0,
+    input reset_req_in1,
+    input reset_req_in2,
+    input reset_req_in3,
+    input reset_req_in4,
+    input reset_req_in5,
+    input reset_req_in6,
+    input reset_req_in7,
+    input reset_req_in8,
+    input reset_req_in9,
+    input reset_req_in10,
+    input reset_req_in11,
+    input reset_req_in12,
+    input reset_req_in13,
+    input reset_req_in14,
+    input reset_req_in15,
+
+
+    input  clk,
+    output reg reset_out,
+    output reg reset_req
+);
+
+   // Always use async reset synchronizer if reset_req is used
+   localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
+
+   // --------------------------------------
+   // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
+   // --------------------------------------
+   localparam MIN_METASTABLE = 3;
+   localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
+
+   localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
+
+   localparam ASSERTION_CHAIN_LENGTH =  (MIN_METASTABLE > LARGER) ? 
+                                            MIN_RST_ASSERTION_TIME + 1 :
+                                        (
+                                        (MIN_RST_ASSERTION_TIME > LARGER)? 
+                                            MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
+                                            MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
+                                        );
+
+   localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
+   // --------------------------------------
+
+   wire merged_reset;
+   wire merged_reset_req_in;
+   wire reset_out_pre;
+   wire reset_req_pre;
+
+   // Registers and Interconnect
+   (*preserve*) reg  [RSTREQ_ASRT_SYNC_TAP: 0]  altera_reset_synchronizer_int_chain;
+   reg [ASSERTION_CHAIN_LENGTH-1: 0]            r_sync_rst_chain;
+   reg                                          r_sync_rst;
+   reg                                          r_early_rst;
+
+    // --------------------------------------
+    // "Or" all the input resets together
+    // --------------------------------------
+    assign merged_reset = (  
+                              reset_in0 | 
+                              reset_in1 | 
+                              reset_in2 | 
+                              reset_in3 | 
+                              reset_in4 | 
+                              reset_in5 | 
+                              reset_in6 | 
+                              reset_in7 | 
+                              reset_in8 | 
+                              reset_in9 | 
+                              reset_in10 | 
+                              reset_in11 | 
+                              reset_in12 | 
+                              reset_in13 | 
+                              reset_in14 | 
+                              reset_in15
+                          );
+
+    assign merged_reset_req_in = (
+                              ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0)  |
+                              ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) 
+                            );
+
+
+    // --------------------------------------
+    // And if required, synchronize it to the required clock domain,
+    // with the correct synchronization type
+    // --------------------------------------
+    generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
+
+        assign reset_out_pre = merged_reset;
+        assign reset_req_pre = merged_reset_req_in;
+
+    end else begin
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
+        )
+        alt_rst_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset),
+            .reset_out  (reset_out_pre)
+        );
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_req_sync_uq1
+        (
+            .clk        (clk),
+            .reset_in   (merged_reset_req_in),
+            .reset_out  (reset_req_pre)
+        );
+
+    end
+    endgenerate
+
+    generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
+                  ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
+        always @* begin
+            reset_out = reset_out_pre;
+            reset_req = reset_req_pre;
+        end
+    end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
+
+        wire reset_out_pre2;
+
+        altera_reset_synchronizer
+        #(
+            .DEPTH      (SYNC_DEPTH+1),
+            .ASYNC_RESET(0)
+        )
+        alt_rst_sync_uq2
+        (
+            .clk        (clk),
+            .reset_in   (reset_out_pre),
+            .reset_out  (reset_out_pre2)
+        );
+
+        always @* begin
+            reset_out = reset_out_pre2;
+            reset_req = reset_req_pre;
+        end
+
+    end
+    else begin
+
+    // 3-FF Metastability Synchronizer
+    initial
+    begin
+        altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= 
+            {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; 
+    end
+
+    // Synchronous reset pipe
+    initial
+    begin
+        r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+
+    always @(posedge clk)
+    begin
+        if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
+        begin
+            r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
+    end
+    else
+    begin
+        r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
+    end
+    end
+
+    // Standard synchronous reset output.  From 0-1, the transition lags the early output.  For 1->0, the transition
+    // matches the early input.
+
+    always @(posedge clk)
+    begin
+        case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
+            3'b000:   r_sync_rst <= 1'b0; // Not reset
+            3'b001:   r_sync_rst <= 1'b0;
+            3'b010:   r_sync_rst <= 1'b0;
+            3'b011:   r_sync_rst <= 1'b1;
+            3'b100:   r_sync_rst <= 1'b1; 
+            3'b101:   r_sync_rst <= 1'b1;
+            3'b110:   r_sync_rst <= 1'b1;
+            3'b111:   r_sync_rst <= 1'b1; // In Reset
+            default:  r_sync_rst <= 1'b1;
+        endcase
+
+        case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
+            2'b00:   r_early_rst <= 1'b0; // Not reset
+            2'b01:   r_early_rst <= 1'b1; // Coming out of reset
+            2'b10:   r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
+            2'b11:   r_early_rst <= 1'b1; // Held in reset
+            default: r_early_rst <= 1'b1;
+        endcase
+    end
+
+    always @* begin
+        reset_out = r_sync_rst;
+        reset_req = r_early_rst;
+    end
+
+    end
+    endgenerate
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_synchronizer.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_synchronizer.v
new file mode 100644
index 0000000..c2f45bb
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/altera_reset_synchronizer.v
@@ -0,0 +1,87 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1 ns / 1 ns
+
+module altera_reset_synchronizer
+#(
+    parameter ASYNC_RESET = 1,
+    parameter DEPTH       = 2
+)
+(
+    input   reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
+
+    input   clk,
+    output  reset_out
+);
+
+    // -----------------------------------------------
+    // Synchronizer register chain. We cannot reuse the
+    // standard synchronizer in this implementation 
+    // because our timing constraints are different.
+    //
+    // Instead of cutting the timing path to the d-input 
+    // on the first flop we need to cut the aclr input.
+    // 
+    // We omit the "preserve" attribute on the final
+    // output register, so that the synthesis tool can
+    // duplicate it where needed.
+    // -----------------------------------------------
+    (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
+    reg altera_reset_synchronizer_int_chain_out;
+
+    generate if (ASYNC_RESET) begin
+
+        // -----------------------------------------------
+        // Assert asynchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk or posedge reset_in) begin
+            if (reset_in) begin
+                altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
+                altera_reset_synchronizer_int_chain_out <= 1'b1;
+            end
+            else begin
+                altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+                altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
+                altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+            end
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+     
+    end else begin
+
+        // -----------------------------------------------
+        // Assert synchronously, deassert synchronously.
+        // -----------------------------------------------
+        always @(posedge clk) begin
+            altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
+            altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
+            altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
+        end
+
+        assign reset_out = altera_reset_synchronizer_int_chain_out;
+ 
+    end
+    endgenerate
+
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v
new file mode 100644
index 0000000..b7967b6
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_avalon_bridge.v
@@ -0,0 +1,138 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
+// IN THIS FILE.
+
+/******************************************************************************
+ *                                                                            *
+ * This module connects the an External Bus to Avalon Switch Fabric           *
+ *  It acts as both a master for the avalon swtich fabric                     *
+ *  and a slave to the master peripheral                                      *
+ *                                                                            *
+ ******************************************************************************/
+
+module flash_interface_10M04SCU169C8G_avalon_bridge (
+	// Inputs
+	clk,
+	reset,
+
+	// Inputs from Avalon Switch Fabric
+	avalon_readdata,
+	avalon_waitrequest,
+
+	// Inputs from the master peripheral
+	address,
+	byte_enable,
+	read,
+	write,
+	write_data,
+
+	// Bidirectionals
+
+	// Outputs
+	// Output to Avalon Switch Fabric
+	avalon_address,
+	avalon_byteenable,
+	avalon_read,
+	avalon_write,
+	avalon_writedata,
+
+	// Outputs to master peripheral
+	acknowledge,
+	read_data
+);
+
+
+/*****************************************************************************
+ *                           Parameter Declarations                          *
+ *****************************************************************************/
+
+parameter	AW	= 23;	// Address width
+parameter	DW	= 31;	// Data width
+
+parameter	BW	= 3;	// Byte enable width
+
+/*****************************************************************************
+ *                             Port Declarations                             *
+ *****************************************************************************/
+// Inputs
+input						clk;
+input						reset;
+
+input						avalon_waitrequest;
+input			[DW: 0]	avalon_readdata;
+
+input			[AW: 0]	address;
+input			[BW: 0]	byte_enable;
+input						write;
+input						read;
+input			[DW: 0]	write_data;
+
+// Bidirectionals
+
+// Outputs
+output		[AW: 0]	avalon_address;
+output		[BW: 0]	avalon_byteenable;
+output					avalon_read;
+output					avalon_write;
+output		[DW: 0]	avalon_writedata;
+
+output					acknowledge;
+output		[DW: 0]	read_data;
+
+/*****************************************************************************
+ *                           Constant Declarations                           *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                 Internal Wires and Registers Declarations                 *
+ *****************************************************************************/
+
+// Internal Wires
+
+// Internal Registers
+
+// State Machine Registers
+
+/*****************************************************************************
+ *                         Finite State Machine(s)                           *
+ *****************************************************************************/
+
+
+/*****************************************************************************
+ *                             Sequential Logic                              *
+ *****************************************************************************/
+
+/*****************************************************************************
+ *                            Combinational Logic                            *
+ *****************************************************************************/
+assign read_data 				= avalon_readdata;
+assign avalon_address 		= address;
+assign avalon_byteenable	= byte_enable;
+assign avalon_write 			= write;
+assign avalon_read 			= read;
+assign avalon_writedata 	= write_data;
+assign acknowledge 			= ~avalon_waitrequest & (avalon_read | avalon_write);
+
+/*****************************************************************************
+ *                              Internal Modules                             *
+ *****************************************************************************/
+
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v
new file mode 100644
index 0000000..16de39f
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0.v
@@ -0,0 +1,916 @@
+// flash_interface_10M04SCU169C8G_mm_interconnect_0.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module flash_interface_10M04SCU169C8G_mm_interconnect_0 (
+		input  wire        clk_source_clk_clk,                              //                            clk_source_clk.clk
+		input  wire        avalon_bridge_reset_reset_bridge_in_reset_reset, // avalon_bridge_reset_reset_bridge_in_reset.reset
+		input  wire [23:0] avalon_bridge_avalon_master_address,             //               avalon_bridge_avalon_master.address
+		output wire        avalon_bridge_avalon_master_waitrequest,         //                                          .waitrequest
+		input  wire [3:0]  avalon_bridge_avalon_master_byteenable,          //                                          .byteenable
+		input  wire        avalon_bridge_avalon_master_read,                //                                          .read
+		output wire [31:0] avalon_bridge_avalon_master_readdata,            //                                          .readdata
+		input  wire        avalon_bridge_avalon_master_write,               //                                          .write
+		input  wire [31:0] avalon_bridge_avalon_master_writedata,           //                                          .writedata
+		output wire [0:0]  onchip_flash_csr_address,                        //                          onchip_flash_csr.address
+		output wire        onchip_flash_csr_write,                          //                                          .write
+		output wire        onchip_flash_csr_read,                           //                                          .read
+		input  wire [31:0] onchip_flash_csr_readdata,                       //                                          .readdata
+		output wire [31:0] onchip_flash_csr_writedata,                      //                                          .writedata
+		output wire [15:0] onchip_flash_data_address,                       //                         onchip_flash_data.address
+		output wire        onchip_flash_data_write,                         //                                          .write
+		output wire        onchip_flash_data_read,                          //                                          .read
+		input  wire [31:0] onchip_flash_data_readdata,                      //                                          .readdata
+		output wire [31:0] onchip_flash_data_writedata,                     //                                          .writedata
+		output wire [3:0]  onchip_flash_data_burstcount,                    //                                          .burstcount
+		input  wire        onchip_flash_data_readdatavalid,                 //                                          .readdatavalid
+		input  wire        onchip_flash_data_waitrequest                    //                                          .waitrequest
+	);
+
+	wire         avalon_bridge_avalon_master_translator_avalon_universal_master_0_waitrequest;   // avalon_bridge_avalon_master_agent:av_waitrequest -> avalon_bridge_avalon_master_translator:uav_waitrequest
+	wire  [31:0] avalon_bridge_avalon_master_translator_avalon_universal_master_0_readdata;      // avalon_bridge_avalon_master_agent:av_readdata -> avalon_bridge_avalon_master_translator:uav_readdata
+	wire         avalon_bridge_avalon_master_translator_avalon_universal_master_0_debugaccess;   // avalon_bridge_avalon_master_translator:uav_debugaccess -> avalon_bridge_avalon_master_agent:av_debugaccess
+	wire  [23:0] avalon_bridge_avalon_master_translator_avalon_universal_master_0_address;       // avalon_bridge_avalon_master_translator:uav_address -> avalon_bridge_avalon_master_agent:av_address
+	wire         avalon_bridge_avalon_master_translator_avalon_universal_master_0_read;          // avalon_bridge_avalon_master_translator:uav_read -> avalon_bridge_avalon_master_agent:av_read
+	wire   [3:0] avalon_bridge_avalon_master_translator_avalon_universal_master_0_byteenable;    // avalon_bridge_avalon_master_translator:uav_byteenable -> avalon_bridge_avalon_master_agent:av_byteenable
+	wire         avalon_bridge_avalon_master_translator_avalon_universal_master_0_readdatavalid; // avalon_bridge_avalon_master_agent:av_readdatavalid -> avalon_bridge_avalon_master_translator:uav_readdatavalid
+	wire         avalon_bridge_avalon_master_translator_avalon_universal_master_0_lock;          // avalon_bridge_avalon_master_translator:uav_lock -> avalon_bridge_avalon_master_agent:av_lock
+	wire         avalon_bridge_avalon_master_translator_avalon_universal_master_0_write;         // avalon_bridge_avalon_master_translator:uav_write -> avalon_bridge_avalon_master_agent:av_write
+	wire  [31:0] avalon_bridge_avalon_master_translator_avalon_universal_master_0_writedata;     // avalon_bridge_avalon_master_translator:uav_writedata -> avalon_bridge_avalon_master_agent:av_writedata
+	wire   [2:0] avalon_bridge_avalon_master_translator_avalon_universal_master_0_burstcount;    // avalon_bridge_avalon_master_translator:uav_burstcount -> avalon_bridge_avalon_master_agent:av_burstcount
+	wire         rsp_mux_src_valid;                                                              // rsp_mux:src_valid -> avalon_bridge_avalon_master_agent:rp_valid
+	wire  [96:0] rsp_mux_src_data;                                                               // rsp_mux:src_data -> avalon_bridge_avalon_master_agent:rp_data
+	wire         rsp_mux_src_ready;                                                              // avalon_bridge_avalon_master_agent:rp_ready -> rsp_mux:src_ready
+	wire   [1:0] rsp_mux_src_channel;                                                            // rsp_mux:src_channel -> avalon_bridge_avalon_master_agent:rp_channel
+	wire         rsp_mux_src_startofpacket;                                                      // rsp_mux:src_startofpacket -> avalon_bridge_avalon_master_agent:rp_startofpacket
+	wire         rsp_mux_src_endofpacket;                                                        // rsp_mux:src_endofpacket -> avalon_bridge_avalon_master_agent:rp_endofpacket
+	wire  [31:0] onchip_flash_csr_agent_m0_readdata;                                             // onchip_flash_csr_translator:uav_readdata -> onchip_flash_csr_agent:m0_readdata
+	wire         onchip_flash_csr_agent_m0_waitrequest;                                          // onchip_flash_csr_translator:uav_waitrequest -> onchip_flash_csr_agent:m0_waitrequest
+	wire         onchip_flash_csr_agent_m0_debugaccess;                                          // onchip_flash_csr_agent:m0_debugaccess -> onchip_flash_csr_translator:uav_debugaccess
+	wire  [23:0] onchip_flash_csr_agent_m0_address;                                              // onchip_flash_csr_agent:m0_address -> onchip_flash_csr_translator:uav_address
+	wire   [3:0] onchip_flash_csr_agent_m0_byteenable;                                           // onchip_flash_csr_agent:m0_byteenable -> onchip_flash_csr_translator:uav_byteenable
+	wire         onchip_flash_csr_agent_m0_read;                                                 // onchip_flash_csr_agent:m0_read -> onchip_flash_csr_translator:uav_read
+	wire         onchip_flash_csr_agent_m0_readdatavalid;                                        // onchip_flash_csr_translator:uav_readdatavalid -> onchip_flash_csr_agent:m0_readdatavalid
+	wire         onchip_flash_csr_agent_m0_lock;                                                 // onchip_flash_csr_agent:m0_lock -> onchip_flash_csr_translator:uav_lock
+	wire  [31:0] onchip_flash_csr_agent_m0_writedata;                                            // onchip_flash_csr_agent:m0_writedata -> onchip_flash_csr_translator:uav_writedata
+	wire         onchip_flash_csr_agent_m0_write;                                                // onchip_flash_csr_agent:m0_write -> onchip_flash_csr_translator:uav_write
+	wire   [2:0] onchip_flash_csr_agent_m0_burstcount;                                           // onchip_flash_csr_agent:m0_burstcount -> onchip_flash_csr_translator:uav_burstcount
+	wire         onchip_flash_csr_agent_rf_source_valid;                                         // onchip_flash_csr_agent:rf_source_valid -> onchip_flash_csr_agent_rsp_fifo:in_valid
+	wire  [97:0] onchip_flash_csr_agent_rf_source_data;                                          // onchip_flash_csr_agent:rf_source_data -> onchip_flash_csr_agent_rsp_fifo:in_data
+	wire         onchip_flash_csr_agent_rf_source_ready;                                         // onchip_flash_csr_agent_rsp_fifo:in_ready -> onchip_flash_csr_agent:rf_source_ready
+	wire         onchip_flash_csr_agent_rf_source_startofpacket;                                 // onchip_flash_csr_agent:rf_source_startofpacket -> onchip_flash_csr_agent_rsp_fifo:in_startofpacket
+	wire         onchip_flash_csr_agent_rf_source_endofpacket;                                   // onchip_flash_csr_agent:rf_source_endofpacket -> onchip_flash_csr_agent_rsp_fifo:in_endofpacket
+	wire         onchip_flash_csr_agent_rsp_fifo_out_valid;                                      // onchip_flash_csr_agent_rsp_fifo:out_valid -> onchip_flash_csr_agent:rf_sink_valid
+	wire  [97:0] onchip_flash_csr_agent_rsp_fifo_out_data;                                       // onchip_flash_csr_agent_rsp_fifo:out_data -> onchip_flash_csr_agent:rf_sink_data
+	wire         onchip_flash_csr_agent_rsp_fifo_out_ready;                                      // onchip_flash_csr_agent:rf_sink_ready -> onchip_flash_csr_agent_rsp_fifo:out_ready
+	wire         onchip_flash_csr_agent_rsp_fifo_out_startofpacket;                              // onchip_flash_csr_agent_rsp_fifo:out_startofpacket -> onchip_flash_csr_agent:rf_sink_startofpacket
+	wire         onchip_flash_csr_agent_rsp_fifo_out_endofpacket;                                // onchip_flash_csr_agent_rsp_fifo:out_endofpacket -> onchip_flash_csr_agent:rf_sink_endofpacket
+	wire         cmd_mux_src_valid;                                                              // cmd_mux:src_valid -> onchip_flash_csr_agent:cp_valid
+	wire  [96:0] cmd_mux_src_data;                                                               // cmd_mux:src_data -> onchip_flash_csr_agent:cp_data
+	wire         cmd_mux_src_ready;                                                              // onchip_flash_csr_agent:cp_ready -> cmd_mux:src_ready
+	wire   [1:0] cmd_mux_src_channel;                                                            // cmd_mux:src_channel -> onchip_flash_csr_agent:cp_channel
+	wire         cmd_mux_src_startofpacket;                                                      // cmd_mux:src_startofpacket -> onchip_flash_csr_agent:cp_startofpacket
+	wire         cmd_mux_src_endofpacket;                                                        // cmd_mux:src_endofpacket -> onchip_flash_csr_agent:cp_endofpacket
+	wire  [31:0] onchip_flash_data_agent_m0_readdata;                                            // onchip_flash_data_translator:uav_readdata -> onchip_flash_data_agent:m0_readdata
+	wire         onchip_flash_data_agent_m0_waitrequest;                                         // onchip_flash_data_translator:uav_waitrequest -> onchip_flash_data_agent:m0_waitrequest
+	wire         onchip_flash_data_agent_m0_debugaccess;                                         // onchip_flash_data_agent:m0_debugaccess -> onchip_flash_data_translator:uav_debugaccess
+	wire  [23:0] onchip_flash_data_agent_m0_address;                                             // onchip_flash_data_agent:m0_address -> onchip_flash_data_translator:uav_address
+	wire   [3:0] onchip_flash_data_agent_m0_byteenable;                                          // onchip_flash_data_agent:m0_byteenable -> onchip_flash_data_translator:uav_byteenable
+	wire         onchip_flash_data_agent_m0_read;                                                // onchip_flash_data_agent:m0_read -> onchip_flash_data_translator:uav_read
+	wire         onchip_flash_data_agent_m0_readdatavalid;                                       // onchip_flash_data_translator:uav_readdatavalid -> onchip_flash_data_agent:m0_readdatavalid
+	wire         onchip_flash_data_agent_m0_lock;                                                // onchip_flash_data_agent:m0_lock -> onchip_flash_data_translator:uav_lock
+	wire  [31:0] onchip_flash_data_agent_m0_writedata;                                           // onchip_flash_data_agent:m0_writedata -> onchip_flash_data_translator:uav_writedata
+	wire         onchip_flash_data_agent_m0_write;                                               // onchip_flash_data_agent:m0_write -> onchip_flash_data_translator:uav_write
+	wire   [5:0] onchip_flash_data_agent_m0_burstcount;                                          // onchip_flash_data_agent:m0_burstcount -> onchip_flash_data_translator:uav_burstcount
+	wire         onchip_flash_data_agent_rf_source_valid;                                        // onchip_flash_data_agent:rf_source_valid -> onchip_flash_data_agent_rsp_fifo:in_valid
+	wire  [97:0] onchip_flash_data_agent_rf_source_data;                                         // onchip_flash_data_agent:rf_source_data -> onchip_flash_data_agent_rsp_fifo:in_data
+	wire         onchip_flash_data_agent_rf_source_ready;                                        // onchip_flash_data_agent_rsp_fifo:in_ready -> onchip_flash_data_agent:rf_source_ready
+	wire         onchip_flash_data_agent_rf_source_startofpacket;                                // onchip_flash_data_agent:rf_source_startofpacket -> onchip_flash_data_agent_rsp_fifo:in_startofpacket
+	wire         onchip_flash_data_agent_rf_source_endofpacket;                                  // onchip_flash_data_agent:rf_source_endofpacket -> onchip_flash_data_agent_rsp_fifo:in_endofpacket
+	wire         onchip_flash_data_agent_rsp_fifo_out_valid;                                     // onchip_flash_data_agent_rsp_fifo:out_valid -> onchip_flash_data_agent:rf_sink_valid
+	wire  [97:0] onchip_flash_data_agent_rsp_fifo_out_data;                                      // onchip_flash_data_agent_rsp_fifo:out_data -> onchip_flash_data_agent:rf_sink_data
+	wire         onchip_flash_data_agent_rsp_fifo_out_ready;                                     // onchip_flash_data_agent:rf_sink_ready -> onchip_flash_data_agent_rsp_fifo:out_ready
+	wire         onchip_flash_data_agent_rsp_fifo_out_startofpacket;                             // onchip_flash_data_agent_rsp_fifo:out_startofpacket -> onchip_flash_data_agent:rf_sink_startofpacket
+	wire         onchip_flash_data_agent_rsp_fifo_out_endofpacket;                               // onchip_flash_data_agent_rsp_fifo:out_endofpacket -> onchip_flash_data_agent:rf_sink_endofpacket
+	wire         cmd_mux_001_src_valid;                                                          // cmd_mux_001:src_valid -> onchip_flash_data_agent:cp_valid
+	wire  [96:0] cmd_mux_001_src_data;                                                           // cmd_mux_001:src_data -> onchip_flash_data_agent:cp_data
+	wire         cmd_mux_001_src_ready;                                                          // onchip_flash_data_agent:cp_ready -> cmd_mux_001:src_ready
+	wire   [1:0] cmd_mux_001_src_channel;                                                        // cmd_mux_001:src_channel -> onchip_flash_data_agent:cp_channel
+	wire         cmd_mux_001_src_startofpacket;                                                  // cmd_mux_001:src_startofpacket -> onchip_flash_data_agent:cp_startofpacket
+	wire         cmd_mux_001_src_endofpacket;                                                    // cmd_mux_001:src_endofpacket -> onchip_flash_data_agent:cp_endofpacket
+	wire         avalon_bridge_avalon_master_agent_cp_valid;                                     // avalon_bridge_avalon_master_agent:cp_valid -> router:sink_valid
+	wire  [96:0] avalon_bridge_avalon_master_agent_cp_data;                                      // avalon_bridge_avalon_master_agent:cp_data -> router:sink_data
+	wire         avalon_bridge_avalon_master_agent_cp_ready;                                     // router:sink_ready -> avalon_bridge_avalon_master_agent:cp_ready
+	wire         avalon_bridge_avalon_master_agent_cp_startofpacket;                             // avalon_bridge_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
+	wire         avalon_bridge_avalon_master_agent_cp_endofpacket;                               // avalon_bridge_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
+	wire         router_src_valid;                                                               // router:src_valid -> cmd_demux:sink_valid
+	wire  [96:0] router_src_data;                                                                // router:src_data -> cmd_demux:sink_data
+	wire         router_src_ready;                                                               // cmd_demux:sink_ready -> router:src_ready
+	wire   [1:0] router_src_channel;                                                             // router:src_channel -> cmd_demux:sink_channel
+	wire         router_src_startofpacket;                                                       // router:src_startofpacket -> cmd_demux:sink_startofpacket
+	wire         router_src_endofpacket;                                                         // router:src_endofpacket -> cmd_demux:sink_endofpacket
+	wire         onchip_flash_csr_agent_rp_valid;                                                // onchip_flash_csr_agent:rp_valid -> router_001:sink_valid
+	wire  [96:0] onchip_flash_csr_agent_rp_data;                                                 // onchip_flash_csr_agent:rp_data -> router_001:sink_data
+	wire         onchip_flash_csr_agent_rp_ready;                                                // router_001:sink_ready -> onchip_flash_csr_agent:rp_ready
+	wire         onchip_flash_csr_agent_rp_startofpacket;                                        // onchip_flash_csr_agent:rp_startofpacket -> router_001:sink_startofpacket
+	wire         onchip_flash_csr_agent_rp_endofpacket;                                          // onchip_flash_csr_agent:rp_endofpacket -> router_001:sink_endofpacket
+	wire         router_001_src_valid;                                                           // router_001:src_valid -> rsp_demux:sink_valid
+	wire  [96:0] router_001_src_data;                                                            // router_001:src_data -> rsp_demux:sink_data
+	wire         router_001_src_ready;                                                           // rsp_demux:sink_ready -> router_001:src_ready
+	wire   [1:0] router_001_src_channel;                                                         // router_001:src_channel -> rsp_demux:sink_channel
+	wire         router_001_src_startofpacket;                                                   // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
+	wire         router_001_src_endofpacket;                                                     // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
+	wire         onchip_flash_data_agent_rp_valid;                                               // onchip_flash_data_agent:rp_valid -> router_002:sink_valid
+	wire  [96:0] onchip_flash_data_agent_rp_data;                                                // onchip_flash_data_agent:rp_data -> router_002:sink_data
+	wire         onchip_flash_data_agent_rp_ready;                                               // router_002:sink_ready -> onchip_flash_data_agent:rp_ready
+	wire         onchip_flash_data_agent_rp_startofpacket;                                       // onchip_flash_data_agent:rp_startofpacket -> router_002:sink_startofpacket
+	wire         onchip_flash_data_agent_rp_endofpacket;                                         // onchip_flash_data_agent:rp_endofpacket -> router_002:sink_endofpacket
+	wire         router_002_src_valid;                                                           // router_002:src_valid -> rsp_demux_001:sink_valid
+	wire  [96:0] router_002_src_data;                                                            // router_002:src_data -> rsp_demux_001:sink_data
+	wire         router_002_src_ready;                                                           // rsp_demux_001:sink_ready -> router_002:src_ready
+	wire   [1:0] router_002_src_channel;                                                         // router_002:src_channel -> rsp_demux_001:sink_channel
+	wire         router_002_src_startofpacket;                                                   // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
+	wire         router_002_src_endofpacket;                                                     // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
+	wire         cmd_demux_src0_valid;                                                           // cmd_demux:src0_valid -> cmd_mux:sink0_valid
+	wire  [96:0] cmd_demux_src0_data;                                                            // cmd_demux:src0_data -> cmd_mux:sink0_data
+	wire         cmd_demux_src0_ready;                                                           // cmd_mux:sink0_ready -> cmd_demux:src0_ready
+	wire   [1:0] cmd_demux_src0_channel;                                                         // cmd_demux:src0_channel -> cmd_mux:sink0_channel
+	wire         cmd_demux_src0_startofpacket;                                                   // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
+	wire         cmd_demux_src0_endofpacket;                                                     // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
+	wire         cmd_demux_src1_valid;                                                           // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
+	wire  [96:0] cmd_demux_src1_data;                                                            // cmd_demux:src1_data -> cmd_mux_001:sink0_data
+	wire         cmd_demux_src1_ready;                                                           // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
+	wire   [1:0] cmd_demux_src1_channel;                                                         // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
+	wire         cmd_demux_src1_startofpacket;                                                   // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
+	wire         cmd_demux_src1_endofpacket;                                                     // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
+	wire         rsp_demux_src0_valid;                                                           // rsp_demux:src0_valid -> rsp_mux:sink0_valid
+	wire  [96:0] rsp_demux_src0_data;                                                            // rsp_demux:src0_data -> rsp_mux:sink0_data
+	wire         rsp_demux_src0_ready;                                                           // rsp_mux:sink0_ready -> rsp_demux:src0_ready
+	wire   [1:0] rsp_demux_src0_channel;                                                         // rsp_demux:src0_channel -> rsp_mux:sink0_channel
+	wire         rsp_demux_src0_startofpacket;                                                   // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
+	wire         rsp_demux_src0_endofpacket;                                                     // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
+	wire         rsp_demux_001_src0_valid;                                                       // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
+	wire  [96:0] rsp_demux_001_src0_data;                                                        // rsp_demux_001:src0_data -> rsp_mux:sink1_data
+	wire         rsp_demux_001_src0_ready;                                                       // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
+	wire   [1:0] rsp_demux_001_src0_channel;                                                     // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
+	wire         rsp_demux_001_src0_startofpacket;                                               // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
+	wire         rsp_demux_001_src0_endofpacket;                                                 // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
+	wire         onchip_flash_csr_agent_rdata_fifo_src_valid;                                    // onchip_flash_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
+	wire  [33:0] onchip_flash_csr_agent_rdata_fifo_src_data;                                     // onchip_flash_csr_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
+	wire         onchip_flash_csr_agent_rdata_fifo_src_ready;                                    // avalon_st_adapter:in_0_ready -> onchip_flash_csr_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_out_0_valid;                                                  // avalon_st_adapter:out_0_valid -> onchip_flash_csr_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_out_0_data;                                                   // avalon_st_adapter:out_0_data -> onchip_flash_csr_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_out_0_ready;                                                  // onchip_flash_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+	wire   [0:0] avalon_st_adapter_out_0_error;                                                  // avalon_st_adapter:out_0_error -> onchip_flash_csr_agent:rdata_fifo_sink_error
+	wire         onchip_flash_data_agent_rdata_fifo_src_valid;                                   // onchip_flash_data_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
+	wire  [33:0] onchip_flash_data_agent_rdata_fifo_src_data;                                    // onchip_flash_data_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
+	wire         onchip_flash_data_agent_rdata_fifo_src_ready;                                   // avalon_st_adapter_001:in_0_ready -> onchip_flash_data_agent:rdata_fifo_src_ready
+	wire         avalon_st_adapter_001_out_0_valid;                                              // avalon_st_adapter_001:out_0_valid -> onchip_flash_data_agent:rdata_fifo_sink_valid
+	wire  [33:0] avalon_st_adapter_001_out_0_data;                                               // avalon_st_adapter_001:out_0_data -> onchip_flash_data_agent:rdata_fifo_sink_data
+	wire         avalon_st_adapter_001_out_0_ready;                                              // onchip_flash_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
+	wire   [0:0] avalon_st_adapter_001_out_0_error;                                              // avalon_st_adapter_001:out_0_error -> onchip_flash_data_agent:rdata_fifo_sink_error
+
+	altera_merlin_master_translator #(
+		.AV_ADDRESS_W                (24),
+		.AV_DATA_W                   (32),
+		.AV_BURSTCOUNT_W             (1),
+		.AV_BYTEENABLE_W             (4),
+		.UAV_ADDRESS_W               (24),
+		.UAV_BURSTCOUNT_W            (3),
+		.USE_READ                    (1),
+		.USE_WRITE                   (1),
+		.USE_BEGINBURSTTRANSFER      (0),
+		.USE_BEGINTRANSFER           (0),
+		.USE_CHIPSELECT              (0),
+		.USE_BURSTCOUNT              (0),
+		.USE_READDATAVALID           (0),
+		.USE_WAITREQUEST             (1),
+		.USE_READRESPONSE            (0),
+		.USE_WRITERESPONSE           (0),
+		.AV_SYMBOLS_PER_WORD         (4),
+		.AV_ADDRESS_SYMBOLS          (1),
+		.AV_BURSTCOUNT_SYMBOLS       (0),
+		.AV_CONSTANT_BURST_BEHAVIOR  (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR (0),
+		.AV_LINEWRAPBURSTS           (0),
+		.AV_REGISTERINCOMINGSIGNALS  (0)
+	) avalon_bridge_avalon_master_translator (
+		.clk                    (clk_source_clk_clk),                                                             //                       clk.clk
+		.reset                  (avalon_bridge_reset_reset_bridge_in_reset_reset),                                //                     reset.reset
+		.uav_address            (avalon_bridge_avalon_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
+		.uav_burstcount         (avalon_bridge_avalon_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
+		.uav_read               (avalon_bridge_avalon_master_translator_avalon_universal_master_0_read),          //                          .read
+		.uav_write              (avalon_bridge_avalon_master_translator_avalon_universal_master_0_write),         //                          .write
+		.uav_waitrequest        (avalon_bridge_avalon_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
+		.uav_readdatavalid      (avalon_bridge_avalon_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
+		.uav_byteenable         (avalon_bridge_avalon_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
+		.uav_readdata           (avalon_bridge_avalon_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
+		.uav_writedata          (avalon_bridge_avalon_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
+		.uav_lock               (avalon_bridge_avalon_master_translator_avalon_universal_master_0_lock),          //                          .lock
+		.uav_debugaccess        (avalon_bridge_avalon_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
+		.av_address             (avalon_bridge_avalon_master_address),                                            //      avalon_anti_master_0.address
+		.av_waitrequest         (avalon_bridge_avalon_master_waitrequest),                                        //                          .waitrequest
+		.av_byteenable          (avalon_bridge_avalon_master_byteenable),                                         //                          .byteenable
+		.av_read                (avalon_bridge_avalon_master_read),                                               //                          .read
+		.av_readdata            (avalon_bridge_avalon_master_readdata),                                           //                          .readdata
+		.av_write               (avalon_bridge_avalon_master_write),                                              //                          .write
+		.av_writedata           (avalon_bridge_avalon_master_writedata),                                          //                          .writedata
+		.av_burstcount          (1'b1),                                                                           //               (terminated)
+		.av_beginbursttransfer  (1'b0),                                                                           //               (terminated)
+		.av_begintransfer       (1'b0),                                                                           //               (terminated)
+		.av_chipselect          (1'b0),                                                                           //               (terminated)
+		.av_readdatavalid       (),                                                                               //               (terminated)
+		.av_lock                (1'b0),                                                                           //               (terminated)
+		.av_debugaccess         (1'b0),                                                                           //               (terminated)
+		.uav_clken              (),                                                                               //               (terminated)
+		.av_clken               (1'b1),                                                                           //               (terminated)
+		.uav_response           (2'b00),                                                                          //               (terminated)
+		.av_response            (),                                                                               //               (terminated)
+		.uav_writeresponsevalid (1'b0),                                                                           //               (terminated)
+		.av_writeresponsevalid  ()                                                                                //               (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (1),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (1),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (24),
+		.UAV_BURSTCOUNT_W               (3),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (0),
+		.USE_WAITREQUEST                (0),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (1),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) onchip_flash_csr_translator (
+		.clk                    (clk_source_clk_clk),                              //                      clk.clk
+		.reset                  (avalon_bridge_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (onchip_flash_csr_agent_m0_address),               // avalon_universal_slave_0.address
+		.uav_burstcount         (onchip_flash_csr_agent_m0_burstcount),            //                         .burstcount
+		.uav_read               (onchip_flash_csr_agent_m0_read),                  //                         .read
+		.uav_write              (onchip_flash_csr_agent_m0_write),                 //                         .write
+		.uav_waitrequest        (onchip_flash_csr_agent_m0_waitrequest),           //                         .waitrequest
+		.uav_readdatavalid      (onchip_flash_csr_agent_m0_readdatavalid),         //                         .readdatavalid
+		.uav_byteenable         (onchip_flash_csr_agent_m0_byteenable),            //                         .byteenable
+		.uav_readdata           (onchip_flash_csr_agent_m0_readdata),              //                         .readdata
+		.uav_writedata          (onchip_flash_csr_agent_m0_writedata),             //                         .writedata
+		.uav_lock               (onchip_flash_csr_agent_m0_lock),                  //                         .lock
+		.uav_debugaccess        (onchip_flash_csr_agent_m0_debugaccess),           //                         .debugaccess
+		.av_address             (onchip_flash_csr_address),                        //      avalon_anti_slave_0.address
+		.av_write               (onchip_flash_csr_write),                          //                         .write
+		.av_read                (onchip_flash_csr_read),                           //                         .read
+		.av_readdata            (onchip_flash_csr_readdata),                       //                         .readdata
+		.av_writedata           (onchip_flash_csr_writedata),                      //                         .writedata
+		.av_begintransfer       (),                                                //              (terminated)
+		.av_beginbursttransfer  (),                                                //              (terminated)
+		.av_burstcount          (),                                                //              (terminated)
+		.av_byteenable          (),                                                //              (terminated)
+		.av_readdatavalid       (1'b0),                                            //              (terminated)
+		.av_waitrequest         (1'b0),                                            //              (terminated)
+		.av_writebyteenable     (),                                                //              (terminated)
+		.av_lock                (),                                                //              (terminated)
+		.av_chipselect          (),                                                //              (terminated)
+		.av_clken               (),                                                //              (terminated)
+		.uav_clken              (1'b0),                                            //              (terminated)
+		.av_debugaccess         (),                                                //              (terminated)
+		.av_outputenable        (),                                                //              (terminated)
+		.uav_response           (),                                                //              (terminated)
+		.av_response            (2'b00),                                           //              (terminated)
+		.uav_writeresponsevalid (),                                                //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
+	);
+
+	altera_merlin_slave_translator #(
+		.AV_ADDRESS_W                   (16),
+		.AV_DATA_W                      (32),
+		.UAV_DATA_W                     (32),
+		.AV_BURSTCOUNT_W                (4),
+		.AV_BYTEENABLE_W                (4),
+		.UAV_BYTEENABLE_W               (4),
+		.UAV_ADDRESS_W                  (24),
+		.UAV_BURSTCOUNT_W               (6),
+		.AV_READLATENCY                 (0),
+		.USE_READDATAVALID              (1),
+		.USE_WAITREQUEST                (1),
+		.USE_UAV_CLKEN                  (0),
+		.USE_READRESPONSE               (0),
+		.USE_WRITERESPONSE              (0),
+		.AV_SYMBOLS_PER_WORD            (4),
+		.AV_ADDRESS_SYMBOLS             (0),
+		.AV_BURSTCOUNT_SYMBOLS          (0),
+		.AV_CONSTANT_BURST_BEHAVIOR     (0),
+		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
+		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+		.CHIPSELECT_THROUGH_READLATENCY (0),
+		.AV_READ_WAIT_CYCLES            (0),
+		.AV_WRITE_WAIT_CYCLES           (0),
+		.AV_SETUP_WAIT_CYCLES           (0),
+		.AV_DATA_HOLD_CYCLES            (0)
+	) onchip_flash_data_translator (
+		.clk                    (clk_source_clk_clk),                              //                      clk.clk
+		.reset                  (avalon_bridge_reset_reset_bridge_in_reset_reset), //                    reset.reset
+		.uav_address            (onchip_flash_data_agent_m0_address),              // avalon_universal_slave_0.address
+		.uav_burstcount         (onchip_flash_data_agent_m0_burstcount),           //                         .burstcount
+		.uav_read               (onchip_flash_data_agent_m0_read),                 //                         .read
+		.uav_write              (onchip_flash_data_agent_m0_write),                //                         .write
+		.uav_waitrequest        (onchip_flash_data_agent_m0_waitrequest),          //                         .waitrequest
+		.uav_readdatavalid      (onchip_flash_data_agent_m0_readdatavalid),        //                         .readdatavalid
+		.uav_byteenable         (onchip_flash_data_agent_m0_byteenable),           //                         .byteenable
+		.uav_readdata           (onchip_flash_data_agent_m0_readdata),             //                         .readdata
+		.uav_writedata          (onchip_flash_data_agent_m0_writedata),            //                         .writedata
+		.uav_lock               (onchip_flash_data_agent_m0_lock),                 //                         .lock
+		.uav_debugaccess        (onchip_flash_data_agent_m0_debugaccess),          //                         .debugaccess
+		.av_address             (onchip_flash_data_address),                       //      avalon_anti_slave_0.address
+		.av_write               (onchip_flash_data_write),                         //                         .write
+		.av_read                (onchip_flash_data_read),                          //                         .read
+		.av_readdata            (onchip_flash_data_readdata),                      //                         .readdata
+		.av_writedata           (onchip_flash_data_writedata),                     //                         .writedata
+		.av_burstcount          (onchip_flash_data_burstcount),                    //                         .burstcount
+		.av_readdatavalid       (onchip_flash_data_readdatavalid),                 //                         .readdatavalid
+		.av_waitrequest         (onchip_flash_data_waitrequest),                   //                         .waitrequest
+		.av_begintransfer       (),                                                //              (terminated)
+		.av_beginbursttransfer  (),                                                //              (terminated)
+		.av_byteenable          (),                                                //              (terminated)
+		.av_writebyteenable     (),                                                //              (terminated)
+		.av_lock                (),                                                //              (terminated)
+		.av_chipselect          (),                                                //              (terminated)
+		.av_clken               (),                                                //              (terminated)
+		.uav_clken              (1'b0),                                            //              (terminated)
+		.av_debugaccess         (),                                                //              (terminated)
+		.av_outputenable        (),                                                //              (terminated)
+		.uav_response           (),                                                //              (terminated)
+		.av_response            (2'b00),                                           //              (terminated)
+		.uav_writeresponsevalid (),                                                //              (terminated)
+		.av_writeresponsevalid  (1'b0)                                             //              (terminated)
+	);
+
+	altera_merlin_master_agent #(
+		.PKT_ORI_BURST_SIZE_H      (96),
+		.PKT_ORI_BURST_SIZE_L      (94),
+		.PKT_RESPONSE_STATUS_H     (93),
+		.PKT_RESPONSE_STATUS_L     (92),
+		.PKT_QOS_H                 (81),
+		.PKT_QOS_L                 (81),
+		.PKT_DATA_SIDEBAND_H       (79),
+		.PKT_DATA_SIDEBAND_L       (79),
+		.PKT_ADDR_SIDEBAND_H       (78),
+		.PKT_ADDR_SIDEBAND_L       (78),
+		.PKT_BURST_TYPE_H          (77),
+		.PKT_BURST_TYPE_L          (76),
+		.PKT_CACHE_H               (91),
+		.PKT_CACHE_L               (88),
+		.PKT_THREAD_ID_H           (84),
+		.PKT_THREAD_ID_L           (84),
+		.PKT_BURST_SIZE_H          (75),
+		.PKT_BURST_SIZE_L          (73),
+		.PKT_TRANS_EXCLUSIVE       (65),
+		.PKT_TRANS_LOCK            (64),
+		.PKT_BEGIN_BURST           (80),
+		.PKT_PROTECTION_H          (87),
+		.PKT_PROTECTION_L          (85),
+		.PKT_BURSTWRAP_H           (72),
+		.PKT_BURSTWRAP_L           (72),
+		.PKT_BYTE_CNT_H            (71),
+		.PKT_BYTE_CNT_L            (66),
+		.PKT_ADDR_H                (59),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (60),
+		.PKT_TRANS_POSTED          (61),
+		.PKT_TRANS_WRITE           (62),
+		.PKT_TRANS_READ            (63),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (82),
+		.PKT_SRC_ID_L              (82),
+		.PKT_DEST_ID_H             (83),
+		.PKT_DEST_ID_L             (83),
+		.ST_DATA_W                 (97),
+		.ST_CHANNEL_W              (2),
+		.AV_BURSTCOUNT_W           (3),
+		.SUPPRESS_0_BYTEEN_RSP     (0),
+		.ID                        (0),
+		.BURSTWRAP_VALUE           (1),
+		.CACHE_VALUE               (0),
+		.SECURE_ACCESS_BIT         (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0)
+	) avalon_bridge_avalon_master_agent (
+		.clk                   (clk_source_clk_clk),                                                             //       clk.clk
+		.reset                 (avalon_bridge_reset_reset_bridge_in_reset_reset),                                // clk_reset.reset
+		.av_address            (avalon_bridge_avalon_master_translator_avalon_universal_master_0_address),       //        av.address
+		.av_write              (avalon_bridge_avalon_master_translator_avalon_universal_master_0_write),         //          .write
+		.av_read               (avalon_bridge_avalon_master_translator_avalon_universal_master_0_read),          //          .read
+		.av_writedata          (avalon_bridge_avalon_master_translator_avalon_universal_master_0_writedata),     //          .writedata
+		.av_readdata           (avalon_bridge_avalon_master_translator_avalon_universal_master_0_readdata),      //          .readdata
+		.av_waitrequest        (avalon_bridge_avalon_master_translator_avalon_universal_master_0_waitrequest),   //          .waitrequest
+		.av_readdatavalid      (avalon_bridge_avalon_master_translator_avalon_universal_master_0_readdatavalid), //          .readdatavalid
+		.av_byteenable         (avalon_bridge_avalon_master_translator_avalon_universal_master_0_byteenable),    //          .byteenable
+		.av_burstcount         (avalon_bridge_avalon_master_translator_avalon_universal_master_0_burstcount),    //          .burstcount
+		.av_debugaccess        (avalon_bridge_avalon_master_translator_avalon_universal_master_0_debugaccess),   //          .debugaccess
+		.av_lock               (avalon_bridge_avalon_master_translator_avalon_universal_master_0_lock),          //          .lock
+		.cp_valid              (avalon_bridge_avalon_master_agent_cp_valid),                                     //        cp.valid
+		.cp_data               (avalon_bridge_avalon_master_agent_cp_data),                                      //          .data
+		.cp_startofpacket      (avalon_bridge_avalon_master_agent_cp_startofpacket),                             //          .startofpacket
+		.cp_endofpacket        (avalon_bridge_avalon_master_agent_cp_endofpacket),                               //          .endofpacket
+		.cp_ready              (avalon_bridge_avalon_master_agent_cp_ready),                                     //          .ready
+		.rp_valid              (rsp_mux_src_valid),                                                              //        rp.valid
+		.rp_data               (rsp_mux_src_data),                                                               //          .data
+		.rp_channel            (rsp_mux_src_channel),                                                            //          .channel
+		.rp_startofpacket      (rsp_mux_src_startofpacket),                                                      //          .startofpacket
+		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                        //          .endofpacket
+		.rp_ready              (rsp_mux_src_ready),                                                              //          .ready
+		.av_response           (),                                                                               // (terminated)
+		.av_writeresponsevalid ()                                                                                // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (96),
+		.PKT_ORI_BURST_SIZE_L      (94),
+		.PKT_RESPONSE_STATUS_H     (93),
+		.PKT_RESPONSE_STATUS_L     (92),
+		.PKT_BURST_SIZE_H          (75),
+		.PKT_BURST_SIZE_L          (73),
+		.PKT_TRANS_LOCK            (64),
+		.PKT_BEGIN_BURST           (80),
+		.PKT_PROTECTION_H          (87),
+		.PKT_PROTECTION_L          (85),
+		.PKT_BURSTWRAP_H           (72),
+		.PKT_BURSTWRAP_L           (72),
+		.PKT_BYTE_CNT_H            (71),
+		.PKT_BYTE_CNT_L            (66),
+		.PKT_ADDR_H                (59),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (60),
+		.PKT_TRANS_POSTED          (61),
+		.PKT_TRANS_WRITE           (62),
+		.PKT_TRANS_READ            (63),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (82),
+		.PKT_SRC_ID_L              (82),
+		.PKT_DEST_ID_H             (83),
+		.PKT_DEST_ID_L             (83),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (2),
+		.ST_DATA_W                 (97),
+		.AVS_BURSTCOUNT_W          (3),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) onchip_flash_csr_agent (
+		.clk                     (clk_source_clk_clk),                                //             clk.clk
+		.reset                   (avalon_bridge_reset_reset_bridge_in_reset_reset),   //       clk_reset.reset
+		.m0_address              (onchip_flash_csr_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (onchip_flash_csr_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (onchip_flash_csr_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (onchip_flash_csr_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (onchip_flash_csr_agent_m0_lock),                    //                .lock
+		.m0_readdata             (onchip_flash_csr_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (onchip_flash_csr_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (onchip_flash_csr_agent_m0_read),                    //                .read
+		.m0_waitrequest          (onchip_flash_csr_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (onchip_flash_csr_agent_m0_writedata),               //                .writedata
+		.m0_write                (onchip_flash_csr_agent_m0_write),                   //                .write
+		.rp_endofpacket          (onchip_flash_csr_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (onchip_flash_csr_agent_rp_ready),                   //                .ready
+		.rp_valid                (onchip_flash_csr_agent_rp_valid),                   //                .valid
+		.rp_data                 (onchip_flash_csr_agent_rp_data),                    //                .data
+		.rp_startofpacket        (onchip_flash_csr_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_src_ready),                                 //              cp.ready
+		.cp_valid                (cmd_mux_src_valid),                                 //                .valid
+		.cp_data                 (cmd_mux_src_data),                                  //                .data
+		.cp_startofpacket        (cmd_mux_src_startofpacket),                         //                .startofpacket
+		.cp_endofpacket          (cmd_mux_src_endofpacket),                           //                .endofpacket
+		.cp_channel              (cmd_mux_src_channel),                               //                .channel
+		.rf_sink_ready           (onchip_flash_csr_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (onchip_flash_csr_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (onchip_flash_csr_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (onchip_flash_csr_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (onchip_flash_csr_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (onchip_flash_csr_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (onchip_flash_csr_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (onchip_flash_csr_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (onchip_flash_csr_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (onchip_flash_csr_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_out_0_ready),                     // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_out_0_valid),                     //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_out_0_data),                      //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_out_0_error),                     //                .error
+		.rdata_fifo_src_ready    (onchip_flash_csr_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (onchip_flash_csr_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (onchip_flash_csr_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                             //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                               //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (98),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) onchip_flash_csr_agent_rsp_fifo (
+		.clk               (clk_source_clk_clk),                                //       clk.clk
+		.reset             (avalon_bridge_reset_reset_bridge_in_reset_reset),   // clk_reset.reset
+		.in_data           (onchip_flash_csr_agent_rf_source_data),             //        in.data
+		.in_valid          (onchip_flash_csr_agent_rf_source_valid),            //          .valid
+		.in_ready          (onchip_flash_csr_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (onchip_flash_csr_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (onchip_flash_csr_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (onchip_flash_csr_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (onchip_flash_csr_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (onchip_flash_csr_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (onchip_flash_csr_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (onchip_flash_csr_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                             // (terminated)
+		.csr_read          (1'b0),                                              // (terminated)
+		.csr_write         (1'b0),                                              // (terminated)
+		.csr_readdata      (),                                                  // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated)
+		.almost_full_data  (),                                                  // (terminated)
+		.almost_empty_data (),                                                  // (terminated)
+		.in_empty          (1'b0),                                              // (terminated)
+		.out_empty         (),                                                  // (terminated)
+		.in_error          (1'b0),                                              // (terminated)
+		.out_error         (),                                                  // (terminated)
+		.in_channel        (1'b0),                                              // (terminated)
+		.out_channel       ()                                                   // (terminated)
+	);
+
+	altera_merlin_slave_agent #(
+		.PKT_ORI_BURST_SIZE_H      (96),
+		.PKT_ORI_BURST_SIZE_L      (94),
+		.PKT_RESPONSE_STATUS_H     (93),
+		.PKT_RESPONSE_STATUS_L     (92),
+		.PKT_BURST_SIZE_H          (75),
+		.PKT_BURST_SIZE_L          (73),
+		.PKT_TRANS_LOCK            (64),
+		.PKT_BEGIN_BURST           (80),
+		.PKT_PROTECTION_H          (87),
+		.PKT_PROTECTION_L          (85),
+		.PKT_BURSTWRAP_H           (72),
+		.PKT_BURSTWRAP_L           (72),
+		.PKT_BYTE_CNT_H            (71),
+		.PKT_BYTE_CNT_L            (66),
+		.PKT_ADDR_H                (59),
+		.PKT_ADDR_L                (36),
+		.PKT_TRANS_COMPRESSED_READ (60),
+		.PKT_TRANS_POSTED          (61),
+		.PKT_TRANS_WRITE           (62),
+		.PKT_TRANS_READ            (63),
+		.PKT_DATA_H                (31),
+		.PKT_DATA_L                (0),
+		.PKT_BYTEEN_H              (35),
+		.PKT_BYTEEN_L              (32),
+		.PKT_SRC_ID_H              (82),
+		.PKT_SRC_ID_L              (82),
+		.PKT_DEST_ID_H             (83),
+		.PKT_DEST_ID_L             (83),
+		.PKT_SYMBOL_W              (8),
+		.ST_CHANNEL_W              (2),
+		.ST_DATA_W                 (97),
+		.AVS_BURSTCOUNT_W          (6),
+		.SUPPRESS_0_BYTEEN_CMD     (0),
+		.PREVENT_FIFO_OVERFLOW     (1),
+		.USE_READRESPONSE          (0),
+		.USE_WRITERESPONSE         (0),
+		.ECC_ENABLE                (0)
+	) onchip_flash_data_agent (
+		.clk                     (clk_source_clk_clk),                                 //             clk.clk
+		.reset                   (avalon_bridge_reset_reset_bridge_in_reset_reset),    //       clk_reset.reset
+		.m0_address              (onchip_flash_data_agent_m0_address),                 //              m0.address
+		.m0_burstcount           (onchip_flash_data_agent_m0_burstcount),              //                .burstcount
+		.m0_byteenable           (onchip_flash_data_agent_m0_byteenable),              //                .byteenable
+		.m0_debugaccess          (onchip_flash_data_agent_m0_debugaccess),             //                .debugaccess
+		.m0_lock                 (onchip_flash_data_agent_m0_lock),                    //                .lock
+		.m0_readdata             (onchip_flash_data_agent_m0_readdata),                //                .readdata
+		.m0_readdatavalid        (onchip_flash_data_agent_m0_readdatavalid),           //                .readdatavalid
+		.m0_read                 (onchip_flash_data_agent_m0_read),                    //                .read
+		.m0_waitrequest          (onchip_flash_data_agent_m0_waitrequest),             //                .waitrequest
+		.m0_writedata            (onchip_flash_data_agent_m0_writedata),               //                .writedata
+		.m0_write                (onchip_flash_data_agent_m0_write),                   //                .write
+		.rp_endofpacket          (onchip_flash_data_agent_rp_endofpacket),             //              rp.endofpacket
+		.rp_ready                (onchip_flash_data_agent_rp_ready),                   //                .ready
+		.rp_valid                (onchip_flash_data_agent_rp_valid),                   //                .valid
+		.rp_data                 (onchip_flash_data_agent_rp_data),                    //                .data
+		.rp_startofpacket        (onchip_flash_data_agent_rp_startofpacket),           //                .startofpacket
+		.cp_ready                (cmd_mux_001_src_ready),                              //              cp.ready
+		.cp_valid                (cmd_mux_001_src_valid),                              //                .valid
+		.cp_data                 (cmd_mux_001_src_data),                               //                .data
+		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                      //                .startofpacket
+		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                        //                .endofpacket
+		.cp_channel              (cmd_mux_001_src_channel),                            //                .channel
+		.rf_sink_ready           (onchip_flash_data_agent_rsp_fifo_out_ready),         //         rf_sink.ready
+		.rf_sink_valid           (onchip_flash_data_agent_rsp_fifo_out_valid),         //                .valid
+		.rf_sink_startofpacket   (onchip_flash_data_agent_rsp_fifo_out_startofpacket), //                .startofpacket
+		.rf_sink_endofpacket     (onchip_flash_data_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
+		.rf_sink_data            (onchip_flash_data_agent_rsp_fifo_out_data),          //                .data
+		.rf_source_ready         (onchip_flash_data_agent_rf_source_ready),            //       rf_source.ready
+		.rf_source_valid         (onchip_flash_data_agent_rf_source_valid),            //                .valid
+		.rf_source_startofpacket (onchip_flash_data_agent_rf_source_startofpacket),    //                .startofpacket
+		.rf_source_endofpacket   (onchip_flash_data_agent_rf_source_endofpacket),      //                .endofpacket
+		.rf_source_data          (onchip_flash_data_agent_rf_source_data),             //                .data
+		.rdata_fifo_sink_ready   (avalon_st_adapter_001_out_0_ready),                  // rdata_fifo_sink.ready
+		.rdata_fifo_sink_valid   (avalon_st_adapter_001_out_0_valid),                  //                .valid
+		.rdata_fifo_sink_data    (avalon_st_adapter_001_out_0_data),                   //                .data
+		.rdata_fifo_sink_error   (avalon_st_adapter_001_out_0_error),                  //                .error
+		.rdata_fifo_src_ready    (onchip_flash_data_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
+		.rdata_fifo_src_valid    (onchip_flash_data_agent_rdata_fifo_src_valid),       //                .valid
+		.rdata_fifo_src_data     (onchip_flash_data_agent_rdata_fifo_src_data),        //                .data
+		.m0_response             (2'b00),                                              //     (terminated)
+		.m0_writeresponsevalid   (1'b0)                                                //     (terminated)
+	);
+
+	altera_avalon_sc_fifo #(
+		.SYMBOLS_PER_BEAT    (1),
+		.BITS_PER_SYMBOL     (98),
+		.FIFO_DEPTH          (2),
+		.CHANNEL_WIDTH       (0),
+		.ERROR_WIDTH         (0),
+		.USE_PACKETS         (1),
+		.USE_FILL_LEVEL      (0),
+		.EMPTY_LATENCY       (1),
+		.USE_MEMORY_BLOCKS   (0),
+		.USE_STORE_FORWARD   (0),
+		.USE_ALMOST_FULL_IF  (0),
+		.USE_ALMOST_EMPTY_IF (0)
+	) onchip_flash_data_agent_rsp_fifo (
+		.clk               (clk_source_clk_clk),                                 //       clk.clk
+		.reset             (avalon_bridge_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
+		.in_data           (onchip_flash_data_agent_rf_source_data),             //        in.data
+		.in_valid          (onchip_flash_data_agent_rf_source_valid),            //          .valid
+		.in_ready          (onchip_flash_data_agent_rf_source_ready),            //          .ready
+		.in_startofpacket  (onchip_flash_data_agent_rf_source_startofpacket),    //          .startofpacket
+		.in_endofpacket    (onchip_flash_data_agent_rf_source_endofpacket),      //          .endofpacket
+		.out_data          (onchip_flash_data_agent_rsp_fifo_out_data),          //       out.data
+		.out_valid         (onchip_flash_data_agent_rsp_fifo_out_valid),         //          .valid
+		.out_ready         (onchip_flash_data_agent_rsp_fifo_out_ready),         //          .ready
+		.out_startofpacket (onchip_flash_data_agent_rsp_fifo_out_startofpacket), //          .startofpacket
+		.out_endofpacket   (onchip_flash_data_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
+		.csr_address       (2'b00),                                              // (terminated)
+		.csr_read          (1'b0),                                               // (terminated)
+		.csr_write         (1'b0),                                               // (terminated)
+		.csr_readdata      (),                                                   // (terminated)
+		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated)
+		.almost_full_data  (),                                                   // (terminated)
+		.almost_empty_data (),                                                   // (terminated)
+		.in_empty          (1'b0),                                               // (terminated)
+		.out_empty         (),                                                   // (terminated)
+		.in_error          (1'b0),                                               // (terminated)
+		.out_error         (),                                                   // (terminated)
+		.in_channel        (1'b0),                                               // (terminated)
+		.out_channel       ()                                                    // (terminated)
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_router router (
+		.sink_ready         (avalon_bridge_avalon_master_agent_cp_ready),         //      sink.ready
+		.sink_valid         (avalon_bridge_avalon_master_agent_cp_valid),         //          .valid
+		.sink_data          (avalon_bridge_avalon_master_agent_cp_data),          //          .data
+		.sink_startofpacket (avalon_bridge_avalon_master_agent_cp_startofpacket), //          .startofpacket
+		.sink_endofpacket   (avalon_bridge_avalon_master_agent_cp_endofpacket),   //          .endofpacket
+		.clk                (clk_source_clk_clk),                                 //       clk.clk
+		.reset              (avalon_bridge_reset_reset_bridge_in_reset_reset),    // clk_reset.reset
+		.src_ready          (router_src_ready),                                   //       src.ready
+		.src_valid          (router_src_valid),                                   //          .valid
+		.src_data           (router_src_data),                                    //          .data
+		.src_channel        (router_src_channel),                                 //          .channel
+		.src_startofpacket  (router_src_startofpacket),                           //          .startofpacket
+		.src_endofpacket    (router_src_endofpacket)                              //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001 router_001 (
+		.sink_ready         (onchip_flash_csr_agent_rp_ready),                 //      sink.ready
+		.sink_valid         (onchip_flash_csr_agent_rp_valid),                 //          .valid
+		.sink_data          (onchip_flash_csr_agent_rp_data),                  //          .data
+		.sink_startofpacket (onchip_flash_csr_agent_rp_startofpacket),         //          .startofpacket
+		.sink_endofpacket   (onchip_flash_csr_agent_rp_endofpacket),           //          .endofpacket
+		.clk                (clk_source_clk_clk),                              //       clk.clk
+		.reset              (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_001_src_ready),                            //       src.ready
+		.src_valid          (router_001_src_valid),                            //          .valid
+		.src_data           (router_001_src_data),                             //          .data
+		.src_channel        (router_001_src_channel),                          //          .channel
+		.src_startofpacket  (router_001_src_startofpacket),                    //          .startofpacket
+		.src_endofpacket    (router_001_src_endofpacket)                       //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001 router_002 (
+		.sink_ready         (onchip_flash_data_agent_rp_ready),                //      sink.ready
+		.sink_valid         (onchip_flash_data_agent_rp_valid),                //          .valid
+		.sink_data          (onchip_flash_data_agent_rp_data),                 //          .data
+		.sink_startofpacket (onchip_flash_data_agent_rp_startofpacket),        //          .startofpacket
+		.sink_endofpacket   (onchip_flash_data_agent_rp_endofpacket),          //          .endofpacket
+		.clk                (clk_source_clk_clk),                              //       clk.clk
+		.reset              (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready          (router_002_src_ready),                            //       src.ready
+		.src_valid          (router_002_src_valid),                            //          .valid
+		.src_data           (router_002_src_data),                             //          .data
+		.src_channel        (router_002_src_channel),                          //          .channel
+		.src_startofpacket  (router_002_src_startofpacket),                    //          .startofpacket
+		.src_endofpacket    (router_002_src_endofpacket)                       //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux cmd_demux (
+		.clk                (clk_source_clk_clk),                              //       clk.clk
+		.reset              (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_src_ready),                                //      sink.ready
+		.sink_channel       (router_src_channel),                              //          .channel
+		.sink_data          (router_src_data),                                 //          .data
+		.sink_startofpacket (router_src_startofpacket),                        //          .startofpacket
+		.sink_endofpacket   (router_src_endofpacket),                          //          .endofpacket
+		.sink_valid         (router_src_valid),                                //          .valid
+		.src0_ready         (cmd_demux_src0_ready),                            //      src0.ready
+		.src0_valid         (cmd_demux_src0_valid),                            //          .valid
+		.src0_data          (cmd_demux_src0_data),                             //          .data
+		.src0_channel       (cmd_demux_src0_channel),                          //          .channel
+		.src0_startofpacket (cmd_demux_src0_startofpacket),                    //          .startofpacket
+		.src0_endofpacket   (cmd_demux_src0_endofpacket),                      //          .endofpacket
+		.src1_ready         (cmd_demux_src1_ready),                            //      src1.ready
+		.src1_valid         (cmd_demux_src1_valid),                            //          .valid
+		.src1_data          (cmd_demux_src1_data),                             //          .data
+		.src1_channel       (cmd_demux_src1_channel),                          //          .channel
+		.src1_startofpacket (cmd_demux_src1_startofpacket),                    //          .startofpacket
+		.src1_endofpacket   (cmd_demux_src1_endofpacket)                       //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux cmd_mux (
+		.clk                 (clk_source_clk_clk),                              //       clk.clk
+		.reset               (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_src_ready),                               //       src.ready
+		.src_valid           (cmd_mux_src_valid),                               //          .valid
+		.src_data            (cmd_mux_src_data),                                //          .data
+		.src_channel         (cmd_mux_src_channel),                             //          .channel
+		.src_startofpacket   (cmd_mux_src_startofpacket),                       //          .startofpacket
+		.src_endofpacket     (cmd_mux_src_endofpacket),                         //          .endofpacket
+		.sink0_ready         (cmd_demux_src0_ready),                            //     sink0.ready
+		.sink0_valid         (cmd_demux_src0_valid),                            //          .valid
+		.sink0_channel       (cmd_demux_src0_channel),                          //          .channel
+		.sink0_data          (cmd_demux_src0_data),                             //          .data
+		.sink0_startofpacket (cmd_demux_src0_startofpacket),                    //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                       //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux cmd_mux_001 (
+		.clk                 (clk_source_clk_clk),                              //       clk.clk
+		.reset               (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (cmd_mux_001_src_ready),                           //       src.ready
+		.src_valid           (cmd_mux_001_src_valid),                           //          .valid
+		.src_data            (cmd_mux_001_src_data),                            //          .data
+		.src_channel         (cmd_mux_001_src_channel),                         //          .channel
+		.src_startofpacket   (cmd_mux_001_src_startofpacket),                   //          .startofpacket
+		.src_endofpacket     (cmd_mux_001_src_endofpacket),                     //          .endofpacket
+		.sink0_ready         (cmd_demux_src1_ready),                            //     sink0.ready
+		.sink0_valid         (cmd_demux_src1_valid),                            //          .valid
+		.sink0_channel       (cmd_demux_src1_channel),                          //          .channel
+		.sink0_data          (cmd_demux_src1_data),                             //          .data
+		.sink0_startofpacket (cmd_demux_src1_startofpacket),                    //          .startofpacket
+		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                       //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux rsp_demux (
+		.clk                (clk_source_clk_clk),                              //       clk.clk
+		.reset              (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_001_src_ready),                            //      sink.ready
+		.sink_channel       (router_001_src_channel),                          //          .channel
+		.sink_data          (router_001_src_data),                             //          .data
+		.sink_startofpacket (router_001_src_startofpacket),                    //          .startofpacket
+		.sink_endofpacket   (router_001_src_endofpacket),                      //          .endofpacket
+		.sink_valid         (router_001_src_valid),                            //          .valid
+		.src0_ready         (rsp_demux_src0_ready),                            //      src0.ready
+		.src0_valid         (rsp_demux_src0_valid),                            //          .valid
+		.src0_data          (rsp_demux_src0_data),                             //          .data
+		.src0_channel       (rsp_demux_src0_channel),                          //          .channel
+		.src0_startofpacket (rsp_demux_src0_startofpacket),                    //          .startofpacket
+		.src0_endofpacket   (rsp_demux_src0_endofpacket)                       //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux rsp_demux_001 (
+		.clk                (clk_source_clk_clk),                              //       clk.clk
+		.reset              (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.sink_ready         (router_002_src_ready),                            //      sink.ready
+		.sink_channel       (router_002_src_channel),                          //          .channel
+		.sink_data          (router_002_src_data),                             //          .data
+		.sink_startofpacket (router_002_src_startofpacket),                    //          .startofpacket
+		.sink_endofpacket   (router_002_src_endofpacket),                      //          .endofpacket
+		.sink_valid         (router_002_src_valid),                            //          .valid
+		.src0_ready         (rsp_demux_001_src0_ready),                        //      src0.ready
+		.src0_valid         (rsp_demux_001_src0_valid),                        //          .valid
+		.src0_data          (rsp_demux_001_src0_data),                         //          .data
+		.src0_channel       (rsp_demux_001_src0_channel),                      //          .channel
+		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                //          .startofpacket
+		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                   //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux rsp_mux (
+		.clk                 (clk_source_clk_clk),                              //       clk.clk
+		.reset               (avalon_bridge_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+		.src_ready           (rsp_mux_src_ready),                               //       src.ready
+		.src_valid           (rsp_mux_src_valid),                               //          .valid
+		.src_data            (rsp_mux_src_data),                                //          .data
+		.src_channel         (rsp_mux_src_channel),                             //          .channel
+		.src_startofpacket   (rsp_mux_src_startofpacket),                       //          .startofpacket
+		.src_endofpacket     (rsp_mux_src_endofpacket),                         //          .endofpacket
+		.sink0_ready         (rsp_demux_src0_ready),                            //     sink0.ready
+		.sink0_valid         (rsp_demux_src0_valid),                            //          .valid
+		.sink0_channel       (rsp_demux_src0_channel),                          //          .channel
+		.sink0_data          (rsp_demux_src0_data),                             //          .data
+		.sink0_startofpacket (rsp_demux_src0_startofpacket),                    //          .startofpacket
+		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                      //          .endofpacket
+		.sink1_ready         (rsp_demux_001_src0_ready),                        //     sink1.ready
+		.sink1_valid         (rsp_demux_001_src0_valid),                        //          .valid
+		.sink1_channel       (rsp_demux_001_src0_channel),                      //          .channel
+		.sink1_data          (rsp_demux_001_src0_data),                         //          .data
+		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                //          .startofpacket
+		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket)                   //          .endofpacket
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter (
+		.in_clk_0_clk   (clk_source_clk_clk),                              // in_clk_0.clk
+		.in_rst_0_reset (avalon_bridge_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (onchip_flash_csr_agent_rdata_fifo_src_data),      //     in_0.data
+		.in_0_valid     (onchip_flash_csr_agent_rdata_fifo_src_valid),     //         .valid
+		.in_0_ready     (onchip_flash_csr_agent_rdata_fifo_src_ready),     //         .ready
+		.out_0_data     (avalon_st_adapter_out_0_data),                    //    out_0.data
+		.out_0_valid    (avalon_st_adapter_out_0_valid),                   //         .valid
+		.out_0_ready    (avalon_st_adapter_out_0_ready),                   //         .ready
+		.out_0_error    (avalon_st_adapter_out_0_error)                    //         .error
+	);
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter #(
+		.inBitsPerSymbol (34),
+		.inUsePackets    (0),
+		.inDataWidth     (34),
+		.inChannelWidth  (0),
+		.inErrorWidth    (0),
+		.inUseEmptyPort  (0),
+		.inUseValid      (1),
+		.inUseReady      (1),
+		.inReadyLatency  (0),
+		.outDataWidth    (34),
+		.outChannelWidth (0),
+		.outErrorWidth   (1),
+		.outUseEmptyPort (0),
+		.outUseValid     (1),
+		.outUseReady     (1),
+		.outReadyLatency (0)
+	) avalon_st_adapter_001 (
+		.in_clk_0_clk   (clk_source_clk_clk),                              // in_clk_0.clk
+		.in_rst_0_reset (avalon_bridge_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+		.in_0_data      (onchip_flash_data_agent_rdata_fifo_src_data),     //     in_0.data
+		.in_0_valid     (onchip_flash_data_agent_rdata_fifo_src_valid),    //         .valid
+		.in_0_ready     (onchip_flash_data_agent_rdata_fifo_src_ready),    //         .ready
+		.out_0_data     (avalon_st_adapter_001_out_0_data),                //    out_0.data
+		.out_0_valid    (avalon_st_adapter_001_out_0_valid),               //         .valid
+		.out_0_ready    (avalon_st_adapter_001_out_0_ready),               //         .ready
+		.out_0_error    (avalon_st_adapter_001_out_0_error)                //         .error
+	);
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v
new file mode 100644
index 0000000..fae60e7
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v
@@ -0,0 +1,202 @@
+// flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter.v
+
+// This file was auto-generated from altera_avalon_st_adapter_hw.tcl.  If you edit it your changes
+// will probably be lost.
+// 
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter #(
+		parameter inBitsPerSymbol = 34,
+		parameter inUsePackets    = 0,
+		parameter inDataWidth     = 34,
+		parameter inChannelWidth  = 0,
+		parameter inErrorWidth    = 0,
+		parameter inUseEmptyPort  = 0,
+		parameter inUseValid      = 1,
+		parameter inUseReady      = 1,
+		parameter inReadyLatency  = 0,
+		parameter outDataWidth    = 34,
+		parameter outChannelWidth = 0,
+		parameter outErrorWidth   = 1,
+		parameter outUseEmptyPort = 0,
+		parameter outUseValid     = 1,
+		parameter outUseReady     = 1,
+		parameter outReadyLatency = 0
+	) (
+		input  wire        in_clk_0_clk,   // in_clk_0.clk
+		input  wire        in_rst_0_reset, // in_rst_0.reset
+		input  wire [33:0] in_0_data,      //     in_0.data
+		input  wire        in_0_valid,     //         .valid
+		output wire        in_0_ready,     //         .ready
+		output wire [33:0] out_0_data,     //    out_0.data
+		output wire        out_0_valid,    //         .valid
+		input  wire        out_0_ready,    //         .ready
+		output wire [0:0]  out_0_error     //         .error
+	);
+
+	generate
+		// If any of the display statements (or deliberately broken
+		// instantiations) within this generate block triggers then this module
+		// has been instantiated this module with a set of parameters different
+		// from those it was generated for.  This will usually result in a
+		// non-functioning system.
+		if (inBitsPerSymbol != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inbitspersymbol_check ( .error(1'b1) );
+		end
+		if (inUsePackets != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusepackets_check ( .error(1'b1) );
+		end
+		if (inDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					indatawidth_check ( .error(1'b1) );
+		end
+		if (inChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inchannelwidth_check ( .error(1'b1) );
+		end
+		if (inErrorWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inerrorwidth_check ( .error(1'b1) );
+		end
+		if (inUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseemptyport_check ( .error(1'b1) );
+		end
+		if (inUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inusevalid_check ( .error(1'b1) );
+		end
+		if (inUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inuseready_check ( .error(1'b1) );
+		end
+		if (inReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					inreadylatency_check ( .error(1'b1) );
+		end
+		if (outDataWidth != 34)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outdatawidth_check ( .error(1'b1) );
+		end
+		if (outChannelWidth != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outchannelwidth_check ( .error(1'b1) );
+		end
+		if (outErrorWidth != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outerrorwidth_check ( .error(1'b1) );
+		end
+		if (outUseEmptyPort != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseemptyport_check ( .error(1'b1) );
+		end
+		if (outUseValid != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outusevalid_check ( .error(1'b1) );
+		end
+		if (outUseReady != 1)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outuseready_check ( .error(1'b1) );
+		end
+		if (outReadyLatency != 0)
+		begin
+			initial begin
+				$display("Generated module instantiated with wrong parameters");
+				$stop;
+			end
+			instantiated_with_wrong_parameters_error_see_comment_above
+					outreadylatency_check ( .error(1'b1) );
+		end
+	endgenerate
+
+	flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
+		.clk       (in_clk_0_clk),    //   clk.clk
+		.reset_n   (~in_rst_0_reset), // reset.reset_n
+		.in_data   (in_0_data),       //    in.data
+		.in_valid  (in_0_valid),      //      .valid
+		.in_ready  (in_0_ready),      //      .ready
+		.out_data  (out_0_data),      //   out.data
+		.out_valid (out_0_valid),     //      .valid
+		.out_ready (out_0_ready),     //      .ready
+		.out_error (out_0_error)      //      .error
+	);
+
+endmodule
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
new file mode 100644
index 0000000..f91d7a9
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
@@ -0,0 +1,107 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2013 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+ 
+// $Id: //acds/rel/13.1/ip/.../avalon-st_error_adapter.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2013/09/09 $
+// $Author: dmunday $
+
+
+// --------------------------------------------------------------------------------
+//| Avalon Streaming Error Adapter
+// --------------------------------------------------------------------------------
+
+`timescale 1ns / 100ps
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:        flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+//   use_ready:          true
+//   use_packets:        false
+//   use_empty:          0
+//   empty_width:        0
+//   data_width:         34
+//   channel_width:      0
+//   in_error_width:     0
+//   out_error_width:    1
+//   in_errors_list      
+//   in_errors_indices   0
+//   out_errors_list     
+//   has_in_error_desc:  FALSE
+//   has_out_error_desc: FALSE
+//   out_has_other:      FALSE
+//   out_other_index:    -1
+//   dumpVar:            
+//   inString:            in_error[
+//   closeString:        ] |
+
+// ------------------------------------------
+
+
+
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_avalon_st_adapter_error_adapter_0
+(
+ // Interface: in
+ output reg         in_ready,
+ input              in_valid,
+ input [34-1: 0]     in_data,
+ // Interface: out
+ input               out_ready,
+ output reg          out_valid,
+ output reg [34-1: 0] out_data,
+ output reg [0:0]         out_error,
+  // Interface: clk
+ input              clk,
+ // Interface: reset
+ input              reset_n
+
+ /*AUTOARG*/);
+   
+   reg in_error = 0;
+   initial in_error = 0;
+
+   // ---------------------------------------------------------------------
+   //| Pass-through Mapping
+   // ---------------------------------------------------------------------
+   always_comb begin
+      in_ready = out_ready;
+      out_valid = in_valid;
+      out_data = in_data;
+
+   end
+
+   // ---------------------------------------------------------------------
+   //| Error Mapping 
+   // ---------------------------------------------------------------------
+   always_comb begin
+      out_error = 0;
+      
+      out_error = in_error;
+                                    
+   end //always @*
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv
new file mode 100644
index 0000000..a428437
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux
+//   ST_DATA_W:           97
+//   ST_CHANNEL_W:        2
+//   NUM_OUTPUTS:         2
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [97-1    : 0]   sink_data, // ST_DATA_W=97
+    input  [2-1 : 0]   sink_channel, // ST_CHANNEL_W=2
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [97-1    : 0] src0_data, // ST_DATA_W=97
+    output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+    output reg                      src1_valid,
+    output reg [97-1    : 0] src1_data, // ST_DATA_W=97
+    output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
+    output reg                      src1_startofpacket,
+    output reg                      src1_endofpacket,
+    input                           src1_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 2;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+        src1_data          = sink_data;
+        src1_startofpacket = sink_startofpacket;
+        src1_endofpacket   = sink_endofpacket;
+        src1_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src1_valid         = sink_channel[1] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+    assign ready_vector[1] = src1_ready;
+
+    assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv
new file mode 100644
index 0000000..7aaba76
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux.sv
@@ -0,0 +1,96 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux
+//   NUM_INPUTS:          1
+//   ARBITRATION_SHARES:  1
+//   ARBITRATION_SCHEME   "round-robin"
+//   PIPELINE_ARB:        1
+//   PKT_TRANS_LOCK:      64 (arbitration locking enabled)
+//   ST_DATA_W:           97
+//   ST_CHANNEL_W:        2
+// ------------------------------------------
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_cmd_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [97-1   : 0]  sink0_data,
+    input [2-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [97-1    : 0] src_data,
+    output [2-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 97 + 2 + 2;
+    localparam NUM_INPUTS       = 1;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 1;
+    localparam ST_DATA_W        = 97;
+    localparam ST_CHANNEL_W     = 2;
+    localparam PKT_TRANS_LOCK   = 64;
+
+    assign	src_valid			=  sink0_valid;
+    assign	src_data			=  sink0_data;
+    assign	src_channel			=  sink0_channel;
+    assign	src_startofpacket  	        =  sink0_startofpacket;
+    assign	src_endofpacket		        =  sink0_endofpacket;
+    assign	sink0_ready			=  src_ready;
+endmodule
+
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv
new file mode 100644
index 0000000..51b0862
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router.sv
@@ -0,0 +1,227 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_router_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 1,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 1 
+   )
+  (output [83 - 83 : 0] default_destination_id,
+   output [2-1 : 0] default_wr_channel,
+   output [2-1 : 0] default_rd_channel,
+   output [2-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[83 - 83 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_router
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [97-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [97-1    : 0] src_data,
+    output reg [2-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 59;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 83;
+    localparam PKT_DEST_ID_L = 83;
+    localparam PKT_PROTECTION_H = 87;
+    localparam PKT_PROTECTION_L = 85;
+    localparam ST_DATA_W = 97;
+    localparam ST_CHANNEL_W = 2;
+    localparam DECODER_TYPE = 0;
+
+    localparam PKT_TRANS_WRITE = 62;
+    localparam PKT_TRANS_READ  = 63;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    localparam PAD0 = log2ceil(64'h40000 - 64'h0); 
+    localparam PAD1 = log2ceil(64'h80008 - 64'h80000); 
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h80008;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH-1;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+      reg [PKT_ADDR_W-1 : 0] address;
+      always @* begin
+        address = {PKT_ADDR_W{1'b0}};
+        address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+      end   
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [PKT_DEST_ID_W-1:0] default_destid;
+    wire [2-1 : 0] default_src_channel;
+
+
+
+
+
+
+    flash_interface_10M04SCU169C8G_mm_interconnect_0_router_default_decode the_default_decode(
+      .default_destination_id (default_destid),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+        src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+        // --------------------------------------------------
+        // Address Decoder
+        // Sets the channel and destination ID based on the address
+        // --------------------------------------------------
+
+    // ( 0x0 .. 0x40000 )
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 20'h0   ) begin
+            src_channel = 2'b10;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+    end
+
+    // ( 0x80000 .. 0x80008 )
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 20'h80000   ) begin
+            src_channel = 2'b01;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+    end
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv
new file mode 100644
index 0000000..4f5b05b
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001.sv
@@ -0,0 +1,215 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on 
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001_default_decode
+  #(
+     parameter DEFAULT_CHANNEL = 0,
+               DEFAULT_WR_CHANNEL = -1,
+               DEFAULT_RD_CHANNEL = -1,
+               DEFAULT_DESTID = 0 
+   )
+  (output [83 - 83 : 0] default_destination_id,
+   output [2-1 : 0] default_wr_channel,
+   output [2-1 : 0] default_rd_channel,
+   output [2-1 : 0] default_src_channel
+  );
+
+  assign default_destination_id = 
+    DEFAULT_DESTID[83 - 83 : 0];
+
+  generate
+    if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+      assign default_src_channel = '0;
+    end
+    else begin : default_channel_assignment
+      assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
+    end
+  endgenerate
+
+  generate
+    if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+      assign default_wr_channel = '0;
+      assign default_rd_channel = '0;
+    end
+    else begin : default_rw_channel_assignment
+      assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
+      assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
+    end
+  endgenerate
+
+endmodule
+
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001
+(
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    input clk,
+    input reset,
+
+    // -------------------
+    // Command Sink (Input)
+    // -------------------
+    input                       sink_valid,
+    input  [97-1 : 0]    sink_data,
+    input                       sink_startofpacket,
+    input                       sink_endofpacket,
+    output                      sink_ready,
+
+    // -------------------
+    // Command Source (Output)
+    // -------------------
+    output                          src_valid,
+    output reg [97-1    : 0] src_data,
+    output reg [2-1 : 0] src_channel,
+    output                          src_startofpacket,
+    output                          src_endofpacket,
+    input                           src_ready
+);
+
+    // -------------------------------------------------------
+    // Local parameters and variables
+    // -------------------------------------------------------
+    localparam PKT_ADDR_H = 59;
+    localparam PKT_ADDR_L = 36;
+    localparam PKT_DEST_ID_H = 83;
+    localparam PKT_DEST_ID_L = 83;
+    localparam PKT_PROTECTION_H = 87;
+    localparam PKT_PROTECTION_L = 85;
+    localparam ST_DATA_W = 97;
+    localparam ST_CHANNEL_W = 2;
+    localparam DECODER_TYPE = 1;
+
+    localparam PKT_TRANS_WRITE = 62;
+    localparam PKT_TRANS_READ  = 63;
+
+    localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+    localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+    // -------------------------------------------------------
+    // Figure out the number of bits to mask off for each slave span
+    // during address decoding
+    // -------------------------------------------------------
+    // -------------------------------------------------------
+    // Work out which address bits are significant based on the
+    // address range of the slaves. If the required width is too
+    // large or too small, we use the address field width instead.
+    // -------------------------------------------------------
+    localparam ADDR_RANGE = 64'h0;
+    localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+    localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+                                  (RANGE_ADDR_WIDTH == 0) ?
+                                        PKT_ADDR_H :
+                                        PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+    localparam RG = RANGE_ADDR_WIDTH;
+    localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+    reg [PKT_DEST_ID_W-1 : 0] destid;
+
+    // -------------------------------------------------------
+    // Pass almost everything through, untouched
+    // -------------------------------------------------------
+    assign sink_ready        = src_ready;
+    assign src_valid         = sink_valid;
+    assign src_startofpacket = sink_startofpacket;
+    assign src_endofpacket   = sink_endofpacket;
+    wire [2-1 : 0] default_src_channel;
+
+
+
+
+
+
+    flash_interface_10M04SCU169C8G_mm_interconnect_0_router_001_default_decode the_default_decode(
+      .default_destination_id (),
+      .default_wr_channel   (),
+      .default_rd_channel   (),
+      .default_src_channel  (default_src_channel)
+    );
+
+    always @* begin
+        src_data    = sink_data;
+        src_channel = default_src_channel;
+
+        // --------------------------------------------------
+        // DestinationID Decoder
+        // Sets the channel based on the destination ID.
+        // --------------------------------------------------
+        destid      = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+
+
+
+        if (destid == 0 ) begin
+            src_channel = 2'b1;
+        end
+
+
+end
+
+
+    // --------------------------------------------------
+    // Ceil(log2()) function
+    // --------------------------------------------------
+    function integer log2ceil;
+        input reg[65:0] val;
+        reg [65:0] i;
+
+        begin
+            i = 1;
+            log2ceil = 0;
+
+            while (i < val) begin
+                log2ceil = log2ceil + 1;
+                i = i << 1;
+            end
+        end
+    endfunction
+
+endmodule
+
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv
new file mode 100644
index 0000000..019f5b2
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux.sv
@@ -0,0 +1,100 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux
+//   ST_DATA_W:           97
+//   ST_CHANNEL_W:        2
+//   NUM_OUTPUTS:         1
+//   VALID_WIDTH:         1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_demux
+(
+    // -------------------
+    // Sink
+    // -------------------
+    input  [1-1      : 0]   sink_valid,
+    input  [97-1    : 0]   sink_data, // ST_DATA_W=97
+    input  [2-1 : 0]   sink_channel, // ST_CHANNEL_W=2
+    input                         sink_startofpacket,
+    input                         sink_endofpacket,
+    output                        sink_ready,
+
+    // -------------------
+    // Sources 
+    // -------------------
+    output reg                      src0_valid,
+    output reg [97-1    : 0] src0_data, // ST_DATA_W=97
+    output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
+    output reg                      src0_startofpacket,
+    output reg                      src0_endofpacket,
+    input                           src0_ready,
+
+
+    // -------------------
+    // Clock & Reset
+    // -------------------
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+    input clk,
+    (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+    input reset
+
+);
+
+    localparam NUM_OUTPUTS = 1;
+    wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+    // -------------------
+    // Demux
+    // -------------------
+    always @* begin
+        src0_data          = sink_data;
+        src0_startofpacket = sink_startofpacket;
+        src0_endofpacket   = sink_endofpacket;
+        src0_channel       = sink_channel >> NUM_OUTPUTS;
+
+        src0_valid         = sink_channel[0] && sink_valid;
+
+    end
+
+    // -------------------
+    // Backpressure
+    // -------------------
+    assign ready_vector[0] = src0_ready;
+
+    assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+
+endmodule
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv
new file mode 100644
index 0000000..4f7c30a
--- /dev/null
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/simulation/submodules/flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux.sv
@@ -0,0 +1,345 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License Subscription 
+// Agreement, Altera MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+//   output_name:         flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux
+//   NUM_INPUTS:          2
+//   ARBITRATION_SHARES:  1 1
+//   ARBITRATION_SCHEME   "no-arb"
+//   PIPELINE_ARB:        0
+//   PKT_TRANS_LOCK:      64 (arbitration locking enabled)
+//   ST_DATA_W:           97
+//   ST_CHANNEL_W:        2
+// ------------------------------------------
+
+module flash_interface_10M04SCU169C8G_mm_interconnect_0_rsp_mux
+(
+    // ----------------------
+    // Sinks
+    // ----------------------
+    input                       sink0_valid,
+    input [97-1   : 0]  sink0_data,
+    input [2-1: 0]  sink0_channel,
+    input                       sink0_startofpacket,
+    input                       sink0_endofpacket,
+    output                      sink0_ready,
+
+    input                       sink1_valid,
+    input [97-1   : 0]  sink1_data,
+    input [2-1: 0]  sink1_channel,
+    input                       sink1_startofpacket,
+    input                       sink1_endofpacket,
+    output                      sink1_ready,
+
+
+    // ----------------------
+    // Source
+    // ----------------------
+    output                      src_valid,
+    output [97-1    : 0] src_data,
+    output [2-1 : 0] src_channel,
+    output                      src_startofpacket,
+    output                      src_endofpacket,
+    input                       src_ready,
+
+    // ----------------------
+    // Clock & Reset
+    // ----------------------
+    input clk,
+    input reset
+);
+    localparam PAYLOAD_W        = 97 + 2 + 2;
+    localparam NUM_INPUTS       = 2;
+    localparam SHARE_COUNTER_W  = 1;
+    localparam PIPELINE_ARB     = 0;
+    localparam ST_DATA_W        = 97;
+    localparam ST_CHANNEL_W     = 2;
+    localparam PKT_TRANS_LOCK   = 64;
+
+    // ------------------------------------------
+    // Signals
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0]      request;
+    wire [NUM_INPUTS - 1 : 0]      valid;
+    wire [NUM_INPUTS - 1 : 0]      grant;
+    wire [NUM_INPUTS - 1 : 0]      next_grant;
+    reg [NUM_INPUTS - 1 : 0]       saved_grant;
+    reg [PAYLOAD_W - 1 : 0]        src_payload;
+    wire                           last_cycle;
+    reg                            packet_in_progress;
+    reg                            update_grant;
+
+    wire [PAYLOAD_W - 1 : 0] sink0_payload;
+    wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+    assign valid[0] = sink0_valid;
+    assign valid[1] = sink1_valid;
+
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Grant Logic & Updates
+    // ------------------------------------------
+    // ------------------------------------------
+    reg [NUM_INPUTS - 1 : 0] lock;
+    always @* begin
+      lock[0] = sink0_data[64];
+      lock[1] = sink1_data[64];
+    end
+
+    assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+    // ------------------------------------------
+    // We're working on a packet at any time valid is high, except
+    // when this is the endofpacket.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        packet_in_progress <= 1'b0;
+      end
+      else begin
+        if (last_cycle)
+          packet_in_progress <= 1'b0; 
+        else if (src_valid)
+          packet_in_progress <= 1'b1;
+      end
+    end
+
+
+    // ------------------------------------------
+    // Shares
+    //
+    // Special case: all-equal shares _should_ be optimized into assigning a
+    // constant to next_grant_share.
+    // Special case: all-1's shares _should_ result in the share counter
+    // being optimized away.
+    // ------------------------------------------
+    // Input  |  arb shares  |  counter load value
+    // 0      |      1       |  0
+    // 1      |      1       |  0
+     wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+     wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+    // ------------------------------------------
+    // Choose the share value corresponding to the grant.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+    always @* begin
+      next_grant_share =
+    share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+    share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Flag to indicate first packet of an arb sequence.
+    // ------------------------------------------
+    wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+    reg first_packet_r;
+    wire first_packet = grant_changed | first_packet_r;
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        first_packet_r <= 1'b0;
+      end
+      else begin 
+        if (update_grant)
+          first_packet_r <= 1'b1;
+        else if (last_cycle)
+          first_packet_r <= 1'b0;
+        else if (grant_changed)
+          first_packet_r <= 1'b1;
+      end
+    end
+
+    // ------------------------------------------
+    // Compute the next share-count value.
+    // ------------------------------------------
+    reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+    reg [SHARE_COUNTER_W - 1 : 0] share_count;
+    reg share_count_zero_flag;
+
+    always @* begin
+      if (first_packet) begin
+        p1_share_count = next_grant_share;
+      end
+      else begin
+            // Update the counter, but don't decrement below 0.
+        p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+      end
+     end
+
+    // ------------------------------------------
+    // Update the share counter and share-counter=zero flag.
+    // ------------------------------------------
+    always @(posedge clk or posedge reset) begin
+      if (reset) begin
+        share_count <= '0;
+        share_count_zero_flag <= 1'b1;
+      end
+      else begin
+        if (last_cycle) begin
+          share_count <= p1_share_count;
+          share_count_zero_flag <= (p1_share_count == '0);
+        end
+      end
+    end
+
+    // ------------------------------------------
+    // For each input, maintain a final_packet signal which goes active for the
+    // last packet of a full-share packet sequence.  Example: if I have 4
+    // shares and I'm continuously requesting, final_packet is active in the
+    // 4th packet.
+    // ------------------------------------------
+    wire final_packet_0 = 1'b1;
+
+    wire final_packet_1 = 1'b1;
+
+
+    // ------------------------------------------
+    // Concatenate all final_packet signals (wire or reg) into a handy vector.
+    // ------------------------------------------
+    wire [NUM_INPUTS - 1 : 0] final_packet = {
+    final_packet_1,
+    final_packet_0
+    };
+
+    // ------------------------------------------
+    // ------------------------------------------
+    wire p1_done = |(final_packet & grant);
+
+    // ------------------------------------------
+    // Flag for the first cycle of packets within an 
+    // arb sequence
+    // ------------------------------------------
+    reg first_cycle;
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        first_cycle <= 0;
+      else
+        first_cycle <= last_cycle && ~p1_done;
+    end
+
+
+    always @* begin
+      update_grant = 0;
+
+        // ------------------------------------------
+        // No arbitration pipeline, update grant whenever
+        // the current arb winner has consumed all shares,
+        // or all requests are low
+        // ------------------------------------------
+  update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+  update_grant = last_cycle;
+    end
+
+    wire save_grant;
+    assign save_grant = 1;
+    assign grant = next_grant;
+
+    always @(posedge clk, posedge reset) begin
+      if (reset)
+        saved_grant <= '0;
+      else if (save_grant)
+        saved_grant <= next_grant;
+    end
+
+    // ------------------------------------------
+    // ------------------------------------------
+    // Arbitrator
+    // ------------------------------------------
+    // ------------------------------------------
+
+    // ------------------------------------------
+    // Create a request vector that stays high during
+    // the packet for unpipelined arbitration.
+    //
+    // The pipelined arbitration scheme does not require
+    // request to be held high during the packet.
+    // ------------------------------------------
+    assign request = valid;
+
+    wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+                               
+    altera_merlin_arbitrator
+    #(
+    .NUM_REQUESTERS(NUM_INPUTS),
+    .SCHEME ("no-arb"),
+    .PIPELINE (0)
+    ) arb (
+    .clk (clk),
+    .reset (reset),
+    .request (request),
+    .grant (next_grant_from_arb),
+    .save_top_priority (src_valid),
+    .increment_top_priority (update_grant)
+    );
+
+   assign next_grant = next_grant_from_arb;
+                         
+    // ------------------------------------------
+    // ------------------------------------------
+    // Mux
+    //
+    // Implemented as a sum of products.
+    // ------------------------------------------
+    // ------------------------------------------
+
+    assign sink0_ready = src_ready && grant[0];
+    assign sink1_ready = src_ready && grant[1];
+
+    assign src_valid = |(grant & valid);
+
+    always @* begin
+      src_payload =
+      sink0_payload & {PAYLOAD_W {grant[0]} } |
+      sink1_payload & {PAYLOAD_W {grant[1]} };
+    end
+
+    // ------------------------------------------
+    // Mux Payload Mapping
+    // ------------------------------------------
+
+    assign sink0_payload = {sink0_channel,sink0_data,
+    sink0_startofpacket,sink0_endofpacket};
+    assign sink1_payload = {sink1_channel,sink1_data,
+    sink1_startofpacket,sink1_endofpacket};
+
+    assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.debuginfo b/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.debuginfo
index 2447ff5..8685716 100644
--- a/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.debuginfo
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.debuginfo
@@ -5,7 +5,7 @@
  version="22.1"
  fabric="QSYS">
  <!-- Format version 22.1 922 (Future versions may contain additional information.) -->
- <!-- 2024.11.11.08:27:26 -->
+ <!-- 2024.12.06.18:24:42 -->
  <!-- A collection of modules and connections -->
  <parameter name="clockCrossingAdapter">
   <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@@ -57,7 +57,7 @@
  </parameter>
  <parameter name="generationId">
   <type>int</type>
-  <value>1731313641</value>
+  <value>1733509478</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>true</visible>
@@ -4620,5 +4620,5 @@ parameters are a RESULT of the module parameters. -->
   <version>22.1</version>
  </plugin>
  <reportVersion>22.1 922</reportVersion>
- <uniqueIdentifier>04421A2A9CFC000001931A55AF5E</uniqueIdentifier>
+ <uniqueIdentifier>04421A2A9CFC000001939D377C40</uniqueIdentifier>
 </EnsembleReport>
diff --git a/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.qip b/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.qip
index 10a77e3..900402a 100644
--- a/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.qip
+++ b/Quartus/IP/flash_interface_10M04SCU169C8G/synthesis/flash_interface_10M04SCU169C8G.qip
@@ -2,7 +2,7 @@ set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_i
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_TOOL_VERSION "22.1"
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_TOOL_ENV "Qsys"
 set_global_assignment -library "flash_interface_10M04SCU169C8G" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../flash_interface_10M04SCU169C8G.sopcinfo"]
-set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name SLD_INFO "QSYS_NAME flash_interface_10M04SCU169C8G HAS_SOPCINFO 1 GENERATION_ID 1731313641"
+set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name SLD_INFO "QSYS_NAME flash_interface_10M04SCU169C8G HAS_SOPCINFO 1 GENERATION_ID 1733509478"
 set_global_assignment -library "flash_interface_10M04SCU169C8G" -name MISC_FILE [file join $::quartus(qip_path) "../flash_interface_10M04SCU169C8G.cmp"]
 set_global_assignment -library "flash_interface_10M04SCU169C8G" -name SLD_FILE [file join $::quartus(qip_path) "flash_interface_10M04SCU169C8G.debuginfo"]
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
@@ -15,7 +15,7 @@ set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_i
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_REPORT_HIERARCHY "On"
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_INTERNAL "Off"
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTczMTMxMzY0MQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTczMzUwOTQ3OA==::QXV0byBHRU5FUkFUSU9OX0lE"
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::TUFYIDEw::QXV0byBERVZJQ0VfRkFNSUxZ"
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBNMDRTQ1UxNjlDOEc=::QXV0byBERVZJQ0U="
 set_global_assignment -entity "flash_interface_10M04SCU169C8G" -library "flash_interface_10M04SCU169C8G" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="