From 259665fb5a6ecd31da6222a4344763e7f6ea001a Mon Sep 17 00:00:00 2001 From: Jacky Hou - A30492 Date: Thu, 29 Sep 2022 14:17:20 +0800 Subject: [PATCH] APPL-4092: IPv4 fragmented packets are changed --- src/config/proj_opt/proj_opt_ferret_release.h | 8 +-- src/switch/h2tcam.c | 15 +++++- .../vtss_api/base/ocelot/vtss_ocelot_reg.h | 51 ++++++++++++++++++- 3 files changed, 68 insertions(+), 6 deletions(-) diff --git a/src/config/proj_opt/proj_opt_ferret_release.h b/src/config/proj_opt/proj_opt_ferret_release.h index d043d7e..d13dc78 100644 --- a/src/config/proj_opt/proj_opt_ferret_release.h +++ b/src/config/proj_opt/proj_opt_ferret_release.h @@ -31,7 +31,7 @@ #define UNMANAGED_FLOW_CTRL_IF /* Enable debug for TCAM */ -#define UNMANAGED_TCAM_DEBUG_IF 0 +#define UNMANAGED_TCAM_DEBUG_IF 0 /* Enable debug for ANEG disabled and forced 1Gfdx speed for SGMII/SERDES interface * MUST set value =0x2 or 0x9 for CPORT_MAPTO_MIIMBUS accoringly @@ -91,10 +91,10 @@ /**************************************************************************** - * End to End Transparent clock + * One-step End to End Transparent clock ****************************************************************************/ -#define TRANSIT_E2ETC 0 -#define TRANSIT_TCAM_IS2 0 +#define TRANSIT_E2ETC 1 +#define TRANSIT_TCAM_IS2 1 /**************************************************************************** diff --git a/src/switch/h2tcam.c b/src/switch/h2tcam.c index 8349723..a85d659 100644 --- a/src/switch/h2tcam.c +++ b/src/switch/h2tcam.c @@ -77,6 +77,7 @@ typedef enum { IS2_HALF_ETH_PTP_MSG_TYPE, IS2_HALF_ETH_TWO_STEP, IS2_HALF_IPV4_IS_IPV4, + IS2_HALF_IPV4_IS_FRAG, IS2_HALF_IPV4_UDP_TYPE, IS2_HALF_IPV4_DPORT, IS2_HALF_IPV4_PTP_MSG_TYPE, @@ -290,7 +291,7 @@ void h2_tcam_e2e_tc_get(u16 entry_id,tcam_data_conf_t *conf) void h2_tcam_e2e_tc_set(tcam_e2e_tc_t ace_conf) { - if ( is2_entry_id <= MAX_ACE_LIMIT ) { + if ( is2_entry_id <= MAX_ACE_LIMIT ) { if (ace_conf == TCAM_E2E_TC_PTP_ETH) { h2tcam_add_is2_ptp_ethernet(is2_entry_id++,ace_conf); } else if (ace_conf == TCAM_E2E_TC_PTP_IP) { @@ -384,6 +385,10 @@ static void get_offset_len_par(is2_conf_param_t type,u16 *offset) offset[0] = 46; offset[1] = 1; break; + case IS2_HALF_IPV4_IS_FRAG: + offset[0] = 47; + offset[1] = 1; + break; case IS2_HALF_IPV4_UDP_TYPE: offset[0] = 124; offset[1] = 1; @@ -542,6 +547,12 @@ static void h2tcam_is2_set_ipv4_conf(h2ace_is2_t *ace_conf,tcam_data_conf_t *tca value[0] = 1; h2tcam_bit_feild_32bit_set(offset_info[0],offset_info[1],value,tcam_conf->tcam_mask); + get_offset_len_par(IS2_HALF_IPV4_IS_FRAG,offset_info); + value[0]= 0; + h2tcam_bit_feild_32bit_set(offset_info[0],offset_info[1],value,tcam_conf->tcam_entry); + value[0] = 1; + h2tcam_bit_feild_32bit_set(offset_info[0],offset_info[1],value,tcam_conf->tcam_mask); + get_offset_len_par(IS2_HALF_IPV4_UDP_TYPE,offset_info); value[0]=(u32)(ace_conf->pkt_info.ipv4.tcp); h2tcam_bit_feild_32bit_set(offset_info[0],offset_info[1],value,tcam_conf->tcam_entry); @@ -560,11 +571,13 @@ static void h2tcam_is2_set_ipv4_conf(h2ace_is2_t *ace_conf,tcam_data_conf_t *tca value[0] = 2; h2tcam_bit_feild_32bit_set(offset_info[0],offset_info[1],value,tcam_conf->tcam_mask); + get_offset_len_par(IS2_HALF_IPV4_TWO_STEP,offset_info); value[0]=(u32)(ace_conf->pkt_info.ipv4.payload.ptp_payload.ptp_two_step); h2tcam_bit_feild_32bit_set(offset_info[0],offset_info[1],value,tcam_conf->tcam_entry); value[0] = 1; h2tcam_bit_feild_32bit_set(offset_info[0],offset_info[1],value,tcam_conf->tcam_mask); + } static void h2tcam_is2_set_eth_conf(h2ace_is2_t *ace_conf,tcam_data_conf_t *tcam_conf) { diff --git a/src/switch/vtss_api/base/ocelot/vtss_ocelot_reg.h b/src/switch/vtss_api/base/ocelot/vtss_ocelot_reg.h index 4b3224b..a4c9f4d 100644 --- a/src/switch/vtss_api/base/ocelot/vtss_ocelot_reg.h +++ b/src/switch/vtss_api/base/ocelot/vtss_ocelot_reg.h @@ -77,5 +77,54 @@ #define IS1_ACTION_TYPE_SMAC_SIP4 1 #define IS1_ACTION_TYPE_SMAC_SIP6 2 -#endif /* _LUTON26_REG_H */ +/* IS2 half key - IP4_TCP_UDP/IP4_OTHER common */ +//srvl_vcap_key_bit_set(data, IS2_HKO_L3_FRAGMENT, fragment); +//srvl_vcap_key_bit_set(data, IS2_HKO_L3_FRAG_OFS_GT0, VTSS_VCAP_BIT_ANY); +#define VTSS_CHIP_PORTS 11 +#define IS2_HKO_TYPE 0 +#define IS2_HKL_TYPE 4 +#define IS2_HKO_FIRST (IS2_HKO_TYPE + IS2_HKL_TYPE) +#define IS2_HKL_FIRST 1 +#define IS2_HKO_PAG (IS2_HKO_FIRST + IS2_HKL_FIRST) +#define IS2_HKL_PAG 8 +#define IS2_HKO_IGR_PORT_MASK (IS2_HKO_PAG + IS2_HKL_PAG) +#define IS2_HKL_IGR_PORT_MASK (VTSS_CHIP_PORTS + 1) +#define IS2_HKO_SERVICE_FRM (IS2_HKO_IGR_PORT_MASK + IS2_HKL_IGR_PORT_MASK) +#define IS2_HKL_SERVICE_FRM 1 +#define IS2_HKO_HOST_MATCH (IS2_HKO_SERVICE_FRM + IS2_HKL_SERVICE_FRM) +#define IS2_HKL_HOST_MATCH 1 +#define IS2_HKO_L2_MC (IS2_HKO_HOST_MATCH + IS2_HKL_HOST_MATCH) +#define IS2_HKL_L2_MC 1 +#define IS2_HKO_L2_BC (IS2_HKO_L2_MC + IS2_HKL_L2_MC) +#define IS2_HKL_L2_BC 1 +#define IS2_HKO_VLAN_TAGGED (IS2_HKO_L2_BC + IS2_HKL_L2_BC) +#define IS2_HKL_VLAN_TAGGED 1 +#define IS2_HKO_VID (IS2_HKO_VLAN_TAGGED + IS2_HKL_VLAN_TAGGED) +#define IS2_HKL_VID 12 +#define IS2_HKO_DEI (IS2_HKO_VID + IS2_HKL_VID) +#define IS2_HKL_DEI 1 +#define IS2_HKO_PCP (IS2_HKO_DEI + IS2_HKL_DEI) +#define IS2_HKL_PCP 3 + +#define IS2_HKL_PCP 3 +#define IS2_HKO_L2_DMAC (IS2_HKO_PCP + IS2_HKL_PCP) +#define IS2_HKO_IP4 IS2_HKO_L2_DMAC +#define IS2_HKL_IP4 1 +#define IS2_HKO_L3_FRAGMENT (IS2_HKO_IP4 + IS2_HKL_IP4) +#define IS2_HKL_L3_FRAGMENT 1 +#define IS2_HKO_L3_FRAG_OFS_GT0 (IS2_HKO_L3_FRAGMENT + IS2_HKL_L3_FRAGMENT) +#define IS2_HKL_L3_FRAG_OFS_GT0 1 +#define IS2_HKO_L3_OPTIONS (IS2_HKO_L3_FRAG_OFS_GT0 + IS2_HKL_L3_FRAG_OFS_GT0) +#define IS2_HKL_L3_OPTIONS 1 +#define IS2_HKO_L3_TTL_GT0 (IS2_HKO_L3_OPTIONS + IS2_HKL_L3_OPTIONS) +#define IS2_HKL_L3_TTL_GT0 1 +#define IS2_HKO_L3_TOS (IS2_HKO_L3_TTL_GT0 + IS2_HKL_L3_TTL_GT0) +#define IS2_HKL_L3_TOS 8 +#define IS2_HKO_L3_IP4_DIP (IS2_HKO_L3_TOS + IS2_HKL_L3_TOS) +#define IS2_HKL_L3_IP4_DIP 32 +#define IS2_HKO_L3_IP4_SIP (IS2_HKO_L3_IP4_DIP + IS2_HKL_L3_IP4_DIP) +#define IS2_HKL_L3_IP4_SIP 32 +#define IS2_HKO_DIP_EQ_SIP (IS2_HKO_L3_IP4_SIP + IS2_HKL_L3_IP4_SIP) +#define IS2_HKL_DIP_EQ_SIP 1 +#endif /* _VTSS_OCELOT_REG_H_ */