Unused parameters and ports

[malcolm-sci]

Starting from commit 31dbab1, I generated this list of unused parameters and ports. An initial set were generated by verilator-lint. These were removed, and the process repeated until lint clean. Can they be removed?

cheri_ex.sv:  parameter int unsigned HeapBase       = 32'h2001_0000,
cheri_ex.sv:  parameter int unsigned TSMapBase      = 32'h2002_f000,
cheri_ex.sv:  parameter int unsigned TSMapSize      = 1024,
cheri_ex.sv:  localparam int unsigned TSMapTop = TSMapBase+TSMapSize*4;
cheri_ex.sv:  input  logic          instr_valid_i,
cheri_ex.sv:  input  logic [32:0]   lsu_rdata_i,
cheri_ex.sv:  input  reg_cap_t      lsu_rcap_i,
cheri_ex.sv:  input  logic          tbre_lsu_req_i,
cheri_ex.sv:  input  logic          stkz_abort_i,

cheri_tbre.sv:  input  logic          snoop_lsu_req_i,
cheri_tbre.sv:  input  logic          snoop_lsu_is_cap_i,
cheri_tbre.sv:  input  logic          snoop_lsu_cheri_err_i,

cheri_tbre_wrapper.sv:  input  logic          snoop_lsu_req_i,
cheri_tbre_wrapper.sv:  input  logic          snoop_lsu_is_cap_i,
cheri_tbre_wrapper.sv:  input  logic          snoop_lsu_cheri_err_i,

ibex_controller.sv: input  logic                  cheri_ex_valid_i,        // from cheri EX
ibex_controller.sv: input  logic [31:0]           cheri_branch_target_i

ibex_core.sv:  parameter int unsigned TSMapBase         = 32'h2002_f000,

ibex_cs_registers.sv: input  logic                 cheri_csr_access_i,
ibex_cs_registers.sv: input  logic [31:0]          cheri_branch_target_i,

ibex_id_stage.sv: input  logic [31:0]               cheri_branch_target_i

ibex_top_tracing.sv:  parameter bit          HWTraceEn        = 1'b0,

ibex_tracer.sv:  localparam logic [9:0] MEM2 = (1 << 9);
ibex_tracer.sv:  input logic        cheri_tsafe_en_i,
ibex_tracer.sv:  input logic        rvfi_mem_is_cap,

ibexc_top.sv:  parameter rv32b_e      RV32B            = RV32BNone,
ibexc_top.sv:  parameter bit          SecureIbex       = 1'b0,   // placeholder for TB compatbility
ibexc_top.sv:  parameter int unsigned TSMapBase        = 32'h2002_f000, // 4kB default
ibexc_top.sv:  input  prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
ibexc_top.sv:  input  logic [6:0]                   instr_rdata_intg_i,
ibexc_top.sv:  input  logic [6:0]                   data_rdata_intg_i,
ibexc_top.sv:  input  logic                         scramble_key_valid_i,
ibexc_top.sv:  input  logic [SCRAMBLE_KEY_W-1:0]    scramble_key_i,
ibexc_top.sv:  input  logic [SCRAMBLE_NONCE_W-1:0]  scramble_nonce_i,
ibexc_top.sv:  output logic                         scramble_req_o,

ibexc_top_tracing.sv:  parameter int unsigned TSMapBase        = 32'h2004_0000, // 4kB default
ibexc_top_tracing.sv:  input  prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
ibexc_top_tracing.sv:  input  logic [6:0]                   instr_rdata_intg_i,
ibexc_top_tracing.sv:  input  logic [6:0]                   data_rdata_intg_i,
ibexc_top_tracing.sv:  input  logic [6:0]                   tsmap_rdata_intg_i,   // not used in ibexc_top
ibexc_top_tracing.sv:  input  logic                         scramble_key_valid_i,
ibexc_top_tracing.sv:  input  logic [SCRAMBLE_KEY_W-1:0]    scramble_key_i,
ibexc_top_tracing.sv:  input  logic [SCRAMBLE_NONCE_W-1:0]  scramble_nonce_i,
ibexc_top_tracing.sv:  output logic                         scramble_req_o,