From ee8cbf01734d387192c36887c8fca43f429ca292 Mon Sep 17 00:00:00 2001 From: Michael Moll Date: Sun, 18 Feb 2024 16:02:32 +0100 Subject: [PATCH] Revert "clk: starfive: jh7110-sys: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz" This reverts commit fc7b542f8d3d9edcbd036cb650cb0c5fba18f5f9. --- .../clk/starfive/clk-starfive-jh7110-sys.c | 47 +------------------ 1 file changed, 1 insertion(+), 46 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index 8e3892e438e024..8f5e5abfa178db 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -501,52 +501,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) if (ret) return ret; - ret = jh7110_reset_controller_register(priv, "rst-sys", 0); - if (ret) - return ret; - - /* - * Set PLL0 rate to 1.5GHz - * In order to not affect the cpu when the PLL0 rate is changing, - * we need to switch the parent of cpu_root clock to osc clock first, - * and then switch back after setting the PLL0 rate. - */ - pllclk = clk_get(priv->dev, "pll0_out"); - if (!IS_ERR(pllclk)) { - struct clk *osc = clk_get(&pdev->dev, "osc"); - struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk; - struct clk *cpu_core = priv->reg[JH7110_SYSCLK_CPU_CORE].hw.clk; - - if (IS_ERR(osc)) { - clk_put(pllclk); - return PTR_ERR(osc); - } - - /* - * CPU need voltage regulation by CPUfreq if set 1.5GHz. - * So in this driver, cpu_core need to be set the divider to be 2 first - * and will be 750M after setting parent. - */ - ret = clk_set_rate(cpu_core, clk_get_rate(cpu_core) / 2); - if (ret) - goto failed_set; - - ret = clk_set_parent(cpu_root, osc); - if (ret) - goto failed_set; - - ret = clk_set_rate(pllclk, 1500000000); - if (ret) - goto failed_set; - - ret = clk_set_parent(cpu_root, pllclk); - -failed_set: - clk_put(pllclk); - clk_put(osc); - } - - return ret; + return jh7110_reset_controller_register(priv, "rst-sys", 0); } static const struct of_device_id jh7110_syscrg_match[] = {