My very first attempt on pipelined processor.
Also, this is my course project for XJTU CompOrg class.
Features:
- 6-staged vendor-agnostic, FPGA-optimized pipeline. It runs at ~70MHz on XC7A100T-1
- Seperate direct-mapped I/D Cache
- Simulate-everything with verilator (thanks to ZipCPU) to avoid FPGA hell
- Coherence support based on a homemade bus and SI protocol
- UART controller @ 115200Hz
