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hd6309.c
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hd6309.c
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/*
Copyright 2015 by Joseph Forgione
This file is part of VCC (Virtual Color Computer).
VCC (Virtual Color Computer) is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VCC (Virtual Color Computer) is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VCC (Virtual Color Computer). If not, see <http://www.gnu.org/licenses/>.
*/
#include "windows.h"
#include "stdio.h"
#include "hd6309.h"
#include "hd6309defs.h"
#include "tcc1014mmu.h"
#include "logger.h"
//Global variables for CPU Emulation-----------------------
#define NTEST8(r) r>0x7F;
#define NTEST16(r) r>0x7FFF;
#define NTEST32(r) r>0x7FFFFFFF;
#define OVERFLOW8(c,a,b,r) c ^ (((a^b^r)>>7) &1);
#define OVERFLOW16(c,a,b,r) c ^ (((a^b^r)>>15)&1);
#define ZTEST(r) !r;
#define DPADDRESS(r) (dp.Reg |MemRead8(r))
#define IMMADDRESS(r) MemRead16(r)
#define INDADDRESS(r) CalculateEA(MemRead8(r))
#define M65 0
#define M64 1
#define M32 2
#define M21 3
#define M54 4
#define M97 5
#define M85 6
#define M51 7
#define M31 8
#define M1110 9
#define M76 10
#define M75 11
#define M43 12
#define M87 13
#define M86 14
#define M98 15
#define M2726 16
#define M3635 17
#define M3029 18
#define M2827 19
#define M3726 20
#define M3130 21
typedef union
{
unsigned short Reg;
struct
{
unsigned char lsb,msb;
} B;
} cpuregister;
typedef union
{
unsigned int Reg;
struct
{
unsigned short msw,lsw;
} Word;
struct
{
unsigned char mswlsb,mswmsb,lswlsb,lswmsb; //Might be backwards
} Byte;
} wideregister;
#define D_REG q.Word.lsw
#define W_REG q.Word.msw
#define PC_REG pc.Reg
#define X_REG x.Reg
#define Y_REG y.Reg
#define U_REG u.Reg
#define S_REG s.Reg
#define A_REG q.Byte.lswmsb
#define B_REG q.Byte.lswlsb
#define E_REG q.Byte.mswmsb
#define F_REG q.Byte.mswlsb
#define Q_REG q.Reg
#define V_REG v.Reg
#define O_REG z.Reg
static char RegName[16][10]={"D","X","Y","U","S","PC","W","V","A","B","CC","DP","ZERO","ZERO","E","F"};
static wideregister q;
static cpuregister pc,x,y,u,s,dp,v,z;
static unsigned char InsCycles[2][25];
static unsigned int cc[8];
static unsigned int md[8];
static unsigned char *ureg8[8];
static unsigned char ccbits,mdbits;
static unsigned short *xfreg16[8];
static int CycleCounter=0;
static unsigned int SyncWaiting=0;
unsigned short temp16;
static signed short stemp16;
static signed char stemp8;
static unsigned int temp32;
static unsigned char temp8;
static unsigned char PendingInterupts=0;
static unsigned char IRQWaiter=0;
static unsigned char Source=0,Dest=0;
static unsigned char postbyte=0;
static short unsigned postword=0;
static signed char *spostbyte=(signed char *)&postbyte;
static signed short *spostword=(signed short *)&postword;
static char InInterupt=0;
//END Global variables for CPU Emulation-------------------
//Fuction Prototypes---------------------------------------
static unsigned short CalculateEA(unsigned char);
void InvalidInsHandler(void);
void DivbyZero(void);
void ErrorVector(void);
static void setcc (unsigned char);
static unsigned char getcc(void);
static void setmd (unsigned char);
static unsigned char getmd(void);
static void cpu_firq(void);
static void cpu_irq(void);
static void cpu_nmi(void);
unsigned int MemRead32(unsigned short);
void MemWrite32(unsigned int,unsigned short);
unsigned char GetSorceReg(unsigned char);
//unsigned char GetDestReg(unsigned char);
//END Fuction Prototypes-----------------------------------
void HD6309Reset(void)
{
char index;
for(index=0;index<=6;index++) //Set all register to 0 except V
*xfreg16[index] = 0;
for(index=0;index<=7;index++)
*ureg8[index]=0;
for(index=0;index<=7;index++)
cc[index]=0;
for(index=0;index<=7;index++)
md[index]=0;
mdbits=getmd();
dp.Reg=0;
cc[I]=1;
cc[F]=1;
SyncWaiting=0;
PC_REG=MemRead16(VRESET); //PC gets its reset vector
SetMapType(0); //shouldn't be here
return;
}
void HD6309Init(void)
{ //Call this first or RESET will core!
// reg pointers for TFR and EXG and LEA ops
xfreg16[0]=&D_REG;
xfreg16[1]=&X_REG;
xfreg16[2]=&Y_REG;
xfreg16[3]=&U_REG;
xfreg16[4]=&S_REG;
xfreg16[5]=&PC_REG;
xfreg16[6]=&W_REG;
xfreg16[7]=&V_REG;
ureg8[0]=(unsigned char*)&A_REG;
ureg8[1]=(unsigned char*)&B_REG;
ureg8[2]=(unsigned char*)&ccbits;
ureg8[3]=(unsigned char*)&dp.B.msb;
ureg8[4]=(unsigned char*)&O_REG;
ureg8[5]=(unsigned char*)&O_REG;
ureg8[6]=(unsigned char*)&E_REG;
ureg8[7]=(unsigned char*)&F_REG;
//This handles the disparity between 6309 and 6809 Instruction timing
InsCycles[0][M65]=6; //6-5
InsCycles[1][M65]=5;
InsCycles[0][M64]=6; //6-4
InsCycles[1][M64]=4;
InsCycles[0][M32]=3; //3-2
InsCycles[1][M32]=2;
InsCycles[0][M21]=2; //2-1
InsCycles[1][M21]=1;
InsCycles[0][M54]=5; //5-4
InsCycles[1][M54]=4;
InsCycles[0][M97]=9; //9-7
InsCycles[1][M97]=7;
InsCycles[0][M85]=8; //8-5
InsCycles[1][M85]=5;
InsCycles[0][M51]=5; //5-1
InsCycles[1][M51]=1;
InsCycles[0][M31]=3; //3-1
InsCycles[1][M31]=1;
InsCycles[0][M1110]=11; //11-10
InsCycles[1][M1110]=10;
InsCycles[0][M76]=7; //7-6
InsCycles[1][M76]=6;
InsCycles[0][M75]=7; //7-5
InsCycles[1][M75]=5;
InsCycles[0][M43]=4; //4-3
InsCycles[1][M43]=3;
InsCycles[0][M87]=8; //8-7
InsCycles[1][M87]=7;
InsCycles[0][M86]=8; //8-6
InsCycles[1][M86]=6;
InsCycles[0][M98]=9; //9-8
InsCycles[1][M98]=8;
InsCycles[0][M2726]=27; //27-26
InsCycles[1][M2726]=26;
InsCycles[0][M3635]=36; //36-25
InsCycles[1][M3635]=35;
InsCycles[0][M3029]=30; //30-29
InsCycles[1][M3029]=29;
InsCycles[0][M2827]=28; //28-27
InsCycles[1][M2827]=27;
InsCycles[0][M3726]=37; //37-26
InsCycles[1][M3726]=26;
InsCycles[0][M3130]=31; //31-30
InsCycles[1][M3130]=30;
cc[I]=1;
cc[F]=1;
return;
}
int HD6309Exec( int CycleFor)
{
static unsigned char opcode=0;
static unsigned char msn,lsn;
CycleCounter=0;
while (CycleCounter<CycleFor) {
if (PendingInterupts)
{
if (PendingInterupts & 4)
cpu_nmi();
if (PendingInterupts & 2)
cpu_firq();
if (PendingInterupts & 1)
{
if (IRQWaiter==0) // This is needed to fix a subtle timming problem
cpu_irq(); // It allows the CPU to see $FF03 bit 7 high before
else // The IRQ is asserted.
IRQWaiter-=1;
}
}
if (SyncWaiting==1) //Abort the run nothing happens asyncronously from the CPU
return(0);
switch (MemRead8(PC_REG++)){
case NEG_D: //0
temp16 = DPADDRESS(PC_REG++);
postbyte=MemRead8(temp16);
temp8=0-postbyte;
cc[C] =temp8>0;
cc[V] = (postbyte==0x80);
cc[N] = NTEST8(temp8);
cc[Z] = ZTEST(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case OIM_D://1 6309
postbyte=MemRead8(PC_REG++);
temp16 = DPADDRESS(PC_REG++);
postbyte|= MemRead8(temp16);
MemWrite8(postbyte,temp16);
cc[N] = NTEST8(postbyte);
cc[Z] = ZTEST(postbyte);
cc[V] = 0;
CycleCounter+=6;
break;
case AIM_D://2 Phase 2 6309
postbyte=MemRead8(PC_REG++);
temp16 = DPADDRESS(PC_REG++);
postbyte&= MemRead8(temp16);
MemWrite8(postbyte,temp16);
cc[N] = NTEST8(postbyte);
cc[Z] = ZTEST(postbyte);
cc[V] = 0;
CycleCounter+=6;
break;
case COM_D:
temp16 = DPADDRESS(PC_REG++);
temp8=MemRead8(temp16);
temp8=0xFF-temp8;
cc[Z] = ZTEST(temp8);
cc[N] = NTEST8(temp8);
cc[C] = 1;
cc[V] = 0;
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case LSR_D: //S2
temp16 = DPADDRESS(PC_REG++);
temp8 = MemRead8(temp16);
cc[C] = temp8 & 1;
temp8 = temp8 >>1;
cc[Z] = ZTEST(temp8);
cc[N] = 0;
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case EIM_D: //6309 Untested
postbyte=MemRead8(PC_REG++);
temp16 = DPADDRESS(PC_REG++);
postbyte^= MemRead8(temp16);
MemWrite8(postbyte,temp16);
cc[N] = NTEST8(postbyte);
cc[Z] = ZTEST(postbyte);
cc[V] = 0;
CycleCounter+=6;
break;
case ROR_D: //S2
temp16 = DPADDRESS(PC_REG++);
temp8=MemRead8(temp16);
postbyte= cc[C]<<7;
cc[C] = temp8 & 1;
temp8 = (temp8 >> 1)| postbyte;
cc[Z] = ZTEST(temp8);
cc[N] = NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case ASR_D: //7
temp16 = DPADDRESS(PC_REG++);
temp8=MemRead8(temp16);
cc[C] = temp8 & 1;
temp8 = (temp8 & 0x80) | (temp8 >>1);
cc[Z] = ZTEST(temp8);
cc[N] = NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case ASL_D: //8
temp16 = DPADDRESS(PC_REG++);
temp8=MemRead8(temp16);
cc[C] = (temp8 & 0x80) >>7;
cc[V] = cc[C] ^ ((temp8 & 0x40) >> 6);
temp8 = temp8 <<1;
cc[N] = NTEST8(temp8);
cc[Z] = ZTEST(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case ROL_D: //9
temp16 = DPADDRESS(PC_REG++);
temp8 = MemRead8(temp16);
postbyte=cc[C];
cc[C] =(temp8 & 0x80)>>7;
cc[V] = cc[C] ^ ((temp8 & 0x40) >>6);
temp8 = (temp8<<1) | postbyte;
cc[Z] = ZTEST(temp8);
cc[N] = NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case DEC_D: //A
temp16 = DPADDRESS(PC_REG++);
temp8 = MemRead8(temp16)-1;
cc[Z] = ZTEST(temp8);
cc[N] = NTEST8(temp8);
cc[V] = temp8==0x7F;
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case TIM_D: //B 6309 Untested wcreate
postbyte=MemRead8(PC_REG++);
temp8=MemRead8(DPADDRESS(PC_REG++));
postbyte&=temp8;
cc[N] = NTEST8(postbyte);
cc[Z] = ZTEST(postbyte);
cc[V] = 0;
CycleCounter+=6;
break;
case INC_D: //C
temp16=(DPADDRESS(PC_REG++));
temp8 = MemRead8(temp16)+1;
cc[Z] = ZTEST(temp8);
cc[V] = temp8==0x80;
cc[N] = NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case TST_D: //D
temp8 = MemRead8(DPADDRESS(PC_REG++));
cc[Z] = ZTEST(temp8);
cc[N] = NTEST8(temp8);
cc[V] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M64];
break;
case JMP_D: //E
PC_REG= ((dp.Reg |MemRead8(PC_REG)));
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case CLR_D: //F
MemWrite8(0,DPADDRESS(PC_REG++));
cc[Z] = 1;
cc[N] = 0;
cc[V] = 0;
cc[C] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M65];
break;
case Page2:
switch (MemRead8(PC_REG++))
{
case LBEQ_R: //1027
if (cc[Z])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBRN_R: //1021
PC_REG+=2;
CycleCounter+=5;
break;
case LBHI_R: //1022
if (!(cc[C] | cc[Z]))
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBLS_R: //1023
if (cc[C] | cc[Z])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBHS_R: //1024
if (!cc[C])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=6;
break;
case LBCS_R: //1025
if (cc[C])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBNE_R: //1026
if (!cc[Z])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBVC_R: //1028
if ( !cc[V])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBVS_R: //1029
if ( cc[V])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBPL_R: //102A
if (!cc[N])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBMI_R: //102B
if ( cc[N])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBGE_R: //102C
if (! (cc[N] ^ cc[V]))
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBLT_R: //102D
if ( cc[V] ^ cc[N])
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBGT_R: //102E
if ( !( cc[Z] | (cc[N]^cc[V] ) ))
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case LBLE_R: //102F
if ( cc[Z] | (cc[N]^cc[V]) )
{
*spostword=IMMADDRESS(PC_REG);
PC_REG+=*spostword;
CycleCounter+=1;
}
PC_REG+=2;
CycleCounter+=5;
break;
case ADDR: //1030 6309 CC? NITRO 8 bit code
temp8=MemRead8(PC_REG++);
Source= temp8>>4;
Dest=temp8 & 15;
if ( (Source>7) & (Dest>7) )
{
temp16= *ureg8[Source & 7] + *ureg8[Dest & 7];
cc[C] = (temp16 & 0x100)>>8;
cc[V] = OVERFLOW8(cc[C],*ureg8[Source & 7],*ureg8[Dest & 7],temp16);
*ureg8[Dest & 7]=(temp16 & 0xFF);
cc[N] = NTEST8(*ureg8[Dest & 7]);
cc[Z] = ZTEST(*ureg8[Dest & 7]);
}
else
{
temp32= *xfreg16[Source] + *xfreg16[Dest];
cc[C] = (temp32 & 0x10000)>>16;
cc[V] = OVERFLOW16(cc[C],*xfreg16[Source],*xfreg16[Dest],temp32);
*xfreg16[Dest]=(temp32 & 0xFFFF);
cc[N] = NTEST16(*xfreg16[Dest]);
cc[Z] = ZTEST(*xfreg16[Dest]);
}
cc[H] =0;
CycleCounter+=4;
break;
case ADCR: //1031 6309
WriteLog("Hitting UNEMULATED INS ADCR",TOCONS);
CycleCounter+=4;
break;
case SUBR: //1032 6309
temp8=MemRead8(PC_REG++);
Source=temp8>>4;
Dest=temp8 & 15;
switch (Dest)
{
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
if ((Source==12) | (Source==13))
postword=0;
else
postword=*xfreg16[Source];
temp32= *xfreg16[Dest] - postword;
cc[C] =(temp32 & 0x10000)>>16;
cc[V] =!!(((*xfreg16[Dest])^postword^temp32^(temp32>>1)) & 0x8000);
cc[N] =(temp32 & 0x8000)>>15;
cc[Z] = !temp32;
*xfreg16[Dest]=temp32;
break;
case 8:
case 9:
case 10:
case 11:
case 14:
case 15:
if (Source>=8)
{
temp8= *ureg8[Dest&7] - *ureg8[Source&7];
cc[C] = temp8 > *ureg8[Dest&7];
cc[V] = cc[C] ^ ( ((*ureg8[Dest&7])^temp8^(*ureg8[Source&7]))>>7);
cc[N] = temp8>>7;
cc[Z] = !temp8;
*ureg8[Dest&7]=temp8;
}
break;
}
CycleCounter+=4;
break;
case SBCR: //1033 6309
WriteLog("Hitting UNEMULATED INS SBCR",TOCONS);
CycleCounter+=4;
break;
case ANDR: //1034 6309 Untested wcreate
temp8=MemRead8(PC_REG++);
Source=temp8>>4;
Dest=temp8 & 15;
if ( (Source >=8) & (Dest >=8) )
{
(*ureg8[(Dest & 7)])&=(*ureg8[(Source & 7)]);
cc[N] = (*ureg8[(Dest & 7)]) >>7;
cc[Z] = !(*ureg8[(Dest & 7)]);
}
else
{
(*xfreg16[Dest])&=(*xfreg16[Source]);
cc[N] = (*xfreg16[Dest]) >>15;
cc[Z] = !(*xfreg16[Dest]);
}
cc[V] = 0;
CycleCounter+=4;
break;
case ORR: //1035 6309
temp8=MemRead8(PC_REG++);
Source=temp8>>4;
Dest=temp8 & 15;
if ( (Source >=8) & (Dest >=8) )
{
(*ureg8[(Dest & 7)])|=(*ureg8[(Source & 7)]);
cc[N] = (*ureg8[(Dest & 7)]) >>7;
cc[Z] = !(*ureg8[(Dest & 7)]);
}
else
{
(*xfreg16[Dest])|=(*xfreg16[Source]);
cc[N] = (*xfreg16[Dest]) >>15;
cc[Z] = !(*xfreg16[Dest]);
}
cc[V] = 0;
CycleCounter+=4;
break;
case EORR: //1036 6309
temp8=MemRead8(PC_REG++);
Source=temp8>>4;
Dest=temp8 & 15;
if ( (Source >=8) & (Dest >=8) )
{
(*ureg8[(Dest & 7)])^=(*ureg8[(Source & 7)]);
cc[N] = (*ureg8[(Dest & 7)]) >>7;
cc[Z] = !(*ureg8[(Dest & 7)]);
}
else
{
(*xfreg16[Dest])^=(*xfreg16[Source]);
cc[N] = (*xfreg16[Dest]) >>15;
cc[Z] = !(*xfreg16[Dest]);
}
cc[V] = 0;
CycleCounter+=4;
break;
case CMPR: //1037 6309
temp8=MemRead8(PC_REG++);
Source=temp8>>4;
Dest=temp8 & 15;
switch (Dest)
{
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
if ((Source==12) | (Source==13))
postword=0;
else
postword=*xfreg16[Source];
temp16= (*xfreg16[Dest]) - postword;
cc[C] = temp16 > *xfreg16[Dest];
cc[V] = cc[C]^(( (*xfreg16[Dest])^temp16^postword)>>15);
cc[N] = (temp16 >> 15);
cc[Z] = !temp16;
break;
case 8:
case 9:
case 10:
case 11:
case 14:
case 15:
if (Source>=8)
{
temp8= *ureg8[Dest&7] - *ureg8[Source&7];
cc[C] = temp8 > *ureg8[Dest&7];
cc[V] = cc[C] ^ ( ((*ureg8[Dest&7])^temp8^(*ureg8[Source&7]))>>7);
cc[N] = temp8>>7;
cc[Z] = !temp8;
}
break;
}
CycleCounter+=4;
break;
case PSHSW: //1038 DONE 6309
MemWrite8((F_REG),--S_REG);
MemWrite8((E_REG),--S_REG);
CycleCounter+=6;
break;
case PULSW: //1039 6309 Untested wcreate
E_REG=MemRead8( S_REG++);
F_REG=MemRead8( S_REG++);
CycleCounter+=6;
break;
case PSHUW: //103A 6309 Untested
MemWrite8((F_REG),--U_REG);
MemWrite8((E_REG),--U_REG);
CycleCounter+=6;
break;
case PULUW: //103B 6309 Untested
E_REG=MemRead8( U_REG++);
F_REG=MemRead8( U_REG++);
CycleCounter+=6;
break;
case SWI2_I: //103F
cc[E]=1;
MemWrite8( pc.B.lsb,--S_REG);
MemWrite8( pc.B.msb,--S_REG);
MemWrite8( u.B.lsb,--S_REG);
MemWrite8( u.B.msb,--S_REG);
MemWrite8( y.B.lsb,--S_REG);
MemWrite8( y.B.msb,--S_REG);
MemWrite8( x.B.lsb,--S_REG);
MemWrite8( x.B.msb,--S_REG);
MemWrite8( dp.B.msb,--S_REG);
if (md[NATIVE6309])
{
MemWrite8((F_REG),--S_REG);
MemWrite8((E_REG),--S_REG);
CycleCounter+=2;
}
MemWrite8(B_REG,--S_REG);
MemWrite8(A_REG,--S_REG);
MemWrite8(getcc(),--S_REG);
PC_REG=MemRead16(VSWI2);
CycleCounter+=20;
break;
case NEGD_I: //1040 Phase 5 6309
temp16= 0-D_REG;
cc[C] = temp16>0;
cc[V] = D_REG==0x8000;
cc[N] = NTEST16(temp16);
cc[Z] = ZTEST(temp16);
D_REG= temp16;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case COMD_I: //1043 6309
D_REG = 0xFFFF- D_REG;
cc[Z] = ZTEST(D_REG);
cc[N] = NTEST16(D_REG);
cc[C] = 1;
cc[V] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case LSRD_I: //1044 6309
cc[C] = D_REG & 1;
D_REG = D_REG>>1;
cc[Z] = ZTEST(D_REG);
cc[N] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case RORD_I: //1046 6309 Untested
postword=cc[C]<<15;
cc[C] = D_REG & 1;
D_REG = (D_REG>>1) | postword;
cc[Z] = ZTEST(D_REG);
cc[N] = NTEST16(D_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case ASRD_I: //1047 6309 Untested TESTED NITRO MULTIVUE
cc[C] = D_REG & 1;
D_REG = (D_REG & 0x8000) | (D_REG >> 1);
cc[Z] = ZTEST(D_REG);
cc[N] = NTEST16(D_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case ASLD_I: //1048 6309
cc[C] = D_REG >>15;
cc[V] = cc[C] ^((D_REG & 0x4000)>>14);
D_REG = D_REG<<1;
cc[N] = NTEST16(D_REG);
cc[Z] = ZTEST(D_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case ROLD_I: //1049 6309 Untested
postword=cc[C];
cc[C] = D_REG >>15;
cc[V] = cc[C] ^ ((D_REG & 0x4000)>>14);
D_REG= (D_REG<<1) | postword;
cc[Z] = ZTEST(D_REG);
cc[N] = NTEST16(D_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case DECD_I: //104A 6309
D_REG--;
cc[Z] = ZTEST(D_REG);
cc[V] = D_REG==0x7FFF;
cc[N] = NTEST16(D_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case INCD_I: //104C 6309
D_REG++;
cc[Z] = ZTEST(D_REG);
cc[V] = D_REG==0x8000;
cc[N] = NTEST16(D_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case TSTD_I: //104D 6309
cc[Z] = ZTEST(D_REG);
cc[N] = NTEST16(D_REG);
cc[V] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case CLRD_I: //104F 6309
D_REG= 0;
cc[C] = 0;
cc[V] = 0;
cc[N] = 0;
cc[Z] = 1;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case COMW_I: //1053 6309 Untested
W_REG= 0xFFFF- W_REG;
cc[Z] = ZTEST(W_REG);
cc[N] = NTEST16(W_REG);
cc[C] = 1;
cc[V] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case LSRW_I: //1054 6309 Untested
cc[C] = W_REG & 1;
W_REG= W_REG>>1;
cc[Z] = ZTEST(W_REG);
cc[N] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case RORW_I: //1056 6309 Untested
postword=cc[C]<<15;
cc[C] = W_REG & 1;
W_REG= (W_REG>>1) | postword;
cc[Z] = ZTEST(W_REG);
cc[N] = NTEST16(W_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case ROLW_I: //1059 6309
postword=cc[C];
cc[C] = W_REG >>15;
cc[V] = cc[C] ^ ((W_REG & 0x4000)>>14);
W_REG= ( W_REG<<1) | postword;
cc[Z] = ZTEST(W_REG);
cc[N] = NTEST16(W_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case DECW_I: //105A 6309
W_REG--;
cc[Z] = ZTEST(W_REG);
cc[V] = W_REG==0x7FFF;
cc[N] = NTEST16(W_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case INCW_I: //105C 6309
W_REG++;
cc[Z] = ZTEST(W_REG);
cc[V] = W_REG==0x8000;
cc[N] = NTEST16(W_REG);
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case TSTW_I: //105D Untested 6309 wcreate
cc[Z] = ZTEST(W_REG);
cc[N] = NTEST16(W_REG);
cc[V] = 0;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case CLRW_I: //105F 6309
W_REG = 0;
cc[C] = 0;
cc[V] = 0;
cc[N] = 0;
cc[Z] = 1;
CycleCounter+=InsCycles[md[NATIVE6309]][M32];
break;
case SUBW_M: //1080 6309 CHECK