Weird Settings for Clk Speed and CLK_PER_HALF_BIT

[ucycg]

  parameter SPI_MODE = 3;           // CPOL = 1, CPHA = 1
  parameter CLKS_PER_HALF_BIT = 4;  // 6.25 MHz
  parameter MAIN_CLK_DELAY = 2;     // 25 MHz
  parameter MAX_BYTES_PER_CS = 2;   // 2 bytes per chip select
  parameter CS_INACTIVE_CLKS = 10;  // Adds delay between bytes

Here the actual clockspeed to me seems 250 MHz instead of 25 MHz. Also with a CLKS_PER_HALF_BIT of 4 this turns out to be 250 MHz/8 = 31.25 MHz maybe a zero was deleted from the MAIN_CLK_DELAY? So you meat to set it to 20 ns? if you want on the other hands the values in the comment it would require

  parameter SPI_MODE = 3;           // CPOL = 1, CPHA = 1
  parameter CLKS_PER_HALF_BIT = 2;  // 6.25 MHz
  parameter MAIN_CLK_DELAY = 20;     // 25 MHz
  parameter MAX_BYTES_PER_CS = 2;   // 2 bytes per chip select
  parameter CS_INACTIVE_CLKS = 10;  // Adds delay between bytes