forked from ZipCPU/wb2axip
-
Notifications
You must be signed in to change notification settings - Fork 0
/
axivfifo.v
1404 lines (1262 loc) · 38.3 KB
/
axivfifo.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
////////////////////////////////////////////////////////////////////////////////
//
// Filename: axivfifo.v
// {{{
// Project: WB2AXIPSP: bus bridges and other odds and ends
//
// Purpose: A virtual FIFO, using an AXI based memory on the back end. Data
// written via the AXI stream interface is written to an external
// memory once enough is available to fill a burst. It's then copied from
// this external memory to a FIFO from which it can drive an outgoing
// stream.
//
// Registers:
// This core is simple--providing no control interface nor registers
// whereby it may be controlled. To place it in a particular region of
// SDRAM, limit the address width and fill the rest of the address with
// the region you want. Note: THIS CORE DEPENDS UPON ALIGNED MEMORY
// ACCESSES. Hence, it must be aligned to the memory to keep these
// accesses aligned.
//
// Performance goals:
// 100% throughput
// Stay off the bus until you can drive it hard
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2020-2021, Gisselquist Technology, LLC
// {{{
// This file is part of the WB2AXIP project.
//
// The WB2AXIP project contains free software and gateware, licensed under the
// Apache License, Version 2.0 (the "License"). You may not use this project,
// or this file, except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
////////////////////////////////////////////////////////////////////////////////
//
`default_nettype none
//
// `define AXI3
// }}}
module axivfifo #(
// {{{
parameter C_AXI_ID_WIDTH = 1,
parameter C_AXI_ADDR_WIDTH = 32,
parameter C_AXI_DATA_WIDTH = 32,
//
// This core requires that the stream data width be identical
// to the bus data width. Use an upstream core if you need to
// pack a smaller width into your bus's width, or a downstream
// core if you need to unpack it.
localparam C_AXIS_DATA_WIDTH = C_AXI_DATA_WIDTH,
//
// LGMAXBURST determines the size of the maximum AXI burst.
// In AXI4, the maximum burst size is 256 beats the log_2()
// of which is 8. In AXI3, it's a 16 beat burst of which the
// log_2() is 4. Smaller numbers are also permissible here,
// although not verified. I expect problems if LGMAXBURST is
// ever set to zero (no bursting). An upgrade should fix that.
// Lower LGMAXBURST values will decrease the latency in this
// core while possibly causing throughput to be decreased
// (in the rest of the system--this core can handle 100%
// throughput either way.)
//
// Beware of the AXI requirement that bursts cannot cross
// 4kB boundaries. If your bus is larger than 128 bits wide,
// you'll need to lower this maximum burst size to meet that
// requirement.
`ifdef AXI3
parameter LGMAXBURST=4, // 16 beats max
`else
parameter LGMAXBURST=8, // 256 beats
`endif
//
// LGFIFO: This is the (log-based-2) size of the internal FIFO.
// Hence if LGFIFO=8, the internal FIFO will have 256 elements
// (words) in it. High throughput transfers are accomplished
// by first storing data into a FIFO, then once a full burst
// size is available bursting that data over the bus. In
// order to be able to keep receiving data while bursting it
// out, the FIFO size must be at least twice the size of the
// maximum burst size--that is LGFIFO must be at least one more
// than LGMAXBURST. Larger sizes are possible as well.
parameter LGFIFO = LGMAXBURST+1, // 512 element FIFO
//
// AXI uses ID's to transfer information. This core rather
// ignores them. Instead, it uses a constant ID for all
// transfers. The following two parameters control that ID.
parameter [C_AXI_ID_WIDTH-1:0] AXI_READ_ID = 0,
parameter [C_AXI_ID_WIDTH-1:0] AXI_WRITE_ID = 0,
//
localparam ADDRLSB= $clog2(C_AXI_DATA_WIDTH)-3
// }}}
) (
// {{{
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
//
// The AXI4-stream interface
// {{{
// This core does not support TLAST, TKEEP, or TSTRB. If you
// want to support these extra values, expand the width of
// TDATA, and unpack them on the output of the FIFO.
//
// The incoming stream
input wire S_AXIS_TVALID,
output wire S_AXIS_TREADY,
input wire [C_AXIS_DATA_WIDTH-1:0] S_AXIS_TDATA,
//
// The outgoing stream
output wire M_AXIS_TVALID,
input wire M_AXIS_TREADY,
output reg [C_AXIS_DATA_WIDTH-1:0] M_AXIS_TDATA,
// }}}
//
// The AXI Master (DMA) interface
// {{{
// First to write data to the (external) AXI buffer
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
`ifdef AXI3
output wire [3:0] M_AXI_AWLEN,
`else
output wire [7:0] M_AXI_AWLEN,
`endif
output wire [2:0] M_AXI_AWSIZE,
output wire [1:0] M_AXI_AWBURST,
`ifdef AXI3
output wire [1:0] M_AXI_AWLOCK,
`else
output wire M_AXI_AWLOCK,
`endif
output wire [3:0] M_AXI_AWCACHE,
output wire [2:0] M_AXI_AWPROT,
output wire [3:0] M_AXI_AWQOS,
//
//
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
`ifdef AXI3
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
`endif
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
//
//
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [1:0] M_AXI_BRESP,
//
// Then the read interface to read the data back
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
`ifdef AXI3
output wire [3:0] M_AXI_ARLEN,
`else
output wire [7:0] M_AXI_ARLEN,
`endif
output wire [2:0] M_AXI_ARSIZE,
output wire [1:0] M_AXI_ARBURST,
`ifdef AXI3
output wire [1:0] M_AXI_ARLOCK,
`else
output wire M_AXI_ARLOCK,
`endif
output wire [3:0] M_AXI_ARCACHE,
output wire [2:0] M_AXI_ARPROT,
output wire [3:0] M_AXI_ARQOS,
//
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire M_AXI_RLAST,
input wire [1:0] M_AXI_RRESP,
// }}}
//
// {{{
// Request a soft-reset: reset the FIFO without resetting th bus
input wire i_reset,
// o_err is a hard error. If ever true, the core will come
// to a hard stop.
output reg o_err,
// o_overflow is an indication of data changing before it is
// accepted.
output reg o_overflow,
// o_mm2s_full is a reference to the last FIFO in our
// processing pipeline. It's true if a burst of (1<<LGMAXBURST)
// words of (1<<ADDRLSB) bytes may be read from the downstream
// FIFO without waiting on the external memory.
output reg o_mm2s_full,
// o_empty is true if nothing is in the core.
output reg o_empty,
// o_fill counts the number of items in the core. Just because
// the number of items is non-zero, however, doesn't mean you
// can read them out. In general, you will need to write at
// least a full (1<<LGMAXBURST) words to the core, those will
// need to be written to memory, read from memory, and then
// used to fill the downstream FIFO before you can read. This
// number is just available for your informational use.
output reg [C_AXI_ADDR_WIDTH-ADDRLSB:0] o_fill
// }}}
// }}}
);
// Register and signal definitions
// {{{
// The number of beats in this maximum burst size is automatically
// determined from LGMAXBURST, and so its forced to be a power of
// two this way.
localparam MAXBURST=(1<<LGMAXBURST);
localparam BURSTAW = C_AXI_ADDR_WIDTH-LGMAXBURST-ADDRLSB;
reg soft_reset, vfifo_empty, vfifo_full;
wire reset_fifo;
reg [C_AXI_ADDR_WIDTH-ADDRLSB:0] vfifo_fill;
reg [BURSTAW:0] mem_data_available_w,
writes_outstanding;
reg [BURSTAW:0] mem_space_available_w,
reads_outstanding;
reg s_last_stalled;
reg [C_AXI_DATA_WIDTH-1:0] s_last_tdata;
wire read_from_fifo, ififo_full, ififo_empty;
wire [C_AXI_DATA_WIDTH-1:0] ififo_data;
wire [LGFIFO:0] ififo_fill;
reg start_write, phantom_write,
axi_awvalid, axi_wvalid, axi_wlast,
writes_idle;
reg [C_AXI_ADDR_WIDTH-1:0] axi_awaddr;
reg [LGMAXBURST:0] writes_pending;
reg start_read, phantom_read, reads_idle,
axi_arvalid;
reg [C_AXI_ADDR_WIDTH-1:0] axi_araddr;
reg skd_valid;
reg [C_AXI_DATA_WIDTH-1:0] skd_data;
reg [LGFIFO:0] ofifo_space_available;
wire write_to_fifo, ofifo_empty, ofifo_full;
wire [LGFIFO:0] ofifo_fill;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Global FIFO signal handling
// {{{
////////////////////////////////////////////////////////////////////////
//
//
//
// A soft reset
// {{{
// This is how we reset the FIFO without resetting the rest of the AXI
// bus. On a reset request, we raise the soft_reset flag and reset all
// of our internal FIFOs. We also stop issuing bus commands. Once all
// outstanding bus commands come to a halt, then we release from reset
// and start operating as a FIFO.
initial soft_reset = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
soft_reset <= 0;
else if (i_reset)
soft_reset <= 1;
else if (writes_idle && reads_idle)
soft_reset <= 0;
assign reset_fifo = soft_reset || !S_AXI_ARESETN;
// }}}
//
// Calculating the fill of the virtual FIFO, and the associated
// full/empty flags that go with it
// {{{
initial vfifo_fill = 0;
initial vfifo_empty = 1;
initial vfifo_full = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || soft_reset)
begin
vfifo_fill <= 0;
vfifo_empty <= 1;
vfifo_full <= 0;
end else case({ S_AXIS_TVALID && S_AXIS_TREADY,
M_AXIS_TVALID && M_AXIS_TREADY })
2'b10: begin
vfifo_fill <= vfifo_fill + 1;
vfifo_empty <= 0;
vfifo_full <= (&vfifo_fill[C_AXI_ADDR_WIDTH-ADDRLSB-1:0]);
end
2'b01: begin
vfifo_fill <= vfifo_fill - 1;
vfifo_full <= 0;
vfifo_empty<= (vfifo_fill <= 1);
end
default: begin end
endcase
always @(*)
o_fill = vfifo_fill;
always @(*)
o_empty = vfifo_empty;
// }}}
// Determining when the write half is idle
// {{{
// This is required to know when to come out of soft reset.
//
// The first step is to count the number of bursts that remain
// outstanding
initial writes_outstanding = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
writes_outstanding <= 0;
else case({ phantom_write,M_AXI_BVALID && M_AXI_BREADY})
2'b01: writes_outstanding <= writes_outstanding - 1;
2'b10: writes_outstanding <= writes_outstanding + 1;
default: begin end
endcase
// The second step is to use this counter to determine if we are idle.
// If WVALID is ever high, or start_write goes high, then we are
// obviously not idle. Otherwise, we become idle when the number of
// writes outstanding transitions to (or equals) zero.
initial writes_idle = 1;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
writes_idle <= 1;
else if (start_write || M_AXI_WVALID)
writes_idle <= 0;
else
writes_idle <= (writes_outstanding
== ((M_AXI_BVALID && M_AXI_BREADY) ? 1:0));
// }}}
// Count how much space is used in the memory device
// {{{
// Well, obviously, we can't fill our memory device or we have problems.
// To make sure we don't overflow, we count memory usage here. We'll
// count memory usage in units of bursts of (1<<LGMAXBURST) words of
// (1<<ADDRLSB) bytes each. So ... here we count the amount of device
// memory that hasn't (yet) been committed. This is different from the
// memory used (which we don't calculate), or the memory which may yet
// be read--which we'll calculate in a moment.
initial mem_space_available_w = (1<<BURSTAW);
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || soft_reset)
mem_space_available_w <= (1<<BURSTAW);
else case({ phantom_write,M_AXI_RVALID && M_AXI_RREADY && M_AXI_RLAST })
2'b01: mem_space_available_w <= mem_space_available_w + 1;
2'b10: mem_space_available_w <= mem_space_available_w - 1;
default: begin end
endcase
// }}}
// Determining when the read half is idle
// {{{
// Count the number of read bursts that we've committed to. This
// includes bursts that have ARVALID but haven't been accepted, as well
// as any the downstream device will yet return an RLAST for.
initial reads_outstanding = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
reads_outstanding <= 0;
else case({ phantom_read,M_AXI_RVALID && M_AXI_RREADY && M_AXI_RLAST})
2'b01: reads_outstanding <= reads_outstanding - 1;
2'b10: reads_outstanding <= reads_outstanding + 1;
default: begin end
endcase
// Now, using the reads_outstanding counter, we can check whether or not
// we are idle (and can exit a reset) of if instead there are more
// bursts outstanding to wait for.
//
// By registering this counter, we can keep the soft_reset release
// simpler. At least this way, it doesn't need to check two counters
// for zero.
initial reads_idle = 1;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
reads_idle <= 1;
else if (start_read || M_AXI_ARVALID)
reads_idle <= 0;
else
reads_idle <= (reads_outstanding
== ((M_AXI_RVALID && M_AXI_RREADY && M_AXI_RLAST) ? 1:0));
// }}}
// Count how much data is in the memory device that we can read out
// {{{
// In AXI, after you issue a write, you can't depend upon that data
// being present on the device and available for a read until the
// associated BVALID is returned. Therefore we don't count any memory
// as available to be read until BVALID comes back. Once a read
// command is issued, the memory is again no longer available to be
// read. Note also that we are counting bursts here. A second
// conversion below converts this count to bytes.
initial mem_data_available_w = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || soft_reset)
mem_data_available_w <= 0;
else case({ M_AXI_BVALID, phantom_read })
2'b10: mem_data_available_w <= mem_data_available_w + 1;
2'b01: mem_data_available_w <= mem_data_available_w - 1;
default: begin end
endcase
// }}}
//
// Error detection
// {{{
initial o_err = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
o_err <= 1'b0;
else begin
if (M_AXI_BVALID && M_AXI_BRESP[1])
o_err <= 1'b1;
if (M_AXI_RVALID && M_AXI_RRESP[1])
o_err <= 1'b1;
end
// }}}
//
// Incoming stream overflow detection
// {{{
// The overflow flag is set if ever an incoming value violates the
// stream protocol and changes while stalled. Internally, however,
// the overflow flag is ignored. It's provided for your information.
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
s_last_stalled <= 0;
else
s_last_stalled <= S_AXIS_TVALID && !S_AXIS_TREADY;
always @(posedge S_AXI_ACLK)
if (S_AXIS_TVALID)
s_last_tdata <= S_AXIS_TDATA;
initial o_overflow = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || soft_reset)
o_overflow <= 0;
else if (s_last_stalled)
begin
if (!S_AXIS_TVALID)
o_overflow <= 1;
if (S_AXIS_TDATA != s_last_tdata)
o_overflow <= 1;
end
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Incoming FIFO
// {{{
// Incoming data stream info the FIFO
//
////////////////////////////////////////////////////////////////////////
//
//
assign S_AXIS_TREADY = !reset_fifo && !ififo_full && !vfifo_full;
assign read_from_fifo= (!skd_valid || (M_AXI_WVALID && M_AXI_WREADY));
sfifo #(.BW(C_AXIS_DATA_WIDTH), .LGFLEN(LGFIFO))
ififo(S_AXI_ACLK, reset_fifo,
S_AXIS_TVALID && S_AXIS_TREADY,
S_AXIS_TDATA, ififo_full, ififo_fill,
read_from_fifo, ififo_data, ififo_empty);
//
// We need a quick 1-element buffer here in order to keep the soft
// reset, which resets the FIFO pointer, from adjusting any FIFO data.
// {{{
// Here's the rule: we need to fill the buffer before it ever gets
// used. Then, once used, it should be able to maintain 100%
// throughput.
initial skd_valid = 0;
always @(posedge S_AXI_ACLK)
if (reset_fifo)
skd_valid <= 0;
else if (!ififo_empty)
skd_valid <= 1;
else if (M_AXI_WVALID && M_AXI_WREADY)
skd_valid <= 0;
always @(posedge S_AXI_ACLK)
if (!M_AXI_WVALID || M_AXI_WREADY)
begin
if (!skd_valid || M_AXI_WREADY)
skd_data <= ififo_data;
end
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// AXI write processing
// {{{
// Write data from our FIFO onto the bus
//
////////////////////////////////////////////////////////////////////////
//
//
// start_write: determining when to issue a write burst
// {{{
always @(*)
begin
start_write = 0;
if (ififo_fill >= (1<<LGMAXBURST))
start_write = 1;
if (vfifo_full || soft_reset || phantom_write)
start_write = 0;
if (mem_space_available_w == 0)
start_write = 0;
if (M_AXI_WVALID && (!M_AXI_WREADY || !M_AXI_WLAST))
start_write = 0;
if (M_AXI_AWVALID && !M_AXI_AWREADY)
start_write = 0;
if (o_err)
start_write = 0;
end
// }}}
// Register the start write signal into AWVALID and phantom write
// {{{
// phantom_write contains the start signal, but immediately clears
// on the next clock cycle. This allows us some time to calculate
// the data for the next burst which and if AWVALID remains high and
// not yet accepted.
initial phantom_write = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
phantom_write <= 0;
else
phantom_write <= start_write;
// Set AWVALID to start_write if every the channel isn't stalled.
// Incidentally, start_write is guaranteed to be zero if the channel
// is stalled, since that signal is used by other things as well.
initial axi_awvalid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axi_awvalid <= 0;
else if (!M_AXI_AWVALID || M_AXI_AWREADY)
axi_awvalid <= start_write;
// }}}
// Write address
// {{{
// We insist on alignment. On every accepted burst, we step forward by
// one burst length. On reset, we reset the address at our first
// opportunity.
initial axi_awaddr = 0;
always @(posedge S_AXI_ACLK)
begin
if (M_AXI_AWVALID && M_AXI_AWREADY)
axi_awaddr[C_AXI_ADDR_WIDTH-1:LGMAXBURST+ADDRLSB]
<= axi_awaddr[C_AXI_ADDR_WIDTH-1:LGMAXBURST+ADDRLSB] +1;
if ((!M_AXI_AWVALID || M_AXI_AWREADY) && soft_reset)
axi_awaddr <= 0;
if (!S_AXI_ARESETN)
axi_awaddr <= 0;
axi_awaddr[LGMAXBURST+ADDRLSB-1:0] <= 0;
end
// }}}
// Write data channel valid
// {{{
initial axi_wvalid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axi_wvalid <= 0;
else if (start_write)
axi_wvalid <= 1;
else if (!M_AXI_WVALID || M_AXI_WREADY)
axi_wvalid <= M_AXI_WVALID && !M_AXI_WLAST;
// }}}
// WLAST generation
// {{{
// On the beginning of any burst, start a counter of the number of items
// in it. Once the counter gets to 1, set WLAST.
initial writes_pending = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
writes_pending <= 0;
else if (start_write)
writes_pending <= MAXBURST;
else if (M_AXI_WVALID && M_AXI_WREADY)
writes_pending <= writes_pending -1;
always @(posedge S_AXI_ACLK)
if (start_write)
axi_wlast <= (LGMAXBURST == 0);
else if (!M_AXI_WVALID || M_AXI_WREADY)
axi_wlast <= (writes_pending == 1 + (M_AXI_WVALID ? 1:0));
// }}}
// Bus assignments based upon the above
// {{{
assign M_AXI_AWVALID = axi_awvalid;
assign M_AXI_AWID = AXI_WRITE_ID;
assign M_AXI_AWADDR = axi_awaddr;
assign M_AXI_AWLEN = MAXBURST-1;
assign M_AXI_AWSIZE = ADDRLSB[2:0];
assign M_AXI_AWBURST = 2'b01;
assign M_AXI_AWLOCK = 0;
assign M_AXI_AWCACHE = 0;
assign M_AXI_AWPROT = 0;
assign M_AXI_AWQOS = 0;
assign M_AXI_WVALID = axi_wvalid;
assign M_AXI_WDATA = skd_data;
`ifdef AXI3
assign M_AXI_WID = AXI_WRITE_ID;
`endif
assign M_AXI_WLAST = axi_wlast;
assign M_AXI_WSTRB = -1;
assign M_AXI_BREADY = 1;
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// AXI read processing
// {{{
// Read data into our FIFO
//
////////////////////////////////////////////////////////////////////////
//
//
// How much FIFO space is available?
// {{{
// One we issue a read command, the FIFO space isn't available any more.
// That way we can determine when a second read can be issued--even
// before the first has returned--while also guaranteeing that there's
// always room in the outgoing FIFO for anything that might return.
// Remember: NEVER generate backpressure in a bus master
initial ofifo_space_available = (1<<LGFIFO);
always @(posedge S_AXI_ACLK)
if (reset_fifo)
ofifo_space_available <= (1<<LGFIFO);
else case({phantom_read, M_AXIS_TVALID && M_AXIS_TREADY})
2'b10: ofifo_space_available <= ofifo_space_available - MAXBURST;
2'b01: ofifo_space_available <= ofifo_space_available + 1;
2'b11: ofifo_space_available <= ofifo_space_available - MAXBURST + 1;
default: begin end
endcase
// }}}
// Determine when to start a next read-from-memory-to-FIFO burst
// {{{
always @(*)
begin
start_read = 1;
// We can't read yet if we don't have space available.
// Note the comparison is carefully chosen to make certain
// it doesn't use all ofifo_space_available bits, but rather
// only the number of bits between LGFIFO and
// LGMAXBURST--nominally a single bit.
if (ofifo_space_available < MAXBURST) // FIFO space ?
start_read = 0;
// If there's no memory available for us to read from, then
// we can't start a read yet.
if (!M_AXI_BVALID && mem_data_available_w == 0)
start_read = 0;
// Don't start anything while waiting on a reset. Likewise,
// insist on a minimum one clock between read burst issuances.
if (soft_reset || phantom_read)
start_read = 0;
// We can't start a read request if the AR* channel is stalled
if (M_AXI_ARVALID && !M_AXI_ARREADY)
start_read = 0;
// Following a bus error, we come to a complete halt. Such a
// bus error is an indication that something *SERIOUSLY* went
// wrong--perhaps we aren't accessing the memory we are supposed
// to. To prevent damage to external devices, we disable
// ourselves entirely. There is no fall back. We only
// restart on a full bus restart.
if (o_err)
start_read = 0;
end
// }}}
// Set phantom_read and ARVALID
// {{{
initial phantom_read = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
phantom_read <= 0;
else
phantom_read <= start_read;
initial axi_arvalid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axi_arvalid <= 0;
else if (!M_AXI_ARVALID || M_AXI_ARREADY)
axi_arvalid <= start_read;
// }}}
// Calculate the next ARADDR
// {{{
initial axi_araddr = 0;
always @(posedge S_AXI_ACLK)
begin
if (M_AXI_ARVALID && M_AXI_ARREADY)
axi_araddr[C_AXI_ADDR_WIDTH-1:LGMAXBURST+ADDRLSB]
<= axi_araddr[C_AXI_ADDR_WIDTH-1:LGMAXBURST+ADDRLSB]+ 1;
if ((!M_AXI_ARVALID || M_AXI_ARREADY) && soft_reset)
axi_araddr <= 0;
if (!S_AXI_ARESETN)
axi_araddr <= 0;
axi_araddr[LGMAXBURST+ADDRLSB-1:0] <= 0;
end
// }}}
// Assign values to our bus wires
// {{{
assign M_AXI_ARVALID = axi_arvalid;
assign M_AXI_ARID = AXI_READ_ID;
assign M_AXI_ARADDR = axi_araddr;
assign M_AXI_ARLEN = MAXBURST-1;
assign M_AXI_ARSIZE = ADDRLSB[2:0];
assign M_AXI_ARBURST = 2'b01;
assign M_AXI_ARLOCK = 0;
assign M_AXI_ARCACHE = 0;
assign M_AXI_ARPROT = 0;
assign M_AXI_ARQOS = 0;
assign M_AXI_RREADY = 1;
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Outgoing AXI stream processing
// {{{
// Send data out from the MM2S FIFO
//
////////////////////////////////////////////////////////////////////////
//
//
// We basically just stuff the data read from memory back into our
// outgoing FIFO here. The logic is quite straightforward.
assign write_to_fifo = M_AXI_RVALID && M_AXI_RREADY;
assign M_AXIS_TVALID = !ofifo_empty;
sfifo #(.BW(C_AXIS_DATA_WIDTH), .LGFLEN(LGFIFO))
ofifo(S_AXI_ACLK, reset_fifo,
write_to_fifo,
M_AXI_RDATA, ofifo_full, ofifo_fill,
M_AXIS_TVALID && M_AXIS_TREADY, M_AXIS_TDATA, ofifo_empty);
always @(*)
o_mm2s_full = |ofifo_fill[LGFIFO:LGMAXBURST];
// }}}
// Keep Verilator happy
// {{{
// Verilator lint_off UNUSED
wire unused;
assign unused = &{ 1'b0, M_AXI_BID, M_AXI_RID,
M_AXI_BRESP[0], M_AXI_RRESP[0],
ififo_empty, ofifo_full, ofifo_fill
// fifo_full, fifo_fill, fifo_empty,
};
// Verilator lint_on UNUSED
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal property section
// {{{
//
// The following are a subset of the formal properties used to verify this
// core. The full set of formal properties, together with the formal
// property set itself, are available for purchase.
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
// FAXI_DEPTH controls the width of the counters in the bus property
// interface file. In order to support bursts of length 8 (or more),
// there's a minimum of 9. Otherwise, we'll just set this to the width
// of the AXI address bus.
localparam FAXI_DEPTH = (C_AXI_ADDR_WIDTH > 8)
? (C_AXI_ADDR_WIDTH+1) : 9;
reg f_past_valid;
initial f_past_valid = 0;
always @(posedge S_AXI_ACLK)
f_past_valid <= 1;
//
// Wires necessary for interacting with the formal property file
// {{{
// ...
// }}}
// Other registers to keep simplify keeping track of our progress
// {{{
reg [C_AXI_ADDR_WIDTH-1:0] faxi_rd_cknext, faxi_wr_cknext,
f_read_beat_addr, f_write_beat_addr,
faxi_read_beat_addr;
reg [C_AXI_ADDR_WIDTH-1:0] f_read_ckbeat_addr;
reg [FAXI_DEPTH-1:0] f_rd_bursts_after_check;
reg [C_AXI_ADDR_WIDTH:0] f_vfill;
reg [C_AXI_ADDR_WIDTH:0] f_space_available,
f_data_available;
reg [C_AXI_ADDR_WIDTH-1:0] f_read_checksum;
reg [C_AXI_ADDR_WIDTH:0] mem_space_available, mem_data_available;
// }}}
////////////////////////////////////////////////////////////////////////
//
// The main AXI data interface bus property check
//
////////////////////////////////////////////////////////////////////////
//
//
// The number of beats in the maximum burst size is
// automatically determined from LGMAXBURST, and so its
// forced to be a power of two this way.
localparam MAXBURST=(1<<LGMAXBURST);
faxi_master #(
// {{{
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.OPT_MAXBURST(MAXBURST-1),
.OPT_NARROW_BURST(1'b0),
.OPT_ASYNC_RESET(1'b0), // We don't use asynchronous resets
.OPT_EXCLUSIVE(1'b0), // We don't use the LOCK signal
.F_OPT_ASSUME_RESET(1'b1), // We aren't generating the reset
.F_OPT_NO_RESET(1'b1),
.F_LGDEPTH(FAXI_DEPTH) // Width of the counters
// }}}
) faxi(
// {{{
.i_clk(S_AXI_ACLK), .i_axi_reset_n(S_AXI_ARESETN),
// Write signals
// {{{
.i_axi_awvalid(M_AXI_AWVALID),
.i_axi_awready(M_AXI_AWREADY),
.i_axi_awid( M_AXI_AWID),
.i_axi_awaddr( M_AXI_AWADDR),
.i_axi_awlen( M_AXI_AWLEN),
.i_axi_awsize( M_AXI_AWSIZE),
.i_axi_awburst(M_AXI_AWBURST),
.i_axi_awlock( M_AXI_AWLOCK),
.i_axi_awcache(M_AXI_AWCACHE),
.i_axi_awprot( M_AXI_AWPROT),
.i_axi_awqos( M_AXI_AWQOS),
//
.i_axi_wvalid(M_AXI_WVALID),
.i_axi_wready(M_AXI_WREADY),
.i_axi_wdata( M_AXI_WDATA),
.i_axi_wstrb( M_AXI_WSTRB),
.i_axi_wlast( M_AXI_WLAST),
//
.i_axi_bvalid(M_AXI_BVALID),
.i_axi_bready(M_AXI_BREADY),
.i_axi_bid( M_AXI_BID),
.i_axi_bresp( M_AXI_BRESP),
// }}}
// Read signals
// {{{
.i_axi_arvalid(M_AXI_ARVALID),
.i_axi_arready(M_AXI_ARREADY),
.i_axi_arid( M_AXI_ARID),
.i_axi_araddr( M_AXI_ARADDR),
.i_axi_arlen( M_AXI_ARLEN),
.i_axi_arsize( M_AXI_ARSIZE),
.i_axi_arburst(M_AXI_ARBURST),
.i_axi_arlock( M_AXI_ARLOCK),
.i_axi_arcache(M_AXI_ARCACHE),
.i_axi_arprot( M_AXI_ARPROT),
.i_axi_arqos( M_AXI_ARQOS),
//
//
.i_axi_rvalid(M_AXI_RVALID),
.i_axi_rready(M_AXI_RREADY),
.i_axi_rid( M_AXI_RID),
.i_axi_rdata( M_AXI_RDATA),
.i_axi_rlast( M_AXI_RLAST),
.i_axi_rresp( M_AXI_RRESP),
// }}}
// Induction signals
// {{{
// ...
// }}}
// }}}
);
// Some quick sanity checks
// {{{
always @(*)
begin
//
// ...
//
end
// }}}
////////////////////////////////////////////////////////////////////////
//
// Write sanity checking
// {{{
always @(*)
mem_space_available = { mem_space_available_w,
{(LGMAXBURST+ADDRLSB){1'b0} } };
// Let's calculate the address of each write beat
// {{{
initial f_write_beat_addr = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
f_write_beat_addr <= 0;
else if ((!M_AXI_WVALID || (M_AXI_WREADY && M_AXI_WLAST)) && soft_reset)
f_write_beat_addr <= 0;
else if (M_AXI_WVALID && M_AXI_WREADY)
f_write_beat_addr <= f_write_beat_addr + (1<<ADDRLSB);
// }}}
//
// ...
//
// Verify during any write burst that all the burst parameters are
// correct
// {{{
// ...
// }}}
always @(*)
if (M_AXI_AWVALID)
begin
assert(writes_pending == (1<<LGMAXBURST));
// ...
end else
// ...
always @(*)
assert(M_AXI_WVALID == (writes_pending != 0));
//
// ...
//
// Check the writes-idle signal
// {{{
// ...
// }}}
// }}}