forked from ZipCPU/wb2axip
-
Notifications
You must be signed in to change notification settings - Fork 0
/
demofull.v
1274 lines (1175 loc) · 32.2 KB
/
demofull.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
////////////////////////////////////////////////////////////////////////////////
//
// Filename: demofull.v
// {{{
// Project: WB2AXIPSP: bus bridges and other odds and ends
//
// Purpose: Demonstrate a formally verified AXI4 core with a (basic)
// interface. This interface is explained below.
//
// Performance: This core has been designed for a total throughput of one beat
// per clock cycle. Both read and write channels can achieve
// this. The write channel will also introduce two clocks of latency,
// assuming no other latency from the master. This means it will take
// a minimum of 3+AWLEN clock cycles per transaction of (1+AWLEN) beats,
// including both address and acknowledgment cycles. The read channel
// will introduce a single clock of latency, requiring 2+ARLEN cycles
// per transaction of 1+ARLEN beats.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2019-2021, Gisselquist Technology, LLC
// {{{
// This file is part of the WB2AXIP project.
//
// The WB2AXIP project contains free software and gateware, licensed under the
// Apache License, Version 2.0 (the "License"). You may not use this project,
// or this file, except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations
// under the License.
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
// }}}
module demofull #(
// {{{
parameter integer C_S_AXI_ID_WIDTH = 2,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 6,
parameter [0:0] OPT_LOCK = 1'b0,
parameter [0:0] OPT_LOCKID = 1'b1,
parameter [0:0] OPT_LOWPOWER = 1'b0,
// Some useful short-hand definitions
localparam LSB = $clog2(C_S_AXI_DATA_WIDTH)-3
// }}}
) (
// {{{
// User ports
// {{{
// A very basic protocol-independent peripheral interface
// 1. A value will be written any time o_we is true
// 2. A value will be read any time o_rd is true
// 3. Such a slave might just as easily be written as:
//
// always @(posedge S_AXI_ACLK)
// if (o_we)
// begin
// for(k=0; k<C_S_AXI_DATA_WIDTH/8; k=k+1)
// begin
// if (o_wstrb[k])
// mem[o_waddr[AW-1:LSB]][k*8+:8] <= o_wdata[k*8+:8]
// end
// end
//
// always @(posedge S_AXI_ACLK)
// if (o_rd)
// i_rdata <= mem[o_raddr[AW-1:LSB]];
//
// 4. The rule on the input is that i_rdata must be registered,
// and that it must only change if o_rd is true. Violating
// this rule will cause this core to violate the AXI
// protocol standard, as this value is not registered within
// this core
output reg o_we,
output reg [C_S_AXI_ADDR_WIDTH-LSB-1:0] o_waddr,
output reg [C_S_AXI_DATA_WIDTH-1:0] o_wdata,
output reg [C_S_AXI_DATA_WIDTH/8-1:0] o_wstrb,
//
output reg o_rd,
output reg [C_S_AXI_ADDR_WIDTH-LSB-1:0] o_raddr,
input wire [C_S_AXI_DATA_WIDTH-1:0] i_rdata,
//
// User ports ends
// }}}
// Do not modify the ports beyond this line
// AXI signals
// {{{
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address channel
// {{{
// Write Address ID
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID,
// Write address
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Burst length. The burst length gives the exact number of
// transfers in a burst
input wire [7 : 0] S_AXI_AWLEN,
// Burst size. This signal indicates the size of each transfer
// in the burst
input wire [2 : 0] S_AXI_AWSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the burst
// is calculated.
input wire [1 : 0] S_AXI_AWBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_AWLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_AWCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Quality of Service, QoS identifier sent for each
// write transaction.
input wire [3 : 0] S_AXI_AWQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
// Write address valid. This signal indicates that
// the channel is signaling valid write address and
// control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_AWREADY,
// }}}
// Write data channel
// {{{
// Write Data
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte
// lanes hold valid data. There is one write strobe
// bit for each eight bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write last. This signal indicates the last transfer
// in a write burst.
input wire S_AXI_WLAST,
// Optional User-defined signal in the write data channel.
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// }}}
// Write response channel
// {{{
// Response ID tag. This signal is the ID tag of the
// write response.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Optional User-defined signal in the write response channel.
// Write response valid. This signal indicates that the
// channel is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// }}}
// Read address channel
// {{{
// Read address ID. This signal is the identification
// tag for the read address group of signals.
input wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID,
// Read address. This signal indicates the initial
// address of a read burst transaction.
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Burst length. The burst length gives the exact number of
// transfers in a burst
input wire [7 : 0] S_AXI_ARLEN,
// Burst size. This signal indicates the size of each transfer
// in the burst
input wire [2 : 0] S_AXI_ARSIZE,
// Burst type. The burst type and the size information,
// determine how the address for each transfer within the
// burst is calculated.
input wire [1 : 0] S_AXI_ARBURST,
// Lock type. Provides additional information about the
// atomic characteristics of the transfer.
input wire S_AXI_ARLOCK,
// Memory type. This signal indicates how transactions
// are required to progress through a system.
input wire [3 : 0] S_AXI_ARCACHE,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Quality of Service, QoS identifier sent for each
// read transaction.
input wire [3 : 0] S_AXI_ARQOS,
// Region identifier. Permits a single physical interface
// on a slave to be used for multiple logical interfaces.
// Optional User-defined signal in the read address channel.
// Write address valid. This signal indicates that
// the channel is signaling valid read address and
// control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that
// the slave is ready to accept an address and associated
// control signals.
output wire S_AXI_ARREADY,
// }}}
// Read data (return) channel
// {{{
// Read ID tag. This signal is the identification tag
// for the read data group of signals generated by the slave.
output wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_RID,
// Read Data
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of
// the read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read last. This signal indicates the last transfer
// in a read burst.
output wire S_AXI_RLAST,
// Optional User-defined signal in the read address channel.
// Read valid. This signal indicates that the channel
// is signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
// }}}
// }}}
// }}}
);
// Local declarations
// {{{
// More useful shorthand definitions
localparam AW = C_S_AXI_ADDR_WIDTH;
localparam DW = C_S_AXI_DATA_WIDTH;
localparam IW = C_S_AXI_ID_WIDTH;
// Double buffer the write response channel only
reg [IW-1 : 0] r_bid;
reg r_bvalid;
reg [IW-1 : 0] axi_bid;
reg axi_bvalid;
reg axi_awready, axi_wready;
reg [AW-1:0] waddr;
wire [AW-1:0] next_wr_addr;
// Vivado will warn about wlen only using 4-bits. This is
// to be expected, since the axi_addr module only needs to use
// the bottom four bits of wlen to determine address increments
reg [7:0] wlen;
// Vivado will also warn about the top bit of wsize being unused.
// This is also to be expected for a DATA_WIDTH of 32-bits.
reg [2:0] wsize;
reg [1:0] wburst;
wire m_awvalid, m_awlock;
reg m_awready;
wire [AW-1:0] m_awaddr;
wire [1:0] m_awburst;
wire [2:0] m_awsize;
wire [7:0] m_awlen;
wire [IW-1:0] m_awid;
wire [AW-1:0] next_rd_addr;
// Vivado will warn about rlen only using 4-bits. This is
// to be expected, since for a DATA_WIDTH of 32-bits, the axi_addr
// module only uses the bottom four bits of rlen to determine
// address increments
reg [7:0] rlen;
// Vivado will also warn about the top bit of wsize being unused.
// This is also to be expected for a DATA_WIDTH of 32-bits.
reg [2:0] rsize;
reg [1:0] rburst;
reg [IW-1:0] rid;
reg rlock;
reg axi_arready;
reg [8:0] axi_rlen;
reg [AW-1:0] raddr;
// Read skid buffer
reg rskd_valid, rskd_last, rskd_lock;
wire rskd_ready;
reg [IW-1:0] rskd_id;
// Exclusive address register checking
reg exclusive_write, block_write;
wire write_lock_valid;
reg axi_exclusive_write;
// }}}
////////////////////////////////////////////////////////////////////////
//
// AW Skid buffer
// {{{
////////////////////////////////////////////////////////////////////////
//
//
skidbuffer #(
// {{{
.DW(AW+2+3+1+8+IW),
.OPT_LOWPOWER(OPT_LOWPOWER),
.OPT_OUTREG(1'b0)
// }}}
) awbuf(
// {{{
.i_clk(S_AXI_ACLK), .i_reset(!S_AXI_ARESETN),
.i_valid(S_AXI_AWVALID), .o_ready(S_AXI_AWREADY),
.i_data({ S_AXI_AWADDR, S_AXI_AWBURST, S_AXI_AWSIZE,
S_AXI_AWLOCK, S_AXI_AWLEN, S_AXI_AWID }),
.o_valid(m_awvalid), .i_ready(m_awready),
.o_data({ m_awaddr, m_awburst, m_awsize,
m_awlock, m_awlen, m_awid })
// }}}
);
// }}}
////////////////////////////////////////////////////////////////////////
//
// Write processing
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// axi_awready, axi_wready
// {{{
initial axi_awready = 1;
initial axi_wready = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
begin
axi_awready <= 1;
axi_wready <= 0;
end else if (m_awvalid && m_awready)
begin
axi_awready <= 0;
axi_wready <= 1;
end else if (S_AXI_WVALID && S_AXI_WREADY)
begin
axi_awready <= (S_AXI_WLAST)&&(!S_AXI_BVALID || S_AXI_BREADY);
axi_wready <= (!S_AXI_WLAST);
end else if (!axi_awready)
begin
if (S_AXI_WREADY)
axi_awready <= 1'b0;
else if (r_bvalid && !S_AXI_BREADY)
axi_awready <= 1'b0;
else
axi_awready <= 1'b1;
end
// }}}
// Exclusive write calculation
// {{{
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || !OPT_LOCK)
begin
exclusive_write <= 0;
block_write <= 0;
end else if (m_awvalid && m_awready)
begin
exclusive_write <= 1'b0;
block_write <= 1'b0;
if (write_lock_valid)
exclusive_write <= 1'b1;
else if (m_awlock)
block_write <= 1'b1;
end else if (m_awready)
begin
exclusive_write <= 1'b0;
block_write <= 1'b0;
end
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || !OPT_LOCK)
axi_exclusive_write <= 0;
else if (!S_AXI_BVALID || S_AXI_BREADY)
begin
axi_exclusive_write <= exclusive_write;
if (OPT_LOWPOWER && (!S_AXI_WVALID || !S_AXI_WREADY || !S_AXI_WLAST)
&& !r_bvalid)
axi_exclusive_write <= 0;
end
// }}}
// Next write address calculation
// {{{
always @(posedge S_AXI_ACLK)
if (m_awready)
begin
waddr <= m_awaddr;
wburst <= m_awburst;
wsize <= m_awsize;
wlen <= m_awlen;
end else if (S_AXI_WVALID)
waddr <= next_wr_addr;
axi_addr #(
// {{{
.AW(AW), .DW(DW)
// }}}
) get_next_wr_addr(
// {{{
waddr, wsize, wburst, wlen,
next_wr_addr
// }}}
);
// }}}
// o_w*
// {{{
always @(posedge S_AXI_ACLK)
begin
o_we <= (S_AXI_WVALID && S_AXI_WREADY);
o_waddr <= waddr[AW-1:LSB];
o_wdata <= S_AXI_WDATA;
if (block_write)
o_wstrb <= 0;
else
o_wstrb <= S_AXI_WSTRB;
if (!S_AXI_ARESETN)
o_we <= 0;
if (OPT_LOWPOWER && (!S_AXI_ARESETN || !S_AXI_WVALID
|| !S_AXI_WREADY))
begin
o_waddr <= 0;
o_wdata <= 0;
o_wstrb <= 0;
end
end
// }}}
//
// Write return path
// {{{
// r_bvalid
// {{{
initial r_bvalid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
r_bvalid <= 1'b0;
else if (S_AXI_WVALID && S_AXI_WREADY && S_AXI_WLAST
&&(S_AXI_BVALID && !S_AXI_BREADY))
r_bvalid <= 1'b1;
else if (S_AXI_BREADY)
r_bvalid <= 1'b0;
// }}}
// r_bid, axi_bid
// {{{
initial r_bid = 0;
initial axi_bid = 0;
always @(posedge S_AXI_ACLK)
begin
if (m_awready && (!OPT_LOWPOWER || m_awvalid))
r_bid <= m_awid;
if (!S_AXI_BVALID || S_AXI_BREADY)
axi_bid <= r_bid;
if (OPT_LOWPOWER && !S_AXI_ARESETN)
begin
r_bid <= 0;
axi_bid <= 0;
end
end
// }}}
// axi_bvalid
// {{{
initial axi_bvalid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axi_bvalid <= 0;
else if (S_AXI_WVALID && S_AXI_WREADY && S_AXI_WLAST)
axi_bvalid <= 1;
else if (S_AXI_BREADY)
axi_bvalid <= r_bvalid;
// }}}
// m_awready
// {{{
always @(*)
begin
m_awready = axi_awready;
if (S_AXI_WVALID && S_AXI_WREADY && S_AXI_WLAST
&& (!S_AXI_BVALID || S_AXI_BREADY))
m_awready = 1;
end
// }}}
// At one time, axi_awready was the same as S_AXI_AWREADY. Now, though,
// with the extra write address skid buffer, this is no longer the case.
// S_AXI_AWREADY is handled/created/managed by the skid buffer.
//
// assign S_AXI_AWREADY = axi_awready;
//
// The rest of these signals can be set according to their registered
// values above.
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_BID = axi_bid;
//
// This core does not produce any bus errors, nor does it support
// exclusive access, so 2'b00 will always be the correct response.
assign S_AXI_BRESP = { 1'b0, axi_exclusive_write };
// }}}
// }}}
////////////////////////////////////////////////////////////////////////
//
// Read processing
// {{{
////////////////////////////////////////////////////////////////////////
//
//
// axi_arready
// {{{
initial axi_arready = 1;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axi_arready <= 1;
else if (S_AXI_ARVALID && S_AXI_ARREADY)
axi_arready <= (S_AXI_ARLEN==0)&&(o_rd);
else if (o_rd)
axi_arready <= (axi_rlen <= 1);
// }}}
// axi_rlen
// {{{
initial axi_rlen = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
axi_rlen <= 0;
else if (S_AXI_ARVALID && S_AXI_ARREADY)
axi_rlen <= S_AXI_ARLEN + (o_rd ? 0:1);
else if (o_rd)
axi_rlen <= axi_rlen - 1;
// }}}
// Next read address calculation
// {{{
always @(posedge S_AXI_ACLK)
if (o_rd)
raddr <= next_rd_addr;
else if (S_AXI_ARREADY)
begin
raddr <= S_AXI_ARADDR;
if (OPT_LOWPOWER && !S_AXI_ARVALID)
raddr <= 0;
end
// r*
// {{{
always @(posedge S_AXI_ACLK)
if (S_AXI_ARREADY)
begin
rburst <= S_AXI_ARBURST;
rsize <= S_AXI_ARSIZE;
rlen <= S_AXI_ARLEN;
rid <= S_AXI_ARID;
rlock <= S_AXI_ARLOCK && S_AXI_ARVALID && OPT_LOCK;
if (OPT_LOWPOWER && !S_AXI_ARVALID)
begin
rburst <= 0;
rsize <= 0;
rlen <= 0;
rid <= 0;
rlock <= 0;
end
end
// }}}
axi_addr #(
// {{{
.AW(AW), .DW(DW)
// }}}
) get_next_rd_addr(
// {{{
(S_AXI_ARREADY ? S_AXI_ARADDR : raddr),
(S_AXI_ARREADY ? S_AXI_ARSIZE : rsize),
(S_AXI_ARREADY ? S_AXI_ARBURST: rburst),
(S_AXI_ARREADY ? S_AXI_ARLEN : rlen),
next_rd_addr
// }}}
);
// }}}
// o_rd, o_raddr
// {{{
always @(*)
begin
o_rd = (S_AXI_ARVALID || !S_AXI_ARREADY);
if (S_AXI_RVALID && !S_AXI_RREADY)
o_rd = 0;
if (rskd_valid && !rskd_ready)
o_rd = 0;
o_raddr = (S_AXI_ARREADY ? S_AXI_ARADDR[AW-1:LSB] : raddr[AW-1:LSB]);
end
// }}}
// rskd_valid
// {{{
initial rskd_valid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
rskd_valid <= 0;
else if (o_rd)
rskd_valid <= 1;
else if (rskd_ready)
rskd_valid <= 0;
// }}}
// rskd_id
// {{{
always @(posedge S_AXI_ACLK)
if (!rskd_valid || rskd_ready)
begin
if (S_AXI_ARVALID && S_AXI_ARREADY)
rskd_id <= S_AXI_ARID;
else
rskd_id <= rid;
end
// }}}
// rskd_last
// {{{
initial rskd_last = 0;
always @(posedge S_AXI_ACLK)
if (!rskd_valid || rskd_ready)
begin
rskd_last <= 0;
if (o_rd && axi_rlen == 1)
rskd_last <= 1;
if (S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARLEN == 0)
rskd_last <= 1;
end
// }}}
// rskd_lock
// {{{
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || !OPT_LOCK)
rskd_lock <= 1'b0;
else if (!rskd_valid || rskd_ready)
begin
rskd_lock <= 0;
if (!OPT_LOWPOWER || o_rd)
begin
if (S_AXI_ARVALID && S_AXI_ARREADY)
rskd_lock <= S_AXI_ARLOCK;
else
rskd_lock <= rlock;
end
end
// }}}
// Outgoing read skidbuffer
// {{{
skidbuffer #(
// {{{
.OPT_LOWPOWER(OPT_LOWPOWER),
.OPT_OUTREG(1),
.DW(IW+2+DW)
// }}}
) rskid (
// {{{
.i_clk(S_AXI_ACLK), .i_reset(!S_AXI_ARESETN),
.i_valid(rskd_valid), .o_ready(rskd_ready),
.i_data({ rskd_id, rskd_lock, rskd_last, i_rdata }),
.o_valid(S_AXI_RVALID), .i_ready(S_AXI_RREADY),
.o_data({ S_AXI_RID, S_AXI_RRESP[0], S_AXI_RLAST,
S_AXI_RDATA })
// }}}
);
// }}}
assign S_AXI_RRESP[1] = 1'b0;
assign S_AXI_ARREADY = axi_arready;
// }}}
////////////////////////////////////////////////////////////////////////
//
// Exclusive address caching
// {{{
////////////////////////////////////////////////////////////////////////
//
//
generate if (OPT_LOCK && !OPT_LOCKID)
begin : EXCLUSIVE_ACCESS_BLOCK
// {{{
// The AXI4 specification requires that we check one address
// per ID. This isn't that. This algorithm checks one ID,
// whichever the last ID was. It's designed to be lighter on
// the logic requirements, and (unnoticably) not (fully) spec
// compliant. (The difference, if noticed at all, will be in
// performance when multiple masters try to perform an exclusive
// transaction at once.)
// Local declarations
// {{{
reg w_valid_lock_request, w_cancel_lock,
w_lock_request,
lock_valid, returned_lock_valid;
reg [AW-LSB-1:0] lock_start, lock_end;
reg [3:0] lock_len;
reg [1:0] lock_burst;
reg [2:0] lock_size;
reg [IW-1:0] lock_id;
reg w_write_lock_valid;
// }}}
// w_lock_request
// {{{
always @(*)
begin
w_lock_request = 0;
if (S_AXI_ARVALID && S_AXI_ARREADY && S_AXI_ARLOCK)
w_lock_request = 1;
end
// }}}
// w_valid_lock_request
// {{{
always @(*)
begin
w_valid_lock_request = 0;
if (w_lock_request)
w_valid_lock_request = 1;
if (o_we && o_waddr == S_AXI_ARADDR[AW-1:LSB])
w_valid_lock_request = 0;
end
// }}}
// returned_lock_valid
// {{{
initial returned_lock_valid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
returned_lock_valid <= 0;
else if (S_AXI_ARVALID && S_AXI_ARREADY
&& S_AXI_ARLOCK && S_AXI_ARID== lock_id)
returned_lock_valid <= 0;
else if (w_cancel_lock)
returned_lock_valid <= 0;
else if (rskd_valid && rskd_lock && rskd_ready)
returned_lock_valid <= lock_valid;
// }}}
// w_cancel_lock
// {{{
always @(*)
w_cancel_lock = (lock_valid && w_lock_request)
|| (lock_valid && o_we
&& o_waddr >= lock_start
&& o_waddr <= lock_end
&& o_wstrb != 0);
// }}}
// lock_valid
// {{{
initial lock_valid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || !OPT_LOCK)
lock_valid <= 0;
else begin
if (S_AXI_ARVALID && S_AXI_ARREADY
&& S_AXI_ARLOCK && S_AXI_ARID== lock_id)
lock_valid <= 0;
if (w_cancel_lock)
lock_valid <= 0;
if (w_valid_lock_request)
lock_valid <= 1;
end
// }}}
// lock_start, lock_end, lock_len, lock_size, lock_id
// {{{
always @(posedge S_AXI_ACLK)
if (w_valid_lock_request)
begin
lock_start <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1:LSB];
lock_end <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1:LSB]
+ ((S_AXI_ARBURST == 2'b00) ? 0 : S_AXI_ARLEN[3:0]);
lock_len <= S_AXI_ARLEN[3:0];
lock_burst <= S_AXI_ARBURST;
lock_size <= S_AXI_ARSIZE;
lock_id <= S_AXI_ARID;
end
// }}}
// w_write_lock_valid
// {{{
always @(*)
begin
w_write_lock_valid = returned_lock_valid;
if (!m_awvalid || !m_awready || !m_awlock || !lock_valid)
w_write_lock_valid = 0;
if (m_awaddr[C_S_AXI_ADDR_WIDTH-1:LSB] != lock_start)
w_write_lock_valid = 0;
if (m_awid != lock_id)
w_write_lock_valid = 0;
if (m_awlen[3:0] != lock_len) // MAX transfer size is 16 beats
w_write_lock_valid = 0;
if (m_awburst != 2'b01 && lock_len != 0)
w_write_lock_valid = 0;
if (m_awsize != lock_size)
w_write_lock_valid = 0;
end
// }}}
assign write_lock_valid = w_write_lock_valid;
// }}}
end else if (OPT_LOCK) // && OPT_LOCKID
begin : EXCLUSIVE_ACCESS_PER_ID
// {{{
genvar gk;
wire [(1<<IW)-1:0] write_lock_valid_per_id;
for(gk=0; gk<(1<<IW); gk=gk+1)
begin : PER_ID_LOGIC
// {{{
// Local declarations
// {{{
reg w_valid_lock_request,
w_cancel_lock,
lock_valid, returned_lock_valid;
reg [1:0] lock_burst;
reg [2:0] lock_size;
reg [3:0] lock_len;
reg [AW-LSB-1:0] lock_start, lock_end;
reg w_write_lock_valid;
// }}}
// valid_lock_request
// {{{
always @(*)
begin
w_valid_lock_request = 0;
if (S_AXI_ARVALID && S_AXI_ARREADY
&& S_AXI_ARID == gk[IW-1:0]
&& S_AXI_ARLOCK)
w_valid_lock_request = 1;
if (o_we && o_waddr == S_AXI_ARADDR[AW-1:LSB])
w_valid_lock_request = 0;
end
// }}}
// returned_lock_valid
// {{{
initial returned_lock_valid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN)
returned_lock_valid <= 0;
else if (S_AXI_ARVALID && S_AXI_ARREADY
&&S_AXI_ARLOCK&&S_AXI_ARID== gk[IW-1:0])
returned_lock_valid <= 0;
else if (w_cancel_lock)
returned_lock_valid <= 0;
else if (rskd_valid && rskd_lock && rskd_ready
&& rskd_id == gk[IW-1:0])
returned_lock_valid <= lock_valid;
// }}}
// w_cancel_lock
// {{{
always @(*)
w_cancel_lock=(lock_valid&&w_valid_lock_request)
|| (lock_valid && o_we
&& o_waddr >= lock_start
&& o_waddr <= lock_end
&& o_wstrb != 0);
// }}}
// lock_valid
// {{{
initial lock_valid = 0;
always @(posedge S_AXI_ACLK)
if (!S_AXI_ARESETN || !OPT_LOCK)
lock_valid <= 0;
else begin
if (S_AXI_ARVALID && S_AXI_ARREADY
&& S_AXI_ARLOCK
&& S_AXI_ARID == gk[IW-1:0])
lock_valid <= 0;
if (w_cancel_lock)
lock_valid <= 0;
if (w_valid_lock_request)
lock_valid <= 1;
end
// }}}
// lock_start, lock_end, lock_len, lock_size
// {{{
always @(posedge S_AXI_ACLK)
if (w_valid_lock_request)
begin
lock_start <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1:LSB];
lock_end <= S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1:LSB]
+ ((S_AXI_ARBURST == 2'b00) ? 0 : S_AXI_ARLEN[3:0]);
lock_len <= S_AXI_ARLEN[3:0];
lock_size <= S_AXI_ARSIZE;
lock_burst <= S_AXI_ARBURST;
end
// }}}
// w_write_lock_valid
// {{{
always @(*)
begin
w_write_lock_valid = returned_lock_valid;
if (!m_awvalid || !m_awready || !m_awlock || !lock_valid)
w_write_lock_valid = 0;
if (m_awaddr[C_S_AXI_ADDR_WIDTH-1:LSB] != lock_start)
w_write_lock_valid = 0;
if (m_awid[IW-1:0] != gk[IW-1:0])
w_write_lock_valid = 0;
if (m_awlen[3:0] != lock_len) // MAX transfer size is 16 beats
w_write_lock_valid = 0;
if (m_awburst != 2'b01 && lock_len != 0)
w_write_lock_valid = 0;
if (m_awsize != lock_size)
w_write_lock_valid = 0;
end
// }}}
assign write_lock_valid_per_id[gk]= w_write_lock_valid;
// }}}
end
assign write_lock_valid = |write_lock_valid_per_id;
// }}}
end else begin : NO_LOCKING
// {{{
assign write_lock_valid = 1'b0;
// Verilator lint_off UNUSED
wire unused_lock;
assign unused_lock = &{ 1'b0, S_AXI_ARLOCK, S_AXI_AWLOCK };
// Verilator lint_on UNUSED
// }}}
end endgenerate
// }}}
// Make Verilator happy
// {{{
// Verilator lint_off UNUSED
wire unused;
assign unused = &{ 1'b0, S_AXI_AWCACHE, S_AXI_AWPROT, S_AXI_AWQOS,
S_AXI_ARCACHE, S_AXI_ARPROT, S_AXI_ARQOS };
// Verilator lint_on UNUSED
// }}}
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// Formal properties
// {{{
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
//
// The following properties are only some of the properties used
// to verify this core
//
reg f_past_valid;
initial f_past_valid = 0;
always @(posedge S_AXI_ACLK)
f_past_valid <= 1;
always @(*)
if (!f_past_valid)
assume(!S_AXI_ARESETN);
faxi_slave #(
// {{{