From 235e9592f9b4f2e59df0737c97fd0628faabb958 Mon Sep 17 00:00:00 2001 From: Paulo Matias Date: Thu, 4 Dec 2014 17:40:06 -0200 Subject: [PATCH] Add missing Quartus project files --- hw/AcqSys.qpf | 6 + hw/AcqSys.qsf | 70 ++++----- hw/PCIe_AvalonBSV.qsys | 312 +++++++++++++++++++++++++++++++++++++++++ hw/mkAcqSys_hw.tcl | 191 +++++++++++++++++++++++++ 4 files changed, 545 insertions(+), 34 deletions(-) create mode 100644 hw/AcqSys.qpf create mode 100644 hw/PCIe_AvalonBSV.qsys create mode 100644 hw/mkAcqSys_hw.tcl diff --git a/hw/AcqSys.qpf b/hw/AcqSys.qpf new file mode 100644 index 0000000..c60944d --- /dev/null +++ b/hw/AcqSys.qpf @@ -0,0 +1,6 @@ +DATE = "14:30:11 October 14, 2014" +QUARTUS_VERSION = "13.1" + +# Revisions + +PROJECT_REVISION = "AcqSys" diff --git a/hw/AcqSys.qsf b/hw/AcqSys.qsf index 96c2403..0bd0427 100644 --- a/hw/AcqSys.qsf +++ b/hw/AcqSys.qsf @@ -1,30 +1,30 @@ -#============================================================ -# Build by Terasic System Builder -#============================================================ - +#============================================================ +# Build by Terasic System Builder +#============================================================ + set_global_assignment -name FAMILY "Cyclone IV GX" set_global_assignment -name DEVICE EP4CGX150DF31C7 -set_global_assignment -name TOP_LEVEL_ENTITY "AcqSys" +set_global_assignment -name TOP_LEVEL_ENTITY "AcqSys" set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name LAST_QUARTUS_VERSION 14.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:34:45 OCTOBER 23,2014" set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 - -#============================================================ -# CLOCK -#============================================================ + +#============================================================ +# CLOCK +#============================================================ set_location_assignment PIN_AJ16 -to CLOCK_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 set_location_assignment PIN_A15 -to CLOCK2_50 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 set_location_assignment PIN_V11 -to CLOCK3_50 set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK3_50 - -#============================================================ -# LED (High Active) -#============================================================ + +#============================================================ +# LED (High Active) +#============================================================ set_location_assignment PIN_T23 -to LEDR[0] set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] set_location_assignment PIN_T24 -to LEDR[1] @@ -79,10 +79,10 @@ set_location_assignment PIN_AA22 -to LEDG[7] set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] set_location_assignment PIN_J25 -to LEDG[8] set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] - -#============================================================ -# KEY (Active Low) -#============================================================ + +#============================================================ +# KEY (Active Low) +#============================================================ set_location_assignment PIN_AA26 -to KEY[0] set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] set_location_assignment PIN_AE25 -to KEY[1] @@ -91,10 +91,10 @@ set_location_assignment PIN_AF30 -to KEY[2] set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] set_location_assignment PIN_AE26 -to KEY[3] set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] - -#============================================================ -# PCIe -#============================================================ + +#============================================================ +# PCIe +#============================================================ set_location_assignment PIN_V15 -to PCIE_REFCLK_P set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REFCLK_P set_location_assignment PIN_C29 -to PCIE_WAKE_N @@ -109,10 +109,10 @@ set_location_assignment PIN_Y4 -to PCIE_TX_P[1] set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_TX_P[1] set_location_assignment PIN_AA2 -to PCIE_RX_P[1] set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to PCIE_RX_P[1] - -#============================================================ -# GPIO, GPIO connect to GPIO Default -#============================================================ + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ set_location_assignment PIN_G16 -to GPIO[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] set_location_assignment PIN_F17 -to GPIO[1] @@ -185,17 +185,17 @@ set_location_assignment PIN_AG26 -to GPIO[34] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] set_location_assignment PIN_Y21 -to GPIO[35] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] - -#============================================================ -# Fan Control -#============================================================ + +#============================================================ +# Fan Control +#============================================================ set_location_assignment PIN_AF28 -to FAN_CTRL set_instance_assignment -name IO_STANDARD "2.5 V" -to FAN_CTRL - -#============================================================ -# End of pin assignments by Terasic System Builder -#============================================================ - + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name FITTER_EFFORT "STANDARD FIT" @@ -222,4 +222,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHZ +set_global_assignment -name SEARCH_PATH "/opt/bluespec/Bluespec-2014.06.A/lib/Verilog.Quartus" +set_global_assignment -name SEARCH_PATH "/opt/bluespec/Bluespec-2014.06.A/lib/Verilog" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/hw/PCIe_AvalonBSV.qsys b/hw/PCIe_AvalonBSV.qsys new file mode 100644 index 0000000..ec95d52 --- /dev/null +++ b/hw/PCIe_AvalonBSV.qsys @@ -0,0 +1,312 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 32 bit Non-Prefetchable,Not used,Not used,Not used,Not used,Not used + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 + 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/mkAcqSys_hw.tcl b/hw/mkAcqSys_hw.tcl new file mode 100644 index 0000000..edc526a --- /dev/null +++ b/hw/mkAcqSys_hw.tcl @@ -0,0 +1,191 @@ +# TCL File Generated by Component Editor 14.0 +# Thu Oct 23 11:52:32 BRST 2014 +# DO NOT MODIFY + + +# +# mkAcqSys "mkAcqSys" v1.0 +# 2014.10.23.11:52:32 +# +# + +# +# request TCL package from ACDS 14.0 +# +package require -exact qsys 14.0 + + +# +# module mkAcqSys +# +set_module_property DESCRIPTION "" +set_module_property NAME mkAcqSys +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME mkAcqSys +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL mkAcqSys +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file mkAcqSys.v VERILOG PATH mkAcqSys.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset_n reset_n Input 1 + + +# +# connection point interrupt_sender_0 +# +add_interface interrupt_sender_0 interrupt end +set_interface_property interrupt_sender_0 associatedAddressablePoint "" +set_interface_property interrupt_sender_0 associatedClock clock +set_interface_property interrupt_sender_0 associatedReset reset +set_interface_property interrupt_sender_0 bridgedReceiverOffset 0 +set_interface_property interrupt_sender_0 bridgesToReceiver "" +set_interface_property interrupt_sender_0 ENABLED true +set_interface_property interrupt_sender_0 EXPORT_OF "" +set_interface_property interrupt_sender_0 PORT_NAME_MAP "" +set_interface_property interrupt_sender_0 CMSIS_SVD_VARIABLES "" +set_interface_property interrupt_sender_0 SVD_ADDRESS_GROUP "" + +add_interface_port interrupt_sender_0 ins irq Output 1 + + +# +# connection point avalon_slave_0 +# +add_interface avalon_slave_0 avalon end +set_interface_property avalon_slave_0 addressUnits WORDS +set_interface_property avalon_slave_0 associatedClock clock +set_interface_property avalon_slave_0 associatedReset reset +set_interface_property avalon_slave_0 bitsPerSymbol 8 +set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false +set_interface_property avalon_slave_0 burstcountUnits WORDS +set_interface_property avalon_slave_0 explicitAddressSpan 0 +set_interface_property avalon_slave_0 holdTime 0 +set_interface_property avalon_slave_0 linewrapBursts false +set_interface_property avalon_slave_0 maximumPendingReadTransactions 2 +set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0 +set_interface_property avalon_slave_0 readLatency 0 +set_interface_property avalon_slave_0 readWaitTime 1 +set_interface_property avalon_slave_0 setupTime 0 +set_interface_property avalon_slave_0 timingUnits Cycles +set_interface_property avalon_slave_0 writeWaitTime 0 +set_interface_property avalon_slave_0 ENABLED true +set_interface_property avalon_slave_0 EXPORT_OF "" +set_interface_property avalon_slave_0 PORT_NAME_MAP "" +set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave_0 read read Input 1 +add_interface_port avalon_slave_0 write write Input 1 +add_interface_port avalon_slave_0 address address Input 12 +add_interface_port avalon_slave_0 writedata writedata Input 32 +add_interface_port avalon_slave_0 readdata readdata Output 32 +add_interface_port avalon_slave_0 waitrequest waitrequest Output 1 +add_interface_port avalon_slave_0 readdatavalid readdatavalid Output 1 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point status +# +add_interface status conduit end +set_interface_property status associatedClock clock +set_interface_property status associatedReset "" +set_interface_property status ENABLED true +set_interface_property status EXPORT_OF "" +set_interface_property status PORT_NAME_MAP "" +set_interface_property status CMSIS_SVD_VARIABLES "" +set_interface_property status SVD_ADDRESS_GROUP "" + +add_interface_port status LED led Output 10 + + +# +# connection point input +# +add_interface input conduit end +set_interface_property input associatedClock clock +set_interface_property input associatedReset "" +set_interface_property input ENABLED true +set_interface_property input EXPORT_OF "" +set_interface_property input PORT_NAME_MAP "" +set_interface_property input CMSIS_SVD_VARIABLES "" +set_interface_property input SVD_ADDRESS_GROUP "" + +add_interface_port input CH_0_IN ch0 Input 1 +add_interface_port input CH_1_IN ch1 Input 1 +add_interface_port input CH_2_IN ch2 Input 1 +add_interface_port input CH_3_IN ch3 Input 1 +add_interface_port input CH_4_IN ch4 Input 1 +add_interface_port input CH_5_IN ch5 Input 1 +add_interface_port input CH_6_IN ch6 Input 1 +add_interface_port input CH_7_IN ch7 Input 1 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end STIM stim Output 8 +