From c7323031427fdeda1ca2d890ab516d3fc07ff17c Mon Sep 17 00:00:00 2001 From: Aapo Naalisvaara Date: Wed, 9 Oct 2024 14:46:01 +0300 Subject: [PATCH] dts: Add tau device tree --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mp-epc-tau-rev1-u-boot.dtsi | 216 +++++ arch/arm/dts/imx8mp-epc-tau-rev1.dts | 860 +++++++++++++++++++ drivers/net/phy/phy.c | 2 + include/configs/imx8mp_evk.h | 2 +- 5 files changed, 1081 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx8mp-epc-tau-rev1-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-epc-tau-rev1.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7c0d445bbb3..48384bdb70a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1182,7 +1182,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-pico-pi.dtb \ imx8mq-kontron-pitx-imx8m.dtb \ imx8mq-librem5-r4.dtb \ - imx8mn-epc-som-rev2-base-rev3.dtb + imx8mn-epc-som-rev2-base-rev3.dtb \ + imx8mp-epc-tau-rev1.dtb dtb-$(CONFIG_ARCH_IMX9) += \ imx95-15x15-evk.dtb \ diff --git a/arch/arm/dts/imx8mp-epc-tau-rev1-u-boot.dtsi b/arch/arm/dts/imx8mp-epc-tau-rev1-u-boot.dtsi new file mode 100644 index 00000000000..445f45214b0 --- /dev/null +++ b/arch/arm/dts/imx8mp-epc-tau-rev1-u-boot.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019, 2021 NXP + */ +#include "imx8mp-sec-def.h" + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + + mcu_rdc { + compatible = "imx8m,mcu_rdc"; + /* rdc config when MCU starts + * master + * SDMA3p --> domain 1 + * SDMA3b --> domian 1 + * SDMA3_SPBA2 --> domian 1 + * peripheral: + * SAI3 --> Only Domian 1 can access + * UART4 --> Only Domian 1 can access + * GPT1 --> Only Domian 1 can access + * SDMA3 --> Only Domian 1 can access + * I2C3 --> Only Domian 1 can access + * memory: + * TCM --> Only Domian 1 can access (0x7E0000~0x81FFFF) + * DDR --> Only Domian 1 can access (0x80000000~0x81000000) + * end. + */ + start-config = < + RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0 + RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0 + RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 + RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 + RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0 + RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0 + RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS + RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS + 0x0 0x0 0x0 0x0 0x0 + >; + /* rdc config when MCU stops + * memory: + * TCM --> domain 0/1 can access (0x7E0000~0x81FFFF) + * DDR --> domain 0/1 can access (0x80000000~0x81000000) + * end. + */ + stop-config = < + RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS + RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS + 0x0 0x0 0x0 0x0 0x0 + >; + }; +}; + +&pinctrl_i2c1 { + bootph-all; +}; + +&pinctrl_i2c1_gpio { + bootph-all; +}; + +&pinctrl_pmic { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { + bootph-all; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + bootph-all; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; + u-boot,off-on-delay-us = <20000>; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&uart2 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-all; +}; + +&i2c2 { + bootph-pre-ram; +}; + +&i2c3 { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc2 { + bootph-pre-ram; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc3 { + bootph-pre-ram; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&wdog1 { + bootph-pre-ram; +}; + +ðphy0 { + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&fec { + phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&flexspi { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&media_blk_ctrl { + assigned-clock-rates = <500000000>, <200000000>; +}; + +&usb_dwc3_0 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&usb_dwc3_1 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; diff --git a/arch/arm/dts/imx8mp-epc-tau-rev1.dts b/arch/arm/dts/imx8mp-epc-tau-rev1.dts new file mode 100644 index 00000000000..61de86e551b --- /dev/null +++ b/arch/arm/dts/imx8mp-epc-tau-rev1.dts @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +// #include +#include +#include +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus LPDDR4 EVK board"; + compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; + + chosen { + bootargs = "console=ttymxc1,115200"; + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + // pcie0_refclk: pcie0-refclk { + // compatible = "fixed-clock"; + // #clock-cells = <0>; + // clock-frequency = <100000000>; + // }; + + // reg_can1_stby: regulator-can1-stby { + // compatible = "regulator-fixed"; + // regulator-name = "can1-stby"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_flexcan1_reg>; + // regulator-min-microvolt = <3300000>; + // regulator-max-microvolt = <3300000>; + // gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + // enable-active-high; + // }; + + // reg_can2_stby: regulator-can2-stby { + // compatible = "regulator-fixed"; + // regulator-name = "can2-stby"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_flexcan2_reg>; + // regulator-min-microvolt = <3300000>; + // regulator-max-microvolt = <3300000>; + // gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + // enable-active-high; + // }; + + // reg_pcie0: regulator-pcie { + // compatible = "regulator-fixed"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_pcie0_reg>; + // regulator-name = "MPCIE_3V3"; + // regulator-min-microvolt = <3300000>; + // regulator-max-microvolt = <3300000>; + // gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + // enable-active-high; + // regulator-always-on; + // }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + // reg_usb0_vbus: regulator-usb0-vbus { + // compatible = "regulator-fixed"; + // regulator-name = "USB1_VBUS_3V3"; + // regulator-max-microvolt = <3300000>; + // regulator-min-microvolt = <3300000>; + // }; + + // dsi_host: dsi-host { + // compatible = "samsung,sec-mipi-dsi"; + // status = "okay"; + // }; + + // rm67199_panel { + // compatible = "raydium,rm67199"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_mipi_dsi_en>; + // reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + // dsi-lanes = <4>; + // video-mode = <2>; /* 0: burst mode + // * 1: non-burst mode with sync event + // * 2: non-burst mode with sync pulse + // */ + // panel-width-mm = <68>; + // panel-height-mm = <121>; + // status = "okay"; + + // port { + // rm67191_from_dsim: endpoint { + // remote-endpoint = <&dsim_to_rm67191>; + // }; + // }; + // }; + + /* EVK: USB1_SS_SEL - removed */ + // cbtl04gp { + // compatible = "nxp,cbtl04gp"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_typec_mux>; + // switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + // orientation-switch; + + // port { + // usb3_data_ss: endpoint { + // remote-endpoint = <&typec_con_ss>; + // }; + // }; + // }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-id0007.0572"; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; /* ENET_nRST */ + reset-assert-us = <500>; + reset-deassert-us = <500>; + interrupt-parent = <&gpio4>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; /* ENET_nINT */ + vsc8531,led-0-mode = ; + vsc8531,led-1-mode = ; + vsc8531,led-0-combine-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-id0007.0572"; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; /* ENET1_nRST */ + reset-assert-us = <500>; + reset-deassert-us = <500>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; /* ENET1_nINT */ + vsc8531,led-0-mode = ; + vsc8531,led-1-mode = ; + vsc8531,led-0-combine-disable; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + // xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + // xceiver-supply = <®_can2_stby>; + // pinctrl-assert-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + status = "okay";/* can2 pin conflict with pdm */ +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + // adv_bridge: adv7535@3d { + // compatible = "adi,adv7535"; + // reg = <0x3d>; + // adi,addr-cec = <0x3c>; + // adi,dsi-lanes = <4>; + // status = "okay"; + + // port { + // adv7535_from_dsim: endpoint { + // remote-endpoint = <&dsim_to_adv7535>; + // }; + // }; + // }; + + /* EVK: PTN5110NHQZ - removed */ + // ptn5110: tcpc@50 { + // compatible = "nxp,ptn5110"; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_typec>; + // reg = <0x50>; + // interrupt-parent = <&gpio4>; + // interrupts = <19 8>; + // interrupts = <8>; + // reg = <0x50>; + + // port { + // typec_dr_sw: endpoint { + // remote-endpoint = <&usb3_drd_sw>; + // }; + // }; + + // /* EVK: USB1_SS_SEL - removed */ + // // ports { + // // #address-cells = <1>; + // // #size-cells = <0>; + + // // port@1 { + // // reg = <1>; + // // typec_con_ss: endpoint { + // // remote-endpoint = <&usb3_data_ss>; + // // }; + // // }; + // // }; + // }; + // }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + /* EVK: PCA6416AHF,128 - removed */ + // pca6416: gpio@20 { + // compatible = "ti,tca6416"; + // reg = <0x20>; + // gpio-controller; + // #gpio-cells = <2>; + // interrupt-controller; + // #interrupt-cells = <2>; + // pinctrl-names = "default"; + // pinctrl-0 = <&pinctrl_pca6416_int>; + // interrupt-parent = <&gpio1>; + // interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + // gpio-line-names = "EXT_PWREN1", + // "EXT_PWREN2", + // "CAN1/I2C5_SEL", + // "PDM/CAN2_SEL", + // "FAN_EN", + // "PWR_MEAS_IO1", + // "PWR_MEAS_IO2", + // "EXP_P0_7", + // "EXP_P1_0", + // "EXP_P1_1", + // "EXP_P1_2", + // "EXP_P1_3", + // "EXP_P1_4", + // "EXP_P1_5", + // "EXP_P1_6", + // "EXP_P1_7"; + // }; +}; + +// /* I2C on expansion connector J22. */ +// &i2c5 { +// clock-frequency = <100000>; /* Lower clock speed for external bus. */ +// pinctrl-names = "default"; +// pinctrl-0 = <&pinctrl_i2c5>; +// status = "disabled"; /* can1 pins conflict with i2c5 */ + +// /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: +// * LOW: CAN1 (default, pull-down) +// * HIGH: I2C5 +// * You need to set it to high to enable I2C5 (for example, add gpio-hog +// * in pca6416 node). +// */ +// }; + +// &lcdif1 { +// status = "okay"; +// }; + +// &mipi_dsi { +// status = "okay"; + + // ports { + // port@1 { + // dsim_to_adv7535: endpoint { + // remote-endpoint = <&adv7535_from_dsim>; + // }; + // }; + + // port@2 { + // dsim_to_rm67191: endpoint { + // remote-endpoint = <&rm67191_from_dsim>; + // }; + // }; + // }; +// }; + +// &pcie_phy { +// fsl,refclk-pad-mode = ; +// clocks = <&pcie0_refclk>; +// clock-names = "ref"; +// status = "okay"; +// }; + +// &pcie { +// pinctrl-names = "default"; +// pinctrl-0 = <&pinctrl_pcie0>; +// reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; +// clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, +// <&clk IMX8MP_CLK_PCIE_ROOT>, +// <&clk IMX8MP_CLK_HSIO_AXI>; +// clock-names = "pcie", "pcie_aux", "pcie_bus"; +// assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; +// assigned-clock-rates = <10000000>; +// assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; +// vpcie-supply = <®_pcie0>; +// status = "okay"; +// }; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + // fsl,phy-tx-vref-tune = <0xe>; + // fsl,phy-tx-preemp-amp-tune = <3>; + // fsl,phy-tx-vboost-level = <5>; + // fsl,phy-comp-dis-tune = <7>; + // fsl,pcs-tx-deemph-3p5db = <0x21>; + // fsl,phy-pcs-tx-swing-full = <0x7f>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x29 /* ENET_nINT */ + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x10 /* ENET_nRST */ + + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x29 /* ENET1_nINT */ + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x10 /* ENET1_nRST */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 + >; + }; + + // pinctrl_mipi_dsi_en: mipidsiengrp { + // fsl,pins = < + // MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + // >; + // }; + + // pinctrl_pcie0: pcie0grp { + // fsl,pins = < + // MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */ + // MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 + // MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c4 + // >; + // }; + + // pinctrl_pcie0_reg: pcie0reggrp { + // fsl,pins = < + // MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 + // >; + // }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + // pinctrl_pca6416_int: pca6416_int_grp { + // fsl,pins = < + // MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ + // >; + // }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 + >; + }; + + /* EVK: TCPC_nINT1 - removed*/ + // pinctrl_typec: typec1grp { + // fsl,pins = < + // MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + // >; + // }; + + /* EVK: USB1_SS_SEL - removed */ + // pinctrl_typec_mux: typec1muxgrp { + // fsl,pins = < + // MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + // >; + // }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + /* EVK: USB2_PWR - removed */ + // pinctrl_usb1_vbus: usb1grp { + // fsl,pins = < + // MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x10 + // >; + // }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 63b3e46f101..15d5279b0e1 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -24,6 +24,8 @@ #include #include +#define LOG_DEBUG + DECLARE_GLOBAL_DATA_PTR; /* Generic PHY support and helper functions */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 9d34c54d66d..1c25f870fe4 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) -#define CFG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 0 #define PHY_ANEG_TIMEOUT 20000